KR20120080019A - System and the method for measuring dependability of embedded systems using hybrid fault injection - Google Patents

Abstract

PURPOSE: A system for measuring the reliability of an embedded system using hybrid fault injection and a method for the same are provided to verify the influence of errors to the system by separating the system into parts and injecting the errors into a desired part. CONSTITUTION: A target system(100) includes the following: a simulation model part(110) is designed based on the hardware description language of an electronic system level or a register transfer level; a hardware part(130) includes at least one of a processor, a memory, a communication module, a network module, an input/output module, and a controller; a software part(150) drives the hardware part by being loaded on the memory; and a communication interface part synchronizes time or data with the simulation model part, the hardware part, and the software part.

Description

System and method for measuring dependability of embedded systems using hybrid fault injection

The present invention relates to a system and method for measuring reliability of an embedded system using integrated error injection, and more particularly, to configure an integrated embedded system including hardware, software, physical components and hardware simulation models, The present invention relates to a system and method for measuring the reliability of an embedded system by performing an error injection test, analyzing the results of the error injection test, analyzing a failure rate of an integrated embedded system, and measuring reliability. .

Embedded system (Embedded system) is a computer system that performs only a special function by embedding the software that operates the system in hardware, and has a specific requirement, unlike a personal computer (PC), and predefined tasks Only carry.

Among other applications, high reliability embedded systems used in automotive, railroad, aviation, nuclear, military, power generation, chemical plants, etc. require much higher operational reliability than conventional embedded systems. In particular, when the embedded system is used in the converged IT field that is fused with traditional industries such as power, shipbuilding, and chemical engineering, the reliability of the target converged IT system is very important because a large-scale human accident occurs when a failure occurs. The reason for the failure is that it is impossible to design with 100% consideration of the internal and external design requirements in the design process of the target embedded system. In particular, the design requirements may be changed or added later in the product development cycle. It is difficult to reflect all the requirements and design specifications of the product to be manufactured from the initial development of the product. For this reason, it is essential to quantitatively evaluate the reliability of embedded systems.

Although many studies have been conducted on the method of measuring the reliability of an embedded system at home and abroad, there is no technology for measuring the reliability at present, and there is a testing technique to improve the reliability. Testing techniques generally include unit testing performed at the design stage and integrated testing performed after integrating the unit modules.

The purpose of such testing is to verify the target specification of the identified design and the function of the specification. The integrity of the design specification can be verified, but there is a problem that the lifetime after the product is released, such as reliability. .

For example, in software testing, IT products typically perform unit testing and integration testing from the design stage before bringing the product to market in order to maintain high quality. However, the purpose of this testing is to verify whether the developed program performs the functions indicated by the target specification of the design. Software testing can play a role in minimizing the number of errors and improving the life of the product. It is impossible to predict.

Therefore, design elements that are not considered cannot be verified by testing, which is possible to improve reliability but is different from finally verifying reliability.

On the other hand, there are three ways to ensure the reliability of the embedded system as a previous step for measuring the reliability of the embedded system. The first is to verify by using the formal method. This method is to verify the function of the embedded system by modeling the system logically and verifying the converted logical expression. This method needs to develop the logic of the development target embedded system, which has a problem that the conversion is not easy because the requirements and specifications of the general embedded system are very complicated.

Moreover, understanding and using logic expressions is difficult for general beginners and intermediate engineers to perform, and there is a problem that a general software developer draws a logic expression using requirements and specifications.

For these reasons, orthopedic techniques have been proposed for decades, but their application to actual system development is only possible in special cases, and only in part during the development of very high-risk systems.

In this trend, the formal technique is continuously developing, but the complexity of the design requirements of the developed product also increases, so verification using the formal technique is not expected to be easy in the future.

The second method is such as probabilistic safety assessment or probabilistic risk assessment. This method is widely used in the design of high reliability embedded systems, especially in the field of nuclear power generation. The failure rate is analyzed using fault tree analysis, which analyzes the use conditions of the high reliability embedded system and the risk of every detail event. Probability is determined.

In this method, the risk of every detail event must be analyzed one by one. The high-reliability embedded system is very complex and has many components. As a result, the task of developing fault trees for every detail event becomes very large, and it is very difficult to complete such tasks within months of general development.

In addition, in order to determine the risk of each detailed event, it is necessary to set the risk of the basic events that are components of the detailed events, and the task of setting the risk of the basic events is subjective or empirical rather than objective. Therefore, the result obtained by statistically treating risk can be used as a guideline, but it is difficult to quantitatively evaluate the reliability.

The third method is reliability evaluation method using fault injection method, which is used to understand the probability of error in embedded system, and according to the object of error injection, physical fault injection method and hardware error. It is classified into hardware fault injection and software fault injection.

Physical error injection technique is a method of analyzing a failure state by injecting an error into a real product, and hardware error injection technique is a method of injecting an error directly into a target embedded hardware or board and analyzing a failure state of a system. Although these two methods can inject errors that are very similar to the actual situation, the results of the failure analysis can be trusted. However, when accurate observation of the change in the internal state caused by errors is required, it is already commercialized to observe the inside. The disadvantage is that it is impossible or very difficult to analyze.

The software error injection technique has an advantage that it can be easily tested because it injects an error into the software, but when a physical error occurs, it is difficult to experiment by reflecting it in an error model.

Simulation error injection is a method of designing a target system as a simulation model and injecting the error into the design model to analyze the effects of the error. This technique has the advantage of easy control for injecting errors and analysis of changes in the internal state of the system due to errors.However, when all the components of the system are developed as a simulation model, the time and cost are greatly increased. have.

In general, the reliability evaluation of a high reliability embedded system evaluates reliability in units of 0.01% or 0.001%, so a very large number of tests (for example, 100,000 or 1 million times) must be performed, and each test is performed for each error model. Should be. Therefore, in order to evaluate the reliability of an embedded system, it takes several years to test the reliability of the embedded system.

In addition, the simulation error injection method includes a model-based error injection method and a kernel-based error injection method. In the model-based error injection method, a user injects an error by changing a design model. However, if the design model is very complex, such as recent products, it is very difficult to redesign the finished product for reliability testing. Moreover, if the source code of the design model is not provided due to cost or trade secret, etc. There was a problem of paying a very high cost to secure the source code.

On the other hand, since the kernel-based error injection technique injects the error directly into the design model, there is no need to change the design model, and it is possible to inject the error only by setting the error model to be tested without additional coding for error injection testing. .

However, most of the conventional simulation error injection techniques require an integrated error injection technique using a kernel-based error injection technique as a model-based error injection technique.

The present invention was created to solve the above-mentioned problems, and is an integrated system using integrated error injection that maximizes its merits by fusing methods of physical error injection, hardware error injection, software error injection and simulation error injection. It is an object of the present invention to provide a system and method for measuring reliability.

In addition, the present invention is to measure the reliability of the embedded system using the integrated error injection to develop the reliability evaluation index of the embedded system that can be utilized by engineers in the field to solve the above problems and quantitatively estimate the reliability. Another object is to provide a system and method thereof.

The system for measuring the reliability of the embedded system using the integrated error injection according to the present invention for achieving the above object, by setting the target system and the error injection scenario to be subjected to the error injection test to perform the error injection to the target system. The error injection test unit and the result of the error injection test unit is compared with the results of the normal test to extract a failure rate of the target system includes a reliability measuring unit for measuring the reliability.

The target system may include a simulation model unit and a processor, memory, communication module, network module, input / output module, or the like, which are designed using a hardware description language of an electronic system level (ESL) or a register transfer level (RTL). It may include a hardware unit including at least one of the control unit and a software unit loaded in the memory to drive the hardware unit, and a communication interface unit for synchronizing the time or data for the simulation model unit, the hardware unit and the software unit in synchronization. have.

In addition, the target system may further include a simulation driving board capable of driving the simulation model unit.

The error injection test unit may perform error injection into the simulation kernel of the hardware unit through the simulation model unit, and evaluate an operation characteristic due to an error injected into the simulation model unit through the hardware unit.

In addition, the error injection test unit may include a user interface for setting an error injection scenario for the error injection test. The error injection scenario may determine an error to be injected into the target system according to at least one of an error occurrence time, an error occurrence location, an error occurrence type, or an error occurrence frequency, and further include determining an error injection number. can do.

The number of error injections may be performed by performing a predetermined error test prior to a predetermined initial test number, and determining a failure rate according to the statistical method, and the result of the error injection test part is a log of the error injection test part of the error injection test part. It may include at least one of file history, communication history history or memory history history.

In addition, the reliability measuring unit calculates the failure rate using the result of the error injection test unit to compare the failure rate distribution function type, or by using the Monte Carlo method or the maximum likelihood method to estimate the failure rate function λ (t), the failure rate function λ The reliability can be measured by substituting (t) for the reliability differential equation.

On the other hand, the method for measuring the reliability of the embedded system using the integrated error injection according to the present invention for achieving the above object comprises the steps of (a) manufacturing a target system for the object of the error injection test and (b) error injection test Obtaining an error number of injections and measuring the reliability by performing integrated error injection on the target system by the number of error injections.

The target system includes a simulation model unit and a processor, a memory, a communication module, a network module, an input / output module, or a simulation model unit designed using a hardware description language of an electronic system level (ESL) or a register transfer level (RTL). It may include a hardware unit including at least one of the control unit and a software unit loaded in the memory to drive the hardware unit, and a communication interface unit for synchronizing the time or data for the simulation model unit, the hardware unit and the software unit in synchronization. have.

In addition, the error injection frequency is performed by performing a preceding error injection test by a predetermined initial test number, and converts the result of the preceding error injection test including a failure rate into a normal distribution. By extracting a confidence interval that satisfies a predetermined confidence level, it may be a derived number that satisfies the confidence interval.

According to the system and method for measuring the reliability of the embedded system using the integrated error injection according to the present invention,

First, the embedded system of complex structure can be divided into physical parts, hardware parts, software parts, and simulation parts, and errors can be injected into the desired parts to understand the effects of the system due to the errors.

Second, by integrating various error injection techniques, the gap between the results of the reliability test and the value of the variable that occurs when the target embedded system is used in the field is minimized.

Third, by integrating various error injection techniques, the advantages of each error injection technique such as ease of observation, ease of analysis, ease of control, reliability of test results, and ease of testing can be maximized.

Fourth, the lead error injection test variable is derived through the preceding error injection test, the variables are analyzed using the estimation method of statistics, and the reliability test corresponding to the life cycle is performed using the accelerated test method to estimate the objective reliability. This is possible.

Fifth, in the simulation error injection test, the simulation model can use ESL (Electronic Systems Level) and RTL (Register Transaction Level) separately or integratedly, so it does not depend on a specific design method or design tool.

Sixth, the usefulness and usefulness of the results can be improved by applying existing statistical estimation theory in the analysis of experimental data. That is, the objective validity of the test variable values and the result values is statistically guaranteed, so that the test results can be easily applied to field work.

1 is a configuration diagram of a system for measuring reliability of an embedded system using integrated error injection.
2 is an embodiment of a system for measuring the reliability of an embedded system using integrated error injection.
3 is a flowchart of a method of measuring the reliability of an embedded system using integrated error injection.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms, and the inventor should appropriately interpret the concepts of the terms appropriately The present invention should be construed in accordance with the meaning and concept consistent with the technical idea of the present invention.

Therefore, the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention. Therefore, It is to be understood that equivalents and modifications are possible.

1 is a configuration diagram of a system for measuring reliability of an embedded system using integrated error injection, and FIG. 2 illustrates an embodiment of a system for measuring reliability of an embedded system using integrated error injection, FIGS. 1 and 2. The following describes a system for measuring the reliability of an embedded system using integrated error injection.

The embedded system using the integrated error injection includes a target system 100 that is a target of the error injection test, an error injection test unit 200 for performing error injection on the target system 100 by setting an error injection scenario, and the error injection. Comparing and analyzing the results of the error property DB (DataBase, 400), simulation option DB (500) and the error injection test unit 200 that stores the data for injecting errors in the test unit 200 with the results of the normal test And a reliability measuring unit 300 extracting reliability by extracting a failure rate of the target system.

The target system 100 includes a simulation model unit 110, a hardware unit 130, a software unit 150, a communication interface unit 170, and a simulation driver 190.

The simulation model unit 110 uses a hardware description language of an electronic system level (ESL-Electronic Systems Level) such as SystemC, HandelC or SystemVerilog, or a hardware description language of a register transfer level (RTL-Register Transfer Level) such as Verilog or VHDL. The simulation model is designed to run on a workstation.

However, when the simulation model 110 executes a simulation on a workstation, the performance of the workstation, the complexity of the simulation model, and a long simulation time may be a problem in the experiment time. Therefore, in this case, an accelerator board or a hardware emulator board is used to drive the simulation model in the simulation driver 190.

The hardware unit 130 includes at least one of a processor, a memory, a communication module, a network module, and an input / output module, and other devices including temperature, humidity, position sensors, a motor, an engine, and a controller for controlling the devices. can do.

The software unit 150 is loaded into the memory to drive the hardware unit 130.

The communication interface unit 170 synchronizes time or data with respect to the simulation model unit 110, the hardware unit 130, and the software unit 150. For example, when the simulation model is designed in the ESL design language by the simulation model unit 110, data conversion for transmitting output data of the simulation model to the hardware unit 130 is required. The BFM (Bus Function Model) recognizes the simulation output data in the hardware unit 130 and controls it so as not to collide with other hardware tasks. In addition, the communication interface 170 may include a separate interface board for physical connection between the workstation driving the simulation model and the hardware unit 130. As such, in the configuration of the communication interface unit 170, a wrapper, a message communication, or a shared memory may be used.

The target system to be subjected to the integrated error injection test, such as the target system 100, does not individually use the outputs generated in the development process and the development result like the existing reliability test methods, but uses hardware, machine parts, software, It is an integrated system of simulation models. Therefore, there is an advantage that the gap between the result value generated when the developed embedded system product is used in the field and the predicted result of the reliability test can be minimized.

The error injection test unit 200 performs error injection into the simulation kernel of the hardware unit 130 through the simulation model unit 110 with reference to the error property DB 400 and the simulation option DB 500. . As such, when the integrated error injection test is performed using the kernel-based error injection method, error observability increases compared to the existing error injection method, thereby enabling rapid and accurate test. In other words, the impact of each injected error can be seen directly on all components of the system, for example, in hardware and physical parts, resulting in more accurate analysis results than previous methods. This has the advantage of minimizing the gap between the results.

In addition, if the integrated error injection method is performed using the kernel-based error injection method, the test object is easier to manufacture than the existing error injection method, thereby enabling rapid and accurate experiments. That is, when developing each component, it is possible to construct a product regardless of the form of the component. For example, a microprocessor can use physical components in chips, a simulation model written in a hardware description language such as verilog, or a microprocessor simulation software. Therefore, there is an advantage that the limitation of the model making is reduced and the test model can be produced quickly.

In addition, if the integrated error injection test is performed using the kernel-based error injection method, the repeatability of the error injection test is higher than that of other methods, and thus, a rapid and accurate test result can be obtained. Hardware fault injection injects hardware into the failure and the model can no longer be reused. However, in the integrated error injection test, if the failure occurs in the simulation model rather than the hardware model, the test model can be reused even if the failure occurs in the test model. Therefore, there are advantages that can be tested quickly by reducing various restrictions that occur during model making.

In addition, the error injection test unit 200 evaluates the operation characteristics due to the error injected by the simulation model unit 110 through the hardware unit 130. That is, the test object is divided into a hardware part and a simulation part to inject an error into the simulation part, and the operation characteristics caused by the error are evaluated through the hardware part to confirm the reliability of the system. In this case, the simulation model unit 110 is preferably a model in which a hardware simulation model (ESL / RTL) and application software are integrated.

Error injection into the simulation model unit 110 may be applied differently according to the hardware description language. For example, SystemC (IEEE 1666) simulation model, a hardware design language based on C ++, uses SystemC-Based Simulation Fault Injection (SyFI), and Verilog-based Simulation Fault Injection (VSFI) error when using Verilog HDL. It can be used as an injection test device and an error injection test method using the same.

And a user interface unit 210 for setting an error injection scenario for the error injection test.

The error injection scenario determines an error to be injected into the target system 100 according to at least one criterion of an error occurrence time, an error occurrence location, an error occurrence type, or an error occurrence frequency. The error occurrence time may be error-injected in a crystalline or random form, the error occurrence position may be error-injected in a crystalline or random form, and the error occurrence type may be stuck-at-0 / 1, stuck-at-multi-bit Error injection is possible in the form of at least one of -0/1, open / short fault, bridge fault, and the frequency of error occurrence can be error injection in the form of temporary error, continuous error, periodic recurrence error, aperiodic recurrent flow, etc. .

The error injection scenario also includes determining the number of error injections. The number of error injections is performed by performing a previous error injection test a predetermined number of initial tests, and determining the failure rate according to the statistical method.

The reliability measuring unit 300 calculates a failure rate using the result of the error injection test unit 200 and compares the failure rate distribution function types, or estimates the failure rate function λ (t) using Monte Carlo technique or the maximum likelihood technique. Then, the failure rate function lambda (t) is substituted into the reliability differential equation to measure the reliability. In this case, the result of the error injection test may include at least one of a log file history, a communication history, or a memory history by the error injection test of the error injection test unit 200.

3 is a flowchart illustrating a method of measuring the reliability of an embedded system using integrated error injection. Referring to FIG. 3, a method of measuring the reliability of an embedded system using integrated error injection will be described.

First, a target system to be subjected to an error injection test is manufactured (S10), and an error injection count of the error injection test is obtained (S20), and then integrated error injection is performed on the target system as much as the error injection count to measure reliability. (S30).

The target system includes a simulation model unit and a processor, a memory, a communication module, a network module, an input / output module, or a simulation model unit designed using a hardware description language of an electronic system level (ESL) or a register transfer level (RTL). A hardware unit including at least one of the control unit and a software unit loaded in the memory to drive the hardware unit, and a communication interface unit for synchronizing the time or data for the simulation model unit, the hardware unit and the software unit in synchronization.

The simulation model of the simulation model unit is preferably a part designed with Verilog or VHDL, which is a register transfer level tool, which is a kind of hardware description language that uses a simulator running on a small computer and corresponds to a part or whole circuit of hardware. . For example, you can design microprocessor models with Verilog and synthesize them into FPGAs / PLDs. In addition, since FPGA / PLD synthesizes a module that connects a simulation model and a board, if a simulation module is a processor and a communication module is used on a board, the FPGA / PLD synthesizes a bus functional module or a wrapper in the FPGA / PLD. Communication module can be connected.

However, if the processor simulation model cannot be used because the processor or memory must use hardware in chip, one of the components of the other hardware is designed and used in HDL. For example, a supervisory module is designed in HDL on the bus between the processor and memory and a simulation model is constructed.

As such, the target system is an integrated embedded system in which hardware, software, physical components, and simulation models are connected.

On the other hand, obtaining the error injection frequency of the error injection test for the target system is important for deriving a reliable result. Therefore, when the production of the target system to be subjected to the error injection test (S10) is completed, the error injection frequency is obtained (S20).

The error injection frequency is performed by performing a preceding error injection test by a predetermined initial test number, and converting the execution result of the preceding error injection test including a failure rate into a normal distribution. A confidence interval that satisfies a predetermined confidence level is extracted, and is a derived number that satisfies the confidence interval.

In other words, a kernel-based error injection technique first performs an advanced error injection test using the target system. Initially, the parameters of the error injection test, such as test duration and test error, are not known. Therefore, we set the initial test frequency for the well-known error model (e.g. stuck-at-1 / 0, bridge) and execute it accordingly, and calculate the error rate by calculating the failure rate statistically.

이라고 할 수 있다. 이러한 신뢰수준을 만족하는 상한 및 하한 통계량이 정해지면, 설정된 신뢰수준을 만족하는 오류주입횟수 n을 도출할 수 있다. 이 오류주입횟수만큼 시험을 반복하여 고장률 결과를 얻을 수 있다. In the process of calculating the error injection frequency, when the previous error injection test is completed, the test result such as the failure rate is converted into a normal distribution, and then the specified confidence level is satisfied when the sample mean is x, the number n and the variance are σ ^2. The statistics for the upper and lower bounds of the confidence interval

It can be said. If the upper limit and the lower limit statistics satisfying the confidence level are determined, the number of error injections n satisfying the set confidence level can be derived. The failure rate results can be obtained by repeating the test for this number of error injections.

In the step (S30) of measuring the reliability by performing the integrated error injection as much as the error injection frequency in the target system, the reliability is measured by substituting the failure rate function λ (t) into the reliability differential equation. In general, the failure rate λ and the reliability R (t) have a relationship as shown in Equation 1 below.

R (t), a solution of Equation 1, is equal to Equation 2.

In this case, the failure rate function λ (t) in a general service period that has sufficiently passed the initial state of a general product is generally a constant, so when λ is substituted instead of λ (t), the reliability R (t) is expressed by Equation 3 below.

The reliability of the target system is calculated using Equation 3 above.

On the other hand, the method for measuring the reliability of the embedded system using the integrated error injection according to the present invention is easy to control the overall error injection test, the accelerated life test is possible as an embodiment using this method. Accelerated life tests can be configured in two ways:

Firstly, the stress count increase technique is a method of performing the error injection test by fixing the preceding and accelerated life test periods and increasing the number of stresses that are injected between the periods.

Second, as a test period compressor method, this method converts the number of errors that occurred in the preceding life test period into an appropriate value for the compressed life test period, and then injects the changed number of errors during the compressed life test period to accelerate the life. Perform a fault injection test.

Using these methods, the failure rate test results in the accelerated life test environment are obtained, and the reliability R (t) is calculated using the above Equation 3 using them.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

100 target system 110 simulation model part
130 Hardware Section 150 Software Section
170 Communication Interface 190 Simulation Drive Board
200 Error injection test unit 210 User interface unit
300 Reliability Measurement Unit 400 Error Property DB
500 Simulation Option DB

Claims (13)

A target system subject to the error injection test;
An error injection test unit configured to set an error injection scenario and perform error injection on the target system; And
And a reliability measuring unit which compares and analyzes a result of the error injection test unit with a result of a normal test to extract a failure rate of the target system to measure reliability. The method of claim 1,
The target system,
A simulation model unit designed using a hardware description language of an electronic systems level (ESL) or a register transfer level (RTL);
A hardware unit including at least one of a processor, a memory, a communication module, a network module, an input / output module, and a controller;
A software unit loaded in the memory to drive the hardware unit; And
And a communication interface unit for synchronizing time or data with respect to the simulation model unit, the hardware unit, and the software unit. The system for measuring the reliability of an embedded system using integrated error injection. The method of claim 2,
The target system,
And a simulation driving board capable of driving the simulation model unit. The system for measuring the reliability of an embedded system using integrated error injection. The method of claim 2,
The error injection test unit,
System for measuring the reliability of the embedded system using the error injection, characterized in that for performing the error injection to the simulation kernel of the hardware unit through the simulation model. The method of claim 2,
The error injection test unit,
The system for measuring the reliability of the embedded system using the error injection, characterized in that for evaluating the operation characteristics due to the error injected into the simulation model unit through the hardware unit. The method of claim 1,
The error injection test unit,
And a user interface configured to set an error injection scenario for the error injection test. The method of claim 1,
The error injection scenario,
The system for measuring the reliability of the embedded system using the error injection, characterized in that for determining the error to be injected into the target system according to at least one of the error occurrence time, error occurrence location, error occurrence type or error occurrence frequency. The method of claim 7, wherein
The error injection scenario,
Determining the number of error injections,
The error injection number is,
A system for measuring the reliability of an embedded system using an error injection, characterized in that for performing a preceding error injection test a predetermined number of initial test, and determine the failure rate according to the statistical method. The method of claim 1,
The result of the error injection test unit,
System for measuring the reliability of the embedded system using the error injection, characterized in that it comprises at least one of the log file history, communication record history or memory record history by the error injection test of the error injection test. The method of claim 9,
The reliability measuring unit,
Calculate the failure rate using the result of the error injection test unit, compare the failure rate distribution function types, or estimate the failure rate function λ (t) using Monte Carlo method or the maximum likelihood method, and calculate the reliability rate function λ (t) A system for measuring the reliability of an embedded system using error injection characterized in that the reliability is measured by substituting the equation. (a) manufacturing a target system to be subjected to the error injection test;
(b) obtaining the error injection frequency of the error injection test; And
(c) measuring reliability by executing integrated error injection on the target system by the number of error injection times. The method of claim 11,
The target system,
A simulation model unit designed using a hardware description language of an electronic systems level (ESL) or a register transfer level (RTL);
A hardware unit including at least one of a processor, a memory, a communication module, a network module, an input / output module, and a controller;
A software unit loaded in the memory to drive the hardware unit; And
And a communication interface unit for synchronizing time or data with respect to the simulation model unit, the hardware unit, and the software unit. 7. The method of claim 11,
The error injection frequency is
Performing a preceding error injection test by a predetermined initial test number, and converting the preceding error injection test execution result including a failure rate into a normal distribution. And extracting a confidence interval that satisfies a predetermined confidence level, and determining a reliability interval of the embedded system using integrated error injection.

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