KR20120079738A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to secure read margin by controlling verification reference values and a read reference current value according to the change of an operational temperature. CONSTITUTION: A temperature sensing unit(110) generates a temperature sensing signal by sensing an operational temperature. A current control unit(120) generates a read current control signal and a verification current control signal based on the temperature sensing signal. A read current generating unit(130) generates a read current in response to a read current control signal. A verification current generating unit(140) generates a verification current based on the verification current control signal.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a sense amplifier for controlling a data verification reference value by sensing a temperature change.

A unit cell of a phase change random access memory (PCRAM) is made of a phase change material. The phase change material has two stable states (amorphous state and crystalline state) depending on the heat provided in the form of current. Phase change materials include GST (Ge-Sb-Te), a compound of germanium (Ge), stevilium (Sb) and tellurium (Te).

Phase change memory devices store data based on different forms of phase change materials. The phase change material may have a different state depending on the current provided. In conclusion, the phase change material may have an amorphous or crystalline state due to heat generated by the currents provided to the phase change material. However, depending on the operating temperature of the phase change memory device, the state of the phase change material may vary depending on the current provided.

An object of the present invention is to provide a semiconductor memory device that controls the verification reference values and the read reference current values used in the sense amplifier, thereby ensuring a read margin despite a change in the state of the memory cells due to temperature changes. It is.

In an embodiment, a semiconductor memory device may include a temperature detector configured to sense an operating temperature to generate a temperature sensing signal, a current controller to generate a read current control signal and a verify current control signal based on the temperature sense signal, and a read current. And a sense / amplifier including a read current generator for generating a read current in response to the control signal, and a verify current generator for generating a verify current based on the verify current control signal.

In an embodiment, a semiconductor memory device may include a temperature sensing unit configured to sense an operating temperature to generate a temperature control signal and connected to bit lines, and provide different read currents and verify currents based on the temperature control signal. And a write / reader for reading and verifying data written to the memory cells, and a memory cell array including word lines and the memory cells connected to the bit lines.

The semiconductor memory device according to the embodiments of the present invention senses the operating temperature, and adaptively controls the read current reference value and the verification reference value according to the temperature change, thereby ensuring operational reliability over a wide operating temperature range.

1 is a block diagram illustrating a semiconductor memory device having a write / reader according to an embodiment of the present invention.
2 is a diagram for explaining a relationship between a write current and a write time of a phase change memory device.
3A and 3B are diagrams for describing an operation of reading and verifying a phase change memory device according to an exemplary embodiment.
4A and 4B are diagrams for describing a change in a resistance value of a memory cell according to an operating temperature of a semiconductor memory device.
5 is a diagram illustrating a semiconductor memory device having a write / reader according to an embodiment of the present invention.
6 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
7 is a circuit diagram illustrating an example embodiment of the verification current generator of FIGS. 1 and 5.
FIG. 8 is a circuit diagram illustrating another embodiment of the verify current generating unit of FIGS. 1 and 4.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor memory device having a write / reader according to an embodiment of the present invention.

Referring to FIG. 1, the write / reader 100 may include a temperature detector 110, a current controller 120, a read current generator 130, and a verify current generator 140. For example, the write / reader may include a write driver and a sense amplifier.

The temperature detector 110 detects an ambient operating temperature of the semiconductor memory device including the write / reader 100 and generates a temperature detection signal TEMP. In some embodiments, the temperature detector 110 may be activated in response to the mode control signal MD. The write / reader 100 may operate based on the same read current and verify current regardless of the operating temperature in response to the mode control signal MD, or may operate based on different read current and verify current depending on the operating temperature. have.

The current controller 120 may generate a read current control signal RCON and a verify current control signal VCON based on the temperature sensing signal TEMP and the write data WD. The current controller 120 may include an analog to digital converter (ADC). The current controller 120 generates the read current control signal RCON to generate the preset read current Iread according to the temperature sensing signal TEMP, and also controls the verify current to generate the preset verify current Ivrf. The signal VCON may be generated. However, when generating the verify current, a different verify current may be required according to the write data WD that was to be written to the memory cell to be verified, so that the verify current control signal VCON is generated based on the write data WD. can do. According to an embodiment, the read current control signal RCON and the verify current control signal VCON may be digital signals including a plurality of bits.

The read current generator 130 generates a read current Iread based on the read current control signal RCON, and the verify current generator 140 generates a verify current Ivrf based on the verify current control signal VCON. Can be generated.

Therefore, since the semiconductor memory device including the write / reader 100 according to the exemplary embodiment of the present invention senses data by providing different read currents Iread and verify currents Ivrf according to operating temperatures, the operating temperature In some cases, data read error may not occur.

2 is a diagram for explaining a relationship between a write current and a write time of a phase change memory device.

Referring to FIG. 2, the phase change material included in the unit cells of the phase change memory device may have two different states, a reset state and a set state.

In order to change the phase change material to the reset state, a high write value may be provided for a short write time, and in order to change the phase change material to a set state, a low write current may be provided for a relatively long write time. . Accordingly, the phase change material may be changed into a reset state by generating high heat for a short time and may be changed into a set state by generating low heat for a long time.

The phase change material may have a high resistance value due to an unstable amorphous state in the reset state, and may have a low resistance value due to a stable crystalline state in the set state.

3A and 3B are diagrams for describing an operation of reading and verifying a phase change memory device according to an exemplary embodiment of the present invention. In FIGS. 3A and 3B, the X axis represents the resistance value of the memory cells, and the Y axis represents the number of memory cells. That is, it shows distribution according to the number of memory cells having a specific resistance value for memory cell arrays including a plurality of memory cells.

3A is a diagram illustrating states of a plurality of unit cells of a phase change memory device before a verify operation.

Referring to FIG. 3A, when the resistance value of the phase change memory cells is used, the set state and the reset state may be distinguished with a read reference value interposed therebetween. However, since memory cells having resistance values similar to the read reference value are distributed, the memory cells may be determined to correspond to the reset state despite being in the set state, and conversely, the memory cells may be determined to correspond to the set state despite the reset state. Write and read fail may occur. Therefore, there is a need to improve the resistance value distribution of these memory cells.

3B is a diagram illustrating states of a plurality of unit cells of the phase change memory device after the verify operation.

Referring to FIG. 3B, it can be seen that after the verify operation, the number of memory cells having a resistance value similar to the read reference value is significantly reduced. The verify operation of the semiconductor memory device supplies a verify current after supplying a specific write current to the memory cell to compare the resistance value of the memory cell with the verify reference value, and if the resist value does not reach the verify reference value, the write current. The write operation is performed by increasing or decreasing the size of and repeatedly providing the same to the memory cell. For example, when the resistance of the phase change memory device included in the memory cell to be controlled in the set state is greater than the set verify reference value, the verify operation may be performed by providing the write current again. Therefore, the distribution of memory cells may be improved by an iterative verify operation.

When the distribution of the memory cells is opened as shown in FIG. 3B based on the read reference value, it is determined that the read margin is secured.

4A and 4B are diagrams for describing a change in a resistance value of a memory cell according to an operating temperature of a semiconductor memory device. In FIGS. 4A and 4B, the X axis represents an operating temperature (° C.), and the Y axis represents a resistance value (Ω) of the memory cell.

FIG. 4A is a diagram for describing a problem depending on states of memory cells when the same read reference value and verify reference values are applied regardless of an operating temperature.

Referring to FIG. 4A, regardless of the operating temperature, the reset verify reference value, read reference value, and set verify reference value maintain the same value.

As the operating temperature changes, the resistance value of the memory cell with respect to the set state remains relatively constant, but as the operating temperature increases, the resistance value of the memory cell in the reset state decreases drastically. Therefore, when the temperature exceeds a certain operating temperature, the reset state resistance value becomes lower than the reset verification reference value, and consequently, in order to make the resistance value larger than the reset verification reference value, it is changed to an amorphous state among the phase change materials included in the unit cell. The write operation should be performed by increasing the write time by increasing the volume or generating a larger write current. As a result, there is a problem that the write time is increased or the reset write operation is determined to fail.

In addition, since the read reference value is kept constant, a read fail such as determining the reset state as a set state may occur at a high operating temperature, and it is difficult to secure a read margin.

4B is a diagram for explaining a case in which a reading reference value and a verification reference value that are adaptively changed according to an operating temperature are set.

Referring to FIG. 4B, a compensation reset verification reference value is set by changing the reset verification reference value of FIG. 4A differently according to the operating temperature, and a compensation reading reference value is set by changing the reading reference value differently according to the operating temperature. .

Each compensation reset verification reference value and compensation reading reference value has a form of decreasing with temperature. Therefore, the problem caused by failure to reach the reset verification reference value due to the decrease in the resistance value of the reset state as the operating temperature rises can be improved. In FIG. 4B the compensation reset verification reference value is set to a value that decreases with temperature according to the characteristics of the phase change material to have a resistance value smaller than the reset state for all operating temperature ranges. The phase change material having a resistance value greater than the compensation reset verification reference value is determined to be in a reset state.

In addition, the compensation readout reference value decreases as the operating temperature increases. Therefore, it is possible to prevent the read margin from decreasing at high operating temperatures by increasing the operating temperature and decreasing the resistance value in the reset state. Therefore, the same read margin can be secured within all operating ranges, thereby minimizing the read fail.

5 is a diagram illustrating a semiconductor memory device having a write / reader according to an embodiment of the present invention.

Referring to FIG. 5, the semiconductor memory device 10a may include a memory cell 200, a write / reader 500, and a temperature detector 210.

The memory cell 200 is a memory cell connected to the bit line BL and may include a plurality of memory cells. The memory cell 200 is connected to the write / reader 500 by a first switch SW1 electrically connected in response to the column address CADDR through the bit line BL.

The column address CADDR may be provided in a device such as a controller included in the semiconductor memory device 10a. The first switch SW1 is turned on in response to the clamp voltage VCLP. The clamp voltage VCLP is used to maintain the voltage of the bit line BL below a threshold voltage at which the reset state of the phase change film of the memory cell 200 is changed.

The write / reader 500 may include a read current generator 230, a verify current generator 240, a write current generator 250, a current controller 120a, and a verifier 260.

The current controller 120a may generate a read current control signal RCON, a verify current control signal VCON, and a write current control signal WCON based on the temperature sensing signal TEMP. The read, verify, and write current control signals RCON, VCON, and WCON may have different values depending on the operating temperature of the semiconductor memory device 10a. The current controller 120a may include an analog-to-digital converter and control the overall operation of the write / reader 500.

The read current generator 230 may generate a read current Iread based on the read current control signal RCON. The read current Iread is electrically connected to the sensing node SN through the second switch SW2. The second switch SW2 may be turned on in response to the read command signal RCMD included in the command signal.

The verify current generator 240 may generate the verify current Ivrf based on the verify current control signal VCON. The verify current Ivrf is electrically connected to the sensing node SN through the third switch SW3. The third switch SW3 may be turned on in response to the verify command signal VCMD included in the command signal, and may be based on a voltage or current generated at the sensing node SN based on the verify current Ivrf. The verifier 260 determines whether to pass or fail data writing.

As mentioned above. Since the verify value is different according to the data to be written in the memory cell 200, the verify current generator 240 may generate the verify current Ivrf based on the write data WD.

The write current generator 250 may generate the write current Iwrt based on the write current control signal WCON and the write data WD. The write current Iwrt is connected to the sensing node SN through the fourth switch SW4, and the fourth switch SW4 may be turned on in response to the write command WCMD included in the command signal.

Therefore, at the same time, only one of the read current Iread, the verify current Ivrf, and the write current Iwrt may be provided to the sensing node SN based on the command signal.

The verification unit 260 verifies whether or not the write data WD is correctly written to the memory cell 200 based on the write data WD and the voltage or current of the sensing node SN, and verifies the feedback signal FB. Provided to the temperature current control unit 220. The current controller 220 may generate and change the write current control signal WCON according to the verification result.

The semiconductor memory device 10a of FIG. 5 further includes a write current generator 250 and a verification unit 260 including the components of the write / reader 100 shown in FIG. 1 to further perform a write operation. Can be done.

In the semiconductor memory device 10a according to an embodiment of the present invention, the read, verify, and write currents Iread, Ivrf, and Iwrt are generated based on the temperature sensing signal TEMP generated by the temperature sensor 210. Therefore, the currents provided to the memory cell 200 may have different values depending on the operating temperature of the semiconductor memory device 10a.

6 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 6, the semiconductor memory device 10b may include a plurality of word lines WL0, WL1, WL2,... And a plurality of bit lines BL0, BL1, BL2, BL3,. And a plurality of bit lines BL0, BL1, BL2, BL3, ... are connected to the write / readers 500a and 500b. The write / readers 500a and 500b may be connected to a predetermined number of bit lines according to the bit organization of the semiconductor memory device 10b. In FIG. 6, the write / readers 500a and 500b are connected to two bit lines, but the present invention is not limited thereto.

The semiconductor memory device 10b may include a temperature detector 310, and the temperature detector 310 may write a plurality of write / readers in response to the mode control signal MD. 500a, 500b). Therefore, the write / readers 500a and 500b respectively connected to the memory cell arrays including the plurality of memory cells may operate in response to the temperature sensing signal TEMP.

7 is a circuit diagram illustrating an example embodiment of the verification current generator of FIGS. 1 and 5. Hereinafter, for convenience of description, reference numerals of the verification current generation unit will be described using reference numerals of the verification current generation unit 140 of FIG. 1, but the verification current generation unit 240 of FIG. 5 may have substantially the same configuration. Can be.

Referring to FIG. 7, the verify current generator 140a includes a plurality of switches SW5, SW6, SW7, SW8, SW9, and SW10, and a plurality of reset constant current sources Ir1, Ir2, Ir3,..., And Ir. , And a set constant current source Isvrf.

The plurality of reset constant current sources Ir1, Ir2, Ir3, ..., Irn are connected to the fifth to eighth switches SW5, SW6, SW7, and SW8 in response to corresponding bits of the verify current control signal VCON. Through may be provided as a reset verify current (Irvrf). When the write data WD corresponds to the reset state, the ninth switch SW9 may be turned on so that the reset verify current Irvrf may be provided to the bit line BL as the verify current Ivrf.

Since the different verify current control signal VCON is generated according to the temperature sensing signal TEMP, the reset verify current Irvrf may have a different value according to the operating temperature. Therefore, it is possible to reduce the time required for the write operation to the reset state by providing the reset verify current Irvrf based on the compensation reset verify value set according to the operating temperature.

The set verify current Isvrf has a constant value depending on the operating temperature. Therefore, when the write data WD corresponds to the set state, the tenth switch SW10 is turned on so that the set verify current Isvrf is provided to the bit line BL as the verify current Ivrf.

FIG. 8 is a circuit diagram illustrating another embodiment of the verify current generating unit of FIGS. 1 and 4.

Referring to FIG. 8, the verify current generator 140b may include first to fourth NMOS transistors TN1, TN2, TN3, and TN4 and a first PMOS transistor TP1.

In FIG. 8, the first NMOS transistor TN1 and the first PMOS transistor TP1 are connected in series between the boosted voltage VPP and the bit line BL, and the second and third NMOS transistors TN2 and TN3 are connected in series. Is connected in series between the boosted voltage VPP and the bit line BL. The first PMOS transistor TP1 and the third NMOS transistor TN3 are turned on or turned off in response to the write data WD. Therefore, the first PMOS transistor TP1 and the third NMOS transistor TN3 may operate alternately with each other. The first NMOS transistor TN1 operates in response to the set bias voltage Vsvias, and the second NMOS transistor TN2 operates in response to the reset bias voltage Vrbias.

The second NMOS transistor TN2 generates a different reset verify current Irvrf according to the magnitude of the reset bias voltage Vrbias and provides it to the third NMOS transistor TN3, and the write data WD corresponds to the reset state. In the case of data, the verify current Ivrf is provided to the bit line BL.

The first NMOS transistor TN1 generates the set verify current Isvrf based on the set bias voltage Vsvias and provides the set verify current Isvrf to the bit line BL through the first PMOS transistor TP1.

Therefore, the reset bias voltage Vrbias and the set bias voltage Vsvias may have different values according to the temperature sensing signal TEMP. Accordingly, the verify current generator 140b according to an embodiment of the present invention senses the operating temperature to generate a temperature sensing signal TEMP, and accordingly controls the verify current control signal VCON to compensate for the verify values. In order to have a different resistance value according to the operating temperature, and to improve the read margin narrowed with the operating temperature, the read reference value is compensated to reduce the read reference resistance at high temperatures.

In conclusion, the semiconductor memory device including the write / reader according to the embodiments of the present invention may shorten the writing time by compensating the resistance value of the reset state and the set of phase change materials having different resistance values according to the operating temperature. Can be. In addition, the semiconductor memory device including the write / reader according to the embodiments of the present invention may read the read reference value in order to prevent a read fail from occurring in the process of reading the actually written data as the verification reference values are changed. By compensating, the reliability of the read operation can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

100, 500: register / reader
10a and 10b: semiconductor memory device
110, 210, 310: temperature sensor
200: memory cell

Claims (10)

A temperature sensor configured to detect an operating temperature and generate a temperature detection signal;
A current controller configured to generate a read current control signal and a verify current control signal based on the temperature sensing signal;
A read current generator configured to generate a read current in response to the read current control signal; And
And a write / reader including a verify current generator configured to generate a verify current based on the verify current control signal. The method according to claim 1,
And the current controller generates a read current control signal and a verify current control signal according to a predetermined memory cell characteristic based on the temperature sensing signal. The method according to claim 2,
The preset memory cell characteristic is,
And determining the resistance value of the memory cell provided with the read current and the verify current based on an amount of change with temperature. The method according to claim 1,
And a memory cell receiving the read current or the verify current through a bit line. The method of claim 4,
And the memory cell comprises a phase change memory cell. The method according to claim 1,
And the temperature sensing unit is activated in response to a mode control signal. The method according to claim 1,
The verify current generator generates a verify current based on write data and the verify current control signal.
And a verification unit configured to generate a feedback signal by comparing the voltage of the bit line formed by the verification current with the verification data. The method of claim 7,
And a write current generator to generate a write current based on the feedback signal and the verification data and to provide the write current to the bit line. A temperature sensor configured to generate a temperature control signal by sensing an operating temperature;
A write / reader coupled to bit lines, providing different read current and verify current based on the temperature control signal, and reading and verifying data written to memory cells; And
And a memory cell array including word lines and the memory cells connected to the bit lines. The method according to claim 9,
The write / reader sets a compensation read reference value and a compensation verification reference value based on the characteristics of the memory cell and the temperature control signal, and reads the read current and the value based on the set compensation read reference value and the compensation verification reference value. A semiconductor memory device, characterized by providing a verify current.

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