KR20120079670A - Fabrication method of nitride semiconductor light emitting device - Google Patents

Abstract

PURPOSE: A method of fabricating a nitride semiconductor light emitting device is provided to have excellent bond strength even in low pressure by having relatively high surface roughness compared to a Si-Al substrate. CONSTITUTION: A silicon substrate including a nitride buffer structure is prepared. A light emitting laminate(65) is formed by successively growing a first conductivity type nitride semiconductor layer(65a), an active layer(65b), and a second conductivity type nitride semiconductor layer(65c). Provided is a support substrate on the light emitting laminate. The silicon substrate is removed from the light emitting laminate.

Description

TECHNICAL MANUFACTURING METHOD OF NITRIDUM SEMICONDUCTOR LIGHT EMITTING DEVICE

The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly, to a method for manufacturing a nitride semiconductor light emitting device using a silicon substrate as a growth substrate.

In recent years, since the design and manufacturing technology of nitride semiconductor light emitting devices has been rapidly developed, the efficiency of high efficiency, high power blue, green, and UV short wavelength LEDs, as well as white LEDs, has been greatly improved. As a result of these developments, nitride semiconductor light emitting devices are expanding their application scope to automotive headlamps and general lighting.

However, despite these developments, in order to replace existing light sources such as fluorescent lamps, the efficiency related to manufacturing costs needs to be greatly improved. As a representative method for this, large diameter of the substrate may be considered. Since a sapphire (α-Al ₂ O ₃ ) substrate, which is a substrate commonly used at present, is relatively small in size (mainly 2 ″ and 3 ″), there is a problem in that mass productivity is low.

In order to solve this problem, a method of replacing a sapphire substrate with another wafer having a low cost and large diameter such as a silicon (Si) substrate has been studied.

For example, a silicon (Si) substrate can be largely sintered to a high level (eg, 12 "), which is very advantageous in mass production, but nitride single crystals grown on Si substrates are difficult to obtain high crystallinity. However, due to the problem that cracks occur, there is a difficulty in practical use.

Even if a high-quality nitride semiconductor single crystal is grown on such a silicon substrate, photon generated in the active layer can be absorbed by the underlying silicon substrate, so high efficiency is difficult to be expected. For example, in the case of a nitride semiconductor light emitting device of blue light, blue photon energy (˜2.7 eV) generated in the active layer may be emitted in all directions. Here, since the photons directed to the silicon substrate are all absorbed by the silicon substrate (energy band gap of Si: 1.1 eV), a considerable amount thereof (about 50%) may be lost, which causes a problem of lowering the light efficiency.

This can be solved by transferring the nitride semiconductor single crystal constituting the light emitting diode to another substrate.However, in this process, the wafer may be damaged due to mechanical stress such as thermal stress in the wafer handling process as well as the transfer process such as the growth substrate removal process. The problem of being broken or deformed can be caused.

The present invention provides a method of manufacturing a nitride semiconductor light emitting device capable of minimizing impact due to thermal shock of a subsequent process while ensuring efficient removal of a substrate and a transfer process of a nitride epitaxial layer.

In order to realize the above technical problem, the present invention

Providing a silicon substrate having a nitride buffer structure, sequentially growing a first conductivity type nitride semiconductor layer, an active layer, and a second conductivity type nitride semiconductor layer on the nitride buffer structure to form a light emitting laminate; A method of manufacturing a nitride semiconductor light emitting device, the method comprising: providing a support substrate on the light emitting stack, and removing the silicon substrate from the light emitting stack.

Removing the silicon substrate may include grinding the silicon substrate.

Alternatively, removing the silicon substrate may include grinding the silicon substrate so that a portion remains, and etching the remaining portion of the silicon substrate.

If necessary, the method may further include forming irregularities on the surface from which the silicon substrate is removed.

In a particular embodiment, between the forming of the light emitting stack and providing the support substrate, forming a hole in the upper surface of the light emitting stack to expose the first conductivity type nitride semiconductor layer; Forming a first electrode layer connected to the first conductivity type nitride semiconductor layer through the hole on the laminate; and forming a second electrode layer connected to the second conductivity type nitride semiconductor layer on the light emitting laminate. The method may further include forming an electrical insulation layer such that the first electrode layer and the second electrode layer are insulated from each other.

In this case, the forming of the electrically insulating layer may include forming a first insulating film on an upper surface of the light emitting stack and an inner surface of the hole before the forming of the first and second electrode layers; And selectively removing the first insulating film so that the connection region of the second conductivity type nitride semiconductor layer is opened, and after forming the second electrode layer, forming a second insulating film on the second electrode layer. It may include.

A reflective metal layer may be formed between the support substrate and the light emitting stack.

In addition, the support substrate may be a single crystal substrate. Preferably, the support substrate may be an additional silicon substrate. If necessary, the additional silicon substrate may be a silicon substrate doped with impurities to have electrical conductivity.

A nitride buffer structure employable in the present invention includes a nucleation layer formed on the first silicon substrate and made of an Al-containing nitride semiconductor, and a material formed on the nucleation layer and having a larger lattice constant than the nucleation layer. It may include a stress compensation layer made of a nitride semiconductor.

The stress compensation layer may be made of a nitride semiconductor having a lower Al content or no Al than the nucleation layer. The stress compensation layer may comprise GaN, in particular may be undoped GaN.

The stress compensation layer is divided into an upper layer and a lower layer in a thickness direction, and the nitride buffer structure may further include a porous mask layer disposed between the upper layer and the lower layer. Alternatively, the porous mask layer may be disposed between the nucleation layer and the stress compensation layer.

Silicon nitride may be used as the porous mask layer.

The nucleation layer may include a first nitride semiconductor layer formed on the first silicon substrate and a second nitride semiconductor layer including a material having a lattice constant greater than that of the first nitride semiconductor layer and having a smaller lattice constant than the stress compensation layer. It may include.

In this case, The first nitride semiconductor layer may include AlN, and the second nitride semiconductor layer may include Al _x Ga _(1-x) N (0 <x <1). Preferably, the Al content (x) of the second nitride semiconductor layer may decrease from the region adjacent to the first nitride semiconductor layer to the region adjacent to the stress compensation layer.

The nitride buffer structure further includes an intermediate layer formed on the stress compensation layer and formed of a nitride layer containing Al, and an additional nitride semiconductor layer formed on the intermediate layer and having a lattice constant greater than that of the intermediate layer. It may include.

In this case, the intermediate layer may be Al _x Ga _(1-x) N (0 <x≤1), and the additional nitride semiconductor layer may be GaN. The additional nitride semiconductor layer may include a first conductivity type GaN layer.

By using a silicon substrate as the nitride growth substrate, it is possible to realize an effective and precise growth substrate removal process while minimizing damage to the nitride single crystal. In addition, for example, by replacing the conventional Si-Al substrate with a silicon substrate not only reduces the manufacturing cost, but also has a relatively high surface roughness compared to the Si-Al substrate, excellent bonding strength even at low pressure during surface bonding You can expect.

1A to 1D are cross-sectional views of respective processes for explaining a method of manufacturing a nitride semiconductor light emitting device according to one embodiment of the present invention.
2 to 4 are cross-sectional views showing silicon substrates having various nitride buffer structures that can be employed in the present invention.
5A to 5G are cross-sectional views illustrating processes for manufacturing a nitride semiconductor light emitting device according to a particular embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views of main processes for describing a method of manufacturing a nitride semiconductor light emitting device according to an embodiment of the present invention.

As shown in Fig. 1A, the manufacturing method according to the present example starts with a process of preparing a first silicon substrate 11 having a nitride buffer structure 20 formed thereon.

In this embodiment, the first silicon substrate 11 is employed as a substrate for nitride single crystal growth. The nitride buffer structure 20 is employed to alleviate the lattice constant difference between the silicon single crystal, which is the substrate, and the nitride epitaxial layer to be grown, and may be formed in a multilayer structure.

The nitride buffer structure 20 may include, but is not limited to, a nuclear growth layer formed on the first silicon substrate 11 and a stress compensation layer formed on the nuclear growth layer. The nucleus growth layer may be formed of an Al-containing nitride semiconductor, and the stress compensation layer may be formed of a nitride semiconductor having a larger lattice constant than the nucleation layer. For example, the stress compensation layer may be a nitride semiconductor containing less Al than the nucleation layer or containing no Al such as GaN.

In this way, the nitride buffer structure 20 is provided as a structure that prevents strong compressive stress to the epitaxial to be formed on the first silicon substrate (11). This compressive stress can effectively suppress the occurrence of cracks that can be caused by epitaxial by compensating for the tensile stress generated during cooling. In this regard, various types of nitride buffer structures 20 that can be employed in the present invention will be described with reference to FIGS.

Subsequently, as shown in FIG. 1B, the light emitting structure 15 is formed on the nitride buffer structure 20.

The light emitting structure 15 may be obtained by sequentially growing the first conductivity type nitride semiconductor layer 15a, the active layer 15b, and the second conductivity type nitride semiconductor layer 15c. Since the nitride semiconductor single crystal constituting the light emitting structure 15 is formed using the nitride buffer structure 20 described above, it can be grown on the first silicon substrate 11 as a high quality crystal.

Next, as shown in FIG. 1C, a second silicon substrate 31 is provided as a supporting substrate on the light emitting structure 15, and then the first silicon substrate 11 is removed from the light emitting structure 15. Remove

As in the present embodiment, by adopting a support substrate which is a silicon single crystal of the same material, it is possible to alleviate the problem of thermal shock and the like in a subsequent step. In the present process, the process of providing the second silicon substrate may be bonded using a wafer bonding process.

For example, the wafer can be bonded by pressing at a constant temperature. If necessary, a joining metal layer can be used. Since the second silicon substrate employed as the support substrate in the present embodiment has a relatively high surface roughness compared to the Si-Al substrate, there is an advantage of having excellent bonding strength even at low pressure during surface bonding.

In addition, as shown in FIG. 1C, a high reflective metal such as Al or Ag is disposed between the second silicon substrate 31 and the light emitting structure 15 to alleviate the light absorption problem caused by the second silicon substrate 31. It may include a reflective layer 17 including.

In this example, the silicon substrate is exemplified as the support substrate, but other kinds of substrates may be advantageously employed as necessary. For example, other single crystal substrates can be used that can alleviate thermal shock and satisfy the required properties (eg, electrical conductivity) depending on the product.

In the present embodiment, since the first silicon substrate 11 is a material having a relatively low hardness as the substrate for growing nitride, a mechanical rather than a lift-off process using a laser beam that may damage the epitaxial layer of the light emitting structure 15. Effective removal can be achieved using chemical or mechanical chemical removal processes. As shown in Fig. 1C, the grinding process using the grinding device G can be advantageously used.

In contrast, in the process of removing the first silicon substrate 11, the first and second removal processes may be separated to realize a precise and effective removal process for the first silicon substrate 11.

That is, in the first removal step, the grinding step is performed on the first silicon substrate 11 until a part remains, and then in the second removal step, the remaining part of the first silicon substrate 11 is high. Etching processes can be applied to ensure selectivity. As the secondary removal process, dry etching or wet etching, such as reactive ion etching (RIE), may be used. Of course, CMP processes involving chemical etching can also be used.

Here, the "high selectivity" referred to in the secondary removal process may include not only the difference in the etching rate according to the chemical etching characteristics of silicon and GaN, but also the selectivity based on the difference in polishing rate according to the physical hardness. For example, when RIE is employed as the secondary removal process, only silicon can be easily removed with high selectivity without damaging the nitride single crystal by using SF ₆ or CF ₄ as an etching gas.

Subsequently, as shown in FIG. 1D, the contact electrode 18 may be formed on the surface from which the first silicon substrate 11 is removed to be connected to the first conductivity type nitride semiconductor layer.

As described above, the second silicon substrate 31 employs a substrate heavily doped with impurities (eg, a second conductivity type impurity) to have a high conductivity, so that the nitride semiconductor light emitting device 30 shown in FIG. It may have a structure in which current is conducted depending on the stacking direction of the layer.

In the present exemplary embodiment, the nitride buffer structure 20 is removed together in the process of removing the first silicon substrate 31, but a part or all of the nitride buffer structure 20 may be left as necessary. .

As described above, when growing the nitride epitaxial layer on the silicon substrate, various types of multilayer buffer structures may be employed on the silicon substrate. 2-4 illustrate various multilayer nitride buffer structures that may be employed in the present invention.

First, referring to FIG. 2, the multi-layer buffer structure 20-1 formed on the silicon substrate 11 includes a nucleation layer 21 and the nucleation layer 21 formed on the silicon substrate 11. It may include a stress compensation layer 26 formed on the material and having a lattice constant greater than that of the nucleation layer 21.

In such a structure, the stress compensation layer 26 may provide a compressive stress for alleviating the tensile stress applied to the nitride epitaxial of the relatively small lattice constant formed on the silicon substrate 11 having a large lattice constant.

The nucleation layer 21 may be made of an Al-containing nitride semiconductor having a relatively small lattice constant among the nitride semiconductors. In addition, the stress compensation layer 26 may be formed of a nitride semiconductor having a lower Al content or no Al content than the nucleation layer, and may include, for example, GaN.

As shown in FIG. 3, the multilayer buffer structure 20-1 may further include a porous mask layer 25 disposed between the nucleation layer 21 and the stress compensation layer 26. .

The porous mask layer 25 may grow the nitride semiconductor layer, which is the stress compensation layer 26, to have relatively good crystallinity through a similar action to lateral growth. The porous mask layer 25 may be made of silicon nitride.

In contrast, the multilayer buffer structure 20-2 shown in FIG. 3 has the nucleation layer 21 formed on the silicon substrate 11 and the nucleation layer 21 on the silicon substrate 11 similarly to the previous embodiment. Although it includes a stress compensation layer 26 formed of a material having a lattice constant larger than the nucleation layer 21, the position of the porous mask layer 25 is different.

More specifically, as shown in FIG. 4, the stress compensation layer 26 is divided into upper and lower layers 26b and 26a in the thickness direction, and the porous mask layer 25 is formed of the upper and lower layers 26b, 26a). Due to the position of the porous mask layer 25, the lower layer 26a of the stress compensation layer has a different function from that of the other upper layer 26b.

That is, since the upper layer 26b of the stress compensation layer is formed on the porous mask layer 25 similarly to the stress compensation layer 26 shown in FIG. 3, the nitride semiconductor coalesced according to the lateral growth principle. Layer, but the lower layer 26a is located below the porous mask layer 25 and serves as a base exposed by the voids of the mask layer 25, so that the lower layer 26a is on the mask layer 25 rather than the shape shown in FIG. The upper layer 26b, which is the portion of the stress compensation layer formed, may have better crystallinity.

The multi-layer buffer structure 20-3 shown in FIG. 4 is formed on the silicon substrate 11 with the nucleation layer 21 and the nucleation layer 21 formed on the upper and lower layers 26b and 26a. And a porous mask layer 25 formed between the distinct stress compensation layer 26 and the upper and lower layers 26b and 26a of the stress compensation layer.

The nucleation layer 21 employed in the present embodiment has a lattice constant greater than that of the first nitride semiconductor layer 21a and the first nitride semiconductor layer 21a formed on the silicon substrate 11, and the stress compensation. The second nitride semiconductor layer 21b may be formed of a material having a smaller lattice constant than the layer 26.

In the present embodiment, the first nitride semiconductor layer 21a may be AlN, and the second nitride semiconductor layer 21b may be Al _x Ga _(1-x) N (0 <x <1). Preferably, the Al content (x) of the second nitride semiconductor layer 21b may decrease from the region adjacent to the first nitride semiconductor layer 21a to the region adjacent to the stress compensation layer 26. In this case, the stress compensation layer 26 may comprise GaN, in particular undoped GaN.

The multilayer buffer structure 20-3 shown in FIG. 4 is formed on the stress compensation layer 26, and is formed on the intermediate layer 27 made of an Al-containing nitride layer and on the intermediate layer 27. In addition, the semiconductor device may further include an additional nitride semiconductor layer 28 having a lattice constant greater than that of the intermediate layer 27.

The intermediate layer 27 may be Al _x Ga _(1-x) N (0 <x ≦ 1), and the additional nitride semiconductor layer 28 may be GaN. In this case, the additional nitride semiconductor layer 28 may include a first conductivity type GaN layer.

Referring to Fig. 4, the multilayer buffer structure employable in the present invention will be described in detail by another approach. An AlN / AlGaN nucleus growth layer 21a / 21b is grown on the silicon substrate 11 and continuously undoped GaN. SiN _x porosity for growing dislocation density within the stress compensation layer 26 and an additional nitride semiconductor layer 28 of n-type GaN, and inside the stress compensation layer 26 and the additional nitride semiconductor layer 28, respectively. It can be understood that the mask layer 25 and the AlGaN intermediate layer 27 are further interposed.

In a specific example, an AlN / AlGaN nuclear growth layer (about 2 μm or less) is grown, and an undoped GaN layer (about 2 μm or less) and an n-type GaN layer (3 to 4 μm) are grown in succession. When additionally using the SiN _x layer and the AlGaN interlayer at the submicro level inside the layer, the crystallinity of GaN in the luminescent laminate grown based on the multilayer buffer structure is <300 arcsec in the case of (002) FWHM. , (102) FWHM <400 arcsec. In addition, no crack is formed on the wafer, and bowing due to thermal stress can also be maintained at a low level of <20 μm.

5A to 5G are cross-sectional views illustrating processes for manufacturing a nitride semiconductor light emitting device according to a particular embodiment of the present invention.

As shown in FIG. 5A, a hole H is formed on the upper surface of the light emitting stack 65 grown on the first silicon substrate 61 to expose the first conductivity type nitride semiconductor layer 65a.

The first silicon substrate 61 has an upper surface on which the nitride buffer structure 20 described above is formed. The nitride buffer structure 20 may be a multilayer buffer structure illustrated in FIGS. 1A and 2-4. The light emitting stack 65 has a structure in which a first conductive nitride semiconductor layer 65a, an active layer 65b, and a second conductive nitride semiconductor layer 65c are sequentially grown, and the nitride buffer structure 20 is formed. Can be grown to a high quality crystal on the first silicon substrate 61 using.

The hole H formed in the light emitting stack 65 is formed to pass through the active layer 65a on the top surface of the light emitting stack 65. By using the hole H formed in this step, an electrode structure connected to the first conductivity-type semiconductor layer 65a can be formed to be drawn out on the light emitting stack 65.

As described above, in the present embodiment, a first electrode layer connected to the first conductivity type nitride semiconductor layer 65a is formed on the light emitting stack 65 via the hole, and the second conductivity type nitride semiconductor layer ( The second electrode layer connected to 65c also has a structure formed on the light emitting stack 65. In the present embodiment, since the first electrode layer and the second electrode layer are provided on the same surface with respect to the light emitting stack 65, the electrical insulation layer 67 is formed to be electrically insulated from each other.

An example of the process of forming the electrode layer and the insulating layer may be described with reference to FIGS. 5B to 5D.

First, as shown in FIG. 5B, the first and second electrode layers (67 of FIG. 5B and 68 of FIG. 5D) of the first conductivity type nitride semiconductor layer 65a and the second conductivity type nitride semiconductor layer 65c. The first insulating layer 69a may be formed on the upper surface of the light emitting stack 65 and the inner surface of the hole H, except for regions to be connected to the respective layers. The first insulating layer 69a may be an insulating material such as SiO ₂ or SiN _x .

Next, each electrode layer is formed in the exposed connection region of the first conductivity type nitride semiconductor layer 65a and the second conductivity type nitride semiconductor layer 65c. In the present embodiment, each electrode layer 67, 68 is formed on and with contact layers 67a, 68a directly contacting each of the semiconductor layers 65c, 65a to form an ohmic contact, thereby forming a basic arrangement of electrodes. It is illustrated by the form containing the conductive layers 67b and 68b.

As shown in FIG. 5B, the contact layer 67a of the second electrode layer is formed together with the contact layer 68a of the first electrode layer, and the second electrode layer is formed on the contact layer 67a of the second electrode layer. Conductive layer 67b is further formed to complete second electrode layer 67. If necessary, the formation of the contact layers 67a and 68a and the formation of the conductive layer 67b may be performed through separate photoresist processes, respectively.

Subsequently, as illustrated in FIG. 5C, the second insulating layer 66b may be formed to expose the contact layer 67 for the first electrode layer while applying the first electrode layer 67. The first electrode layer 68 and the second electrode layer 69 may be electrically insulated from each other through the second insulating layer 66b.

As described above, the insulating layer 66 employed in the present embodiment may include a first insulating film and a second insulating film having different process sequences and formation regions. The first insulating layer 66a defines a connection area between the first and second electrode layers 67 and 68 while preventing unwanted connection between the light emitting stack 65 and the electrode layers 67 and 68. 66a may electrically insulate the first and second electrode layers 67 and 68.

Next, as shown in FIG. 5D, the second electrode layer is formed by forming a conductive layer 68b connected to the contact layer 68a on the upper surface of the light emitting stack 65. As a result, the first electrode layer 68 is formed on the light emitting stack (the surface opposite to the first silicon substrate 11), and is electrically connected to the first conductivity type nitride semiconductor layer 65a through the hole H. It may have a structure that is connected.

The first electrode layer 68 may be formed of a second silicon substrate, which is provided as a supporting substrate, in the future, including a highly reflective metal material to prevent light absorption, or additionally forming a separate reflective layer made of the highly reflective metal. .

Subsequently, as shown in FIGS. 5E and 5F, the first silicon substrate is provided together with the bonding process of the second silicon substrate.

As shown in FIG. 5E, the second silicon substrate 71 may be bonded using a known wafer bonding process. For example, the wafer can be bonded by pressing at a constant temperature. If necessary, a joining metal layer can be used. Since the second silicon substrate 71 used in the present embodiment has a relatively high surface roughness compared to the Si-Al substrate which is conventionally mainly used as a support substrate, it can have excellent bonding strength even at low pressure during surface bonding. .

The second silicon substrate 71 employed in the present embodiment may be a silicon substrate heavily doped with impurities to have electrical conductivity. Therefore, the second silicon substrate 71 may be incorporated into an electrode structure on one side.

Subsequently, as the process of removing the first silicon substrate 61, the first silicon substrate 61 may be ground until a part of the first silicon substrate 61 remains. Since silicon has a relatively low hardness, when the above grinding process is used, the removal process of the first silicon substrate 61 may be effectively performed. In particular, it is possible to prevent damage to the epitaxial layer that may occur in the laser lift off process, which is a conventional substrate separation process.

In this embodiment, in order to remove the silicon substrate precisely, a partial region 61 'of the first silicon substrate is left as shown in Fig. 5E without completely removing the silicon substrate by the grinding process.

Subsequently, as shown in FIG. 5F, the remaining partial region 61 ′ of the first silicon substrate may be removed by using an etching process to ensure high selectivity.

This secondary removal process may use a dry or wet etching, such as RIE. Of course, CMP processes involving chemical etching can also be used. For example, when RIE is employed as the secondary removal process, SF ₆ or CF ₄ may be used as an etching gas, and when the CMP process is performed, the slurry used may be a material having high selectivity to silicon. By employing, it is possible to perform a precise removal process of the first silicon substrate.

Next, as shown in FIG. 5G, in order to improve light extraction efficiency on the surface from which the first silicon substrate is removed, irregularities may be formed. Subsequently, the light emitting stack 65 may be separated in each device unit, and a passivation layer 76 may be formed on the exposed side surface of the light emitting stack 65.

In addition, the second electrode layer 67 may be exposed, a bonding metal 77 for the second electrode structure may be formed, and a metal layer 78 may be formed on the rear surface of the second silicon substrate 71.

Finally, as shown in FIG. 5G, by dicing the second silicon substrate 71, a desired nitride semiconductor light emitting device 70 can be provided.

By adopting the same silicon substrate as the growth substrate, the final supporting substrate not only reduces manufacturing costs but also has a relatively high surface roughness, and thus excellent bonding strength can be expected even at low pressure during surface bonding. In addition, since the silicon substrate as the growth substrate has low hardness and high selectivity with the nitride single crystal, the growth substrate can be effectively removed while minimizing damage to the nitride single crystal.

The above-described embodiments and the accompanying drawings are merely illustrative of preferred embodiments, and the present invention is intended to be limited by the appended claims. In addition, it will be apparent to those skilled in the art that the present invention may be substituted, modified, and changed in various forms without departing from the technical spirit of the present invention described in the claims.

Claims (23)

Providing a silicon substrate having a nitride buffer structure formed thereon;
Sequentially growing a first conductivity type nitride semiconductor layer, an active layer, and a second conductivity type nitride semiconductor layer on the nitride buffer structure to form a light emitting stack;
Providing a support substrate on the light emitting stack; And
And removing the silicon substrate from the light emitting laminate.
The method of claim 1,
The removing of the silicon substrate may include grinding the silicon substrate.
The method of claim 1,
Removing the silicon substrate,
Grinding the silicon substrate so that a portion remaining, and etching the remaining portion of the silicon substrate.
The method of claim 1,
And forming irregularities on the surface from which the silicon substrate is removed.
The method of claim 1,
Between forming the light emitting stack and providing the support substrate,
Forming a hole in the upper surface of the light emitting stack to expose the first conductivity type nitride semiconductor layer;
Forming a first electrode layer connected to the first conductivity type nitride semiconductor layer through the hole on the light emitting stack;
Forming a second electrode layer connected to the second conductivity type nitride semiconductor layer on the light emitting stack;
And forming an electrical insulation layer such that the first electrode layer and the second electrode layer are insulated from each other.
The method of claim 5,
Forming the electrical insulation layer,
Before forming the first and second electrode layers, forming a first insulating film on an upper surface of the light emitting stack and an inner surface of the hole;
Selectively removing the first insulating film to open the connection region of the first and second conductivity type nitride semiconductor layers;
After forming the second electrode layer, forming a second insulating film on the second electrode layer.
The method of claim 1,
A method of manufacturing a nitride semiconductor light emitting device, characterized in that a reflective metal layer is formed between the support substrate and the light emitting stack.
The method of claim 1,
The support substrate is a nitride semiconductor light emitting device manufacturing method characterized in that the conductive single crystal substrate.
The method according to any one of claims 1 to 8,
The support substrate is a nitride semiconductor light emitting device manufacturing method, characterized in that the additional silicon substrate.
10. The method of claim 9,
And the additional silicon substrate is a silicon substrate doped with impurities to have electrical conductivity.
The method of claim 9, wherein the nitride buffer structure,
A nucleation layer formed on the first silicon substrate and formed of an Al-containing nitride semiconductor;
And a stress compensation layer formed on the nucleation layer and formed of a nitride semiconductor made of a material having a lattice constant greater than that of the nucleation layer.
The method of claim 11,
The stress compensation layer is a nitride semiconductor light emitting device, characterized in that made of a nitride semiconductor containing less Al or Al than the nucleation layer.
The method of claim 12,
The stress compensation layer is nitride semiconductor light emitting device manufacturing method characterized in that it comprises GaN.
The method of claim 13,
The stress compensation layer is a nitride semiconductor light emitting device, characterized in that the undoped GaN.
The method of claim 11,
The stress compensation layer is divided into an upper layer and a lower layer in the thickness direction,
The nitride buffer structure, the nitride semiconductor light emitting device manufacturing method characterized in that it further comprises a porous mask layer disposed between the upper layer and the lower layer.
16. The method of claim 15,
The porous mask layer is a nitride semiconductor light emitting device manufacturing method, characterized in that made of silicon nitride.
The method of claim 11, wherein the nucleation layer,
A first nitride semiconductor layer formed on the first silicon substrate;
And a second nitride semiconductor layer made of a material having a lattice constant greater than that of the first nitride semiconductor layer and having a smaller lattice constant than the stress compensation layer.
18. The method of claim 17,
The first nitride semiconductor layer includes AlN, and the second nitride semiconductor layer includes Al _x Ga _(1-x) N (0 <x <1).
19. The method of claim 18,
And the Al content (x) of the second nitride semiconductor layer decreases gradually from a region adjacent to the first nitride semiconductor layer to a region adjacent to the stress compensation layer.
The method of claim 11,
The nitride buffer structure,
An intermediate layer formed on the stress compensation layer and formed of a nitride layer containing Al,
And a further nitride semiconductor layer formed on the intermediate layer and having a lattice constant greater than the lattice constant of the intermediate layer.
21. The method of claim 20,
The intermediate layer is Al _x Ga _(1-x) N (0 <x _{≤ 1} ), and the additional nitride semiconductor layer is GaN manufacturing method.
The method of claim 21,
The additional nitride semiconductor layer comprises a first conductivity type GaN layer.
The method of claim 11,
The nitride buffer structure further comprises a porous mask layer disposed between the nucleation layer and the stress compensation layer.

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