KR20120073086A - Variable resistance element, semiconductor device including the variable resistance element, and method of operation the semiconductor device - Google Patents

Abstract

PURPOSE: A variable resistance device, a semiconductor device including the same, and a method for operating the semiconductor device are provided to enhance the reliability of the semiconductor device by improving a current distribution of the variable resistance device. CONSTITUTION: A set voltage is applied to a variable resistance device(110). A reset voltage is applied to the variable resistance device(120). A reset current flowing in the variable resistance device with the applied reset voltage is sensed(130). It is determined whether the sensed reset current is within a first current range(140). If the sensed reset current is not within the first current range, the reset voltage is applied to the variable resistance device.

Description

Variable resistance element, semiconductor device including the variable resistance element and a method of operating the semiconductor device {Variable resistance element, Semiconductor device including the variable resistance element, and Method of operation the semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to a variable resistance element, a semiconductor device including the variable resistance element, and a method of operating the semiconductor device.

In accordance with the demand for higher capacity and lower power of memory devices, research on next-generation memory devices that are nonvolatile and do not require refresh is being conducted. Such next-generation memory devices are required to have high integration of DRAM (Dynamic Random Access Memory), nonvolatile flash memory, and high speed of static RAM (SRAM). Next-generation memory devices that are currently in the spotlight include Phase Change RAM (PRAM), Nano Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), and RRAM (Resistive RAM). It is proposed as a next generation memory device that meets the above requirements. Among them, RRAM takes advantage of the phenomenon that when a sufficiently high voltage is applied to the non-conductive material, a passage through which a current flows is generated and the resistance is lowered. At this time, once the passage is created, it may be removed or regenerated by applying an appropriate voltage.

The problem to be solved by the present invention is to improve the current distribution of the variable resistance element, a variable resistance element that can improve the reliability of the semiconductor device including the variable resistance element, a semiconductor device including the variable resistance element and the semiconductor device To provide a method of operation.

In an operation method of a semiconductor device including a variable resistance element according to an exemplary embodiment of the present disclosure, a resistance of the variable resistance element is changed from a first resistor to a second resistor having a different value from the first resistor. Applying a first voltage to the variable resistance element so as to be effective; Sensing a first current flowing through the variable resistance element to which the first voltage is applied; Determining whether the first current is within a predetermined first current range; And applying an additional first voltage having the same voltage level as the first voltage to the variable resistance element when the first current is not included within the predetermined first current range.

In some embodiments, the first resistor may be a set resistor, the second resistor may be a reset resistor, and the second resistor may be greater than the first resistor.

In some embodiments, the sensing of the first current flowing in the variable resistance element may include applying a read voltage having a magnitude smaller than the first voltage to apply the variable resistor to which the first voltage is applied. The first current flowing through the device may be sensed.

In some embodiments, the application time of the first voltage may be 1 μs to 1 ns.

In some embodiments, the additional first voltage may have the same pulse width as the first voltage.

In some embodiments, the first current range is an ON current flowing through the variable resistance element when the variable resistance element has the first resistance and the variable resistance element when the variable resistance element has the second resistance. The predetermined sensing margin may be secured between the off currents flowing in the predetermined current.

In some embodiments, the first current range includes a first off current flowing through the variable resistance element when the variable resistance element has the second resistance and a third resistance in which the variable resistance element is larger than the second resistance. It may be predetermined so that a predetermined sensing margin is secured between the second off current flowing through the variable resistance element when having a.

In some embodiments, the method may further include: detecting the first current and whether the first current is within the predetermined first current range with respect to the variable resistance element to which the additional first voltage is applied. The method may further include repeatedly performing the determining.

In some embodiments, applying the additional first voltage to the variable resistance element, sensing the first current until the first current is within the predetermined first current range, and the The determining of whether the first current is within the predetermined first current range may be repeatedly performed.

In some embodiments, the operation method includes before the step of determining whether the first current is within the predetermined first current range, the current range of the data corresponding to the second resistance, the first current The method may further include determining whether the current is within the second current range.

In some embodiments, the first current range can be included in the second current range.

In some embodiments, the operating method may further include changing a voltage level of the first voltage when the first current is greater than a maximum value of the second current range.

In some embodiments, the step of applying the first voltage whose voltage level is changed and sensing the first current may be repeatedly performed with respect to the variable resistance element.

In some embodiments, the method may further include changing the resistance of the variable resistance element from the second resistor to the first resistor when the first current is smaller than a minimum value of the second current range. The method may further include applying a second voltage to the device.

In some embodiments, the applying of the first voltage and the sensing of the first current may be repeatedly performed with respect to the variable resistance element to which the second voltage is applied.

In some embodiments, determining whether the first current is within the predetermined first current range comprises: determining whether the first current is less than or equal to a maximum value of the predetermined first current range; And determining whether the first current is equal to or greater than a minimum value of the predetermined first current range.

In some embodiments, determining whether the first current is within the first current range includes: an on current flowing through the variable resistance element and the first current when the variable resistance element has the first resistance. It may be determined whether the difference is greater than or equal to a predetermined level.

In some embodiments, the method may further include applying a second voltage to the variable resistance element such that the resistance of the variable resistance element is changed from the second resistance to the first resistance; And sensing a second current flowing through the variable resistance element to which the second voltage is applied.

In some embodiments, the sensing of the second current flowing through the variable resistance element may include applying a read voltage having an absolute value smaller than the first voltage and the second voltage to apply the second voltage. The second current flowing through the variable resistance element may be sensed.

In some embodiments, the application time of the second voltage may be 1 μs to 1 ns.

In some embodiments, the applying of the first voltage to the variable resistance element may be performed after the sensing of the second current.

In some embodiments, the operating method further comprises: determining that the second current is within a third current range; And when the second current is not included in the third current range, applying an additional second voltage having the same voltage level as the second voltage to the variable resistance element.

In some embodiments, when the second current is within the third current range, applying the first voltage to the variable resistance element may be performed.

In some embodiments, for the variable resistance element to which the additional second voltage is applied, repeating the step of sensing the second current and determining whether the second current is within the third current range Can be done.

In addition, the variable resistance device according to an embodiment of the present invention for solving the above problems, the first electrode and the second electrode; And a first voltage disposed between the first electrode and the second electrode, and when a first voltage is applied between the first electrode and the second electrode, the first resistance is changed from a first resistor to a second resistor larger than the first resistor. And a variable resistance material layer that changes from the second resistor to the first resistor when a second voltage is applied, and when the variable resistance material layer has the second resistor, a current flowing through the variable resistance element is in a first current range. The first voltage may be repeatedly applied to the variable resistance material layer until included therein.

In some embodiments, the variable resistance material layer is changed from the second resistor to a third resistor larger than the second resistor when a third voltage having a voltage level higher than the first voltage is applied, and the variable resistance material When the layer has the third resistance, the third voltage may be repeatedly applied to the variable resistance material layer until the current flowing through the variable resistance element is within the second current range.

In addition, the semiconductor device according to an embodiment of the present invention for solving the above problems, when a first voltage is applied is changed from the first resistor to a second resistor larger than the first resistor, and when the second voltage is applied A variable resistance element changing from the second resistor to the first resistor; And a selection element connected in series with the variable resistance element, wherein when the variable resistance element has the second resistance, the first voltage is applied until a current flowing in the variable resistance element is included in a first current range. The variable resistance element may be repeatedly applied.

In some embodiments, the variable resistance element is changed from the second resistor to a third resistor larger than the second resistor when a third voltage having a voltage level higher than the first voltage is applied, and the variable resistor element is In the case of having the third resistor, the third voltage may be repeatedly applied to the variable resistance element until the current flowing in the variable resistance element is included in the second current range.

According to the inventive concept, when a reset voltage is applied to a variable resistance element included in a semiconductor device to write data having an off state to a semiconductor device, a reset current flowing through the variable resistance element to which the reset voltage is applied is predetermined. By repeatedly applying the reset voltage having the same voltage level and the same pulse width until it is within the current range of, the distribution of the off current of the semiconductor device can be greatly improved, thereby improving the reliability of the semiconductor device.

In addition, according to the spirit of the present invention, by applying a reset voltage to the variable resistance element included in the semiconductor device, and detects the reset current flowing through the variable resistance element is applied to the reset voltage, the detected reset current is a predetermined current range It is possible to improve the durability of the semiconductor device by verifying whether it is included in the semiconductor device, and to improve the operating speed of the semiconductor device and reduce power consumption by implementing a driving circuit for the semiconductor device more simply.

1 is a cross-sectional view schematically showing a variable resistance device according to an embodiment of the present invention.
2 is a cross-sectional view schematically illustrating a variable resistance device according to another exemplary embodiment of the present invention.
3 is a graph schematically illustrating a resistance distribution of a variable resistance element when the variable resistance element according to an exemplary embodiment of the present invention is included in a single bit memory device.
4 is a graph schematically illustrating a resistance distribution of a variable resistance element when the variable resistance element according to an exemplary embodiment of the present invention is included in a multi-bit memory device.
5 is a graph illustrating an example of operating voltages applied to the variable resistance device of FIG. 1.
6 is a graph illustrating a current flowing through the variable resistance element when the operating voltages according to FIG. 5 are applied.
7 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to an example embodiment.
FIG. 8 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 7.
FIG. 9 is a graph illustrating a current flowing through the variable resistance element to explain an example of step 140 included in the operating method of the semiconductor device illustrated in FIG. 7.
FIG. 10 is a graph illustrating the distribution of data according to the current of the variable resistance element when the determining whether the reset current is within a predetermined current range according to FIG. 9 is performed.
FIG. 11 is a graph illustrating a current flowing through the variable resistance element to explain another example of step 140 included in the method of operating the semiconductor device of FIG. 7.
FIG. 12 is a graph illustrating the distribution of data according to the current of the variable resistance element when the determining whether the reset current is included in the predetermined current range according to FIG. 11 is performed.
13 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to another exemplary embodiment of the present disclosure.
14 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 13.
15 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to another exemplary embodiment of the present disclosure.
16 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 15.
17 is a graph illustrating another example of operating voltages applied to the semiconductor device of FIG. 15.
18 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to another exemplary embodiment of the present disclosure.
19 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 18.
20 is a graph illustrating a current distribution of a variable resistance element included in the semiconductor device when the conventional method of operating the semiconductor device is performed.
FIG. 21 is a graph illustrating a current distribution of a variable resistance element included in the semiconductor device when the method of operating the semiconductor device according to the embodiment is performed.
22 is a circuit diagram illustrating an example of a semiconductor device including a variable resistance device according to an example embodiment.
FIG. 23 is a circuit diagram illustrating another example of a semiconductor device including a variable resistance device according to an example embodiment. FIG.
24 is a cross-sectional view illustrating an example of the semiconductor device of FIG. 23.
25 is a block diagram illustrating a semiconductor device including a variable resistance device according to example embodiments.
26 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.
27 is a block diagram schematically illustrating an electronic system according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the drawings, the size of components may be exaggerated for convenience of explanation.

Terms used in the embodiments of the present invention described below may have a meaning commonly known in the art. For example, at least one means at least one, that is, one or more numbers and may be used in the same sense as one or a plurality.

1 is a cross-sectional view schematically showing a variable resistance device according to an embodiment of the present invention.

Referring to FIG. 1, the variable resistance element 10 may include a lower electrode 11, a variable resistance material layer 12, and an upper electrode 13, and the variable resistance material layer 12 may include the lower electrode 11. ) And the upper electrode 13. In another embodiment, the variable resistance element 10 may further include a buffer layer (not shown) on the lower electrode 11 or on the variable resistance material layer 12.

The lower electrode 11 and the upper electrode 13 may include a conductive material. For example, the lower electrode 11 and the upper electrode 13 may include an oxidation resistant metal layer or a polysilicon layer. For example, the oxidation resistant metal film may include platinum (Pt), iridium (Ir), iridium oxide (IrO), titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten (W), molybdenum (Mo), and ruthenium (Ru). ) And ruthenium oxide (RuO), and the oxidation resistant metal film may be formed after forming a buffer layer (not shown). In the present embodiment, the lower electrode 11 and the upper electrode 13 are disposed above and below the variable resistance material layer 12, respectively, but the arrangement of the lower electrode 11 and the upper electrode 13 is not limited to the term. Do not. In another embodiment, the lower electrode 11 and the upper electrode 13 may be disposed on the left and right sides of the variable resistance material layer 12, respectively.

The variable resistance material layer 12 may include a perovskite-based oxide or a transition metal oxide. For example, the perovskite oxide may include Pr1-xCaxMnO3, La1-xCaxMnO3, SrZrO3 / SrTiO3, CrTiO3, or Pb (Zr, Ti) O3 / Zn1-xCdxS, and the transition metal may be nickel, niobium, titanium, zirconium. , Hafnium, cobalt, iron, copper, manganese, zinc or chromium. In this case, the resistance of the variable resistance material layer 12 may vary depending on the voltage between the lower electrode 11 and the upper electrode 13.

2 is a cross-sectional view schematically illustrating a variable resistance device according to another exemplary embodiment of the present invention.

Referring to FIG. 2, the variable resistive element 10 ′ may include a lower electrode 11, a variable resistive material layer 12 ′ and an upper electrode 13, and the variable resistive material layer 12 ′ may have a lower portion. It may be formed between the electrode 11 and the upper electrode 13. In the present embodiment, the variable resistance material layer 12 ′ may include a base thin film 12a and an oxygen exchange layer 12b. For example, the base thin film 12a may include TaOx, and the oxygen exchange layer 12b may include Ta2O5. Since the variable resistance element 10 ′ according to the present embodiment is a modified embodiment of the variable resistance element 10 shown in FIG. 1, the above description of FIG. 1 may also be applied to the present embodiment.

3 is a graph schematically illustrating a resistance distribution of a variable resistance element when the variable resistance element according to an exemplary embodiment of the present invention is included in a single bit memory device.

Referring to FIG. 3, the X axis represents a resistance of a single bit memory device including a variable resistance element, and the Y axis represents the number of single bit memory cells. The variable resistance element 10 shown in FIG. 1 or the variable resistance element 10 'shown in FIG. 2 is a single memory that stores data' 0 'or data' 1 'according to the resistance state of the variable resistance material layer 12. It can be used as a semiconductor device such as a single bit nonvolatile memory device.

In the present embodiment, the data '1' may correspond to the case of the low resistance state, and the data '0' may be determined to correspond to the case of the high resistance state. The operation of writing data '1' into the variable resistance element 10 may be referred to as a set operation, and the operation of writing data '0' may be referred to as a reset operation. However, the present invention is not limited thereto, and in another embodiment, it may be determined that data '1' corresponds to a high resistance state and data '0' corresponds to a low resistance state.

When data '1' is written to a single bit nonvolatile memory device The single bit nonvolatile memory device is in an 'ON' state and when the data '0' is written to the single bit nonvolatile memory device Single bit nonvolatile The memory device may correspond to an 'off' state. In this case, in order to improve the reliability of the single bit nonvolatile memory device, a sufficient sensing margin SM must be secured between an 'on' state and an 'off' state of the single bit nonvolatile memory device.

4 is a graph schematically illustrating a resistance distribution of a variable resistance element when the variable resistance element according to an exemplary embodiment of the present invention is included in a multi-bit memory device.

Referring to FIG. 4, the X axis represents a resistance of a multi bit memory device including a variable resistance element, and the Y axis represents the number of multi bit memory cells. The variable resistive element 10 shown in FIG. 1 or the variable resistive element 10 'shown in FIG. 2 may have data' 00 ', data' 01 ', and data '10 depending on the resistance state of the variable resistive material layer 12. Or a semiconductor device such as a multi-bit nonvolatile memory device for storing data '11'.

In the present embodiment, the data '11' may correspond to the case of the low resistance state, and the data '01', the data '10' and the data '00' may be determined to correspond to the case of the high resistance state. Writing data '11' into the variable resistance element 10 may be referred to as a set operation, and writing data '01', data '10' and data '00' may be referred to as a reset operation. However, the present invention is not limited thereto, and in another embodiment, it is determined that data '11' corresponds to a high resistance state, and that data '01', data '10', and data '00' correspond to a low resistance state. It may be.

When data '11' is written in the multi-bit nonvolatile memory device The multi-bit nonvolatile memory device is in an 'on' state, and data '01', data '10' or data '00' is stored in the multi-bit nonvolatile memory device. When written, the multi-bit nonvolatile memory device may correspond to an 'off' state. At this time, in order to improve the reliability of the multi-bit nonvolatile memory device, a sufficient sensing margin SM1 must be secured between an 'on' state and an 'off' state of the multi-bit nonvolatile memory device. Furthermore, in the multi-bit nonvolatile memory device, since three pieces of data may correspond to an 'off' state, sufficient sensing margins SM2 and SM3 must be secured even between data corresponding to the 'off' state.

In addition, the variable resistance element 10 shown in FIG. 1 or the variable resistance element 10 'shown in FIG. 2 may have data' 000 ', data' 001 ', and data according to the resistance state of the variable resistance material layer 12. It can be used as a semiconductor device such as a 3-bit nonvolatile memory device for storing '010', data '011', data '100', data '101', data '110' or data '111'. Furthermore, the variable resistance element 10 shown in FIG. 1 or the variable resistance element 10 'shown in FIG. 2 is a 4-bit or more multi-bit nonvolatile memory device depending on the resistance state of the variable resistance material layer 12. It can also be used in a semiconductor device such as.

5 is a graph illustrating an example of operating voltages applied to the variable resistance device of FIG. 1. 6 is a graph illustrating a current flowing through the variable resistance element when the operating voltages according to FIG. 5 are applied.

Referring to FIG. 5, the X axis represents time in seconds, and the Y axis represents voltage applied to the variable resistance element in V units. In this case, the voltage applied to the variable resistance element 10 is a difference between the voltages applied to the upper electrode 13 and the lower electrode 11. Specifically, when the voltage of the lower electrode 11 is referred to, the upper electrode ( 13).

First, a set voltage VSET may be applied to the variable resistance element 10, and a read voltage VREAD may be applied to detect a current flowing through the variable resistance element 10 to which the set voltage VSET is applied. As described above, it may be referred to as a set cycle that the set voltage VSET and the read voltage VREAD are continuously applied to the variable resistance element 10. When the set voltage VSET is applied to the variable resistance element 10, the variable resistance element 10 may be switched from a high resistance state to a low resistance state, whereby a current may flow in the variable resistance element 10. .

Next, a reset voltage VRESET may be applied to the variable resistance element 10, and a read voltage VREAD may be applied to detect a current flowing through the variable resistance element 10 to which the reset voltage VRESET is applied. . As such, the reset cycle may be sequentially applied to the variable resistance element 10 by the reset voltage VRESET and the read voltage VREAD. When the reset voltage VRESET is applied to the variable resistance element 10, the variable resistance element 10 may be switched from a low resistance state to a high resistance state, whereby current hardly flows in the variable resistance element 10. Can be.

In the present embodiment, the set voltage VSET and the reset voltage VRESET may have polarities opposite to each other. As described above, the variable resistance element in which the polarities of the set voltage VSET and the reset voltage VRESET are opposite to each other ( 10) is called a bipolar variable resistance element. In the graph of FIG. 5, the set voltage VSET of the variable resistance element 10 has a negative value, and the reset voltage VRESET has a positive value. However, the present invention is not limited thereto, and in another embodiment, the set voltage VSET has a positive value according to the type of material included in the variable resistive material layer 12 of the variable resistive element 10. The voltage VRESET may have a negative value.

The application time of the set voltage VSET and the reset voltage VRESET in the variable resistance element 10 may be in a range of 1 μs to 1 ns, and the shape of the applied pulse may be adjusted in various shapes such as rectangular, serrated, and trapezoidal. have.

Although not shown, when the variable resistance element 10 is used in a multi-bit nonvolatile memory device, different voltage levels may be set to write different data corresponding to an off state to the multi-bit nonvolatile memory device. The branches may be applied with first to third reset voltages. For example, the voltage level of the third reset voltage for writing data '00' may be higher than the voltage level of the second reset voltage for writing data '10', and the voltage level of the second reset voltage is data ' It may be higher than the voltage level of the first reset voltage for writing 01 '.

6 is a graph illustrating a current flowing through the variable resistance element when the operating voltages according to FIG. 5 are applied.

Referring to FIG. 6, the X axis represents the number of set cycles or reset cycles, and the Y axis represents current in A units. At this time, the current flowing through the variable resistance element 10 after the set cycle, that is, the current sensed by applying the read voltage VREAD after applying the set voltage VSET to the variable resistance element 10 is set current IST. ). In addition, the current flowing through the variable resistance element 10 after the reset cycle, that is, the current sensed by applying the reset voltage VRESET to the variable resistance element 10 and then applying the read voltage VREAD to the reset current IRESET. ).

In FIG. 6, the set current IST maintains a current level of about 1.00E-5 A, where the set current ISET maintains a constant current level regardless of the number of set cycles. On the other hand, the reset current IRESET has a relatively large dispersion and has a current level of about 1.00E-9 to about 1.00E-7, where the reset current IRESET is nonlinear regardless of the number of reset cycles. It can be seen that the distribution.

As described above, the set current IISE of the variable resistance element 10 is not largely distributed, whereas the reset current IRESET is relatively large. Accordingly, when the sensing margin is not sufficiently secured between the 'on' state and the 'off' state of the variable resistance element 10, the variable resistance element 10 may not be used as a memory element. In particular, when the variable resistance device 10 is used in a multi-bit nonvolatile memory device, the necessity of clearly distinguishing the data corresponding to the off state becomes greater, and a sensing margin may not be sufficiently secured between the data. In this case, the reliability of the multi-bit nonvolatile memory device is greatly reduced.

7 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to an example embodiment. FIG. 8 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 7.

7 and 8, the method of operating the semiconductor device according to the present exemplary embodiment may be, for example, a method of operating the semiconductor device including the variable resistance element 10 illustrated in FIG. 1. Hereinafter, the method of operating the semiconductor device according to the present exemplary embodiment will be described in detail with reference to the variable resistance element 10 illustrated in FIG. 1. In this case, the variable resistance element 10 will be described in detail with reference to the present embodiment, with a focus on the case where the variable resistance element 10 is used for a multi-bit nonvolatile memory element. In FIG. 8, the X axis represents time in seconds, and the Y axis represents operating voltages applied to the semiconductor device in V units.

In step 110, a set voltage VSET is applied to the variable resistance element 10. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIG. 8. The set voltage VSET shown in FIG. 8 may have a negative voltage level, for example, about −3.0 V. FIG.

In step 120, the reset voltage VRESET is applied to the variable resistance element 10. In this case, the reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIG. 8. The reset voltage VRESET illustrated in FIG. 8 may have a positive voltage level, and the voltage level of the reset voltage VRESET may be higher than the voltage level of the read voltage VREAD.

When the variable resistance element 10 is used in a multi-bit nonvolatile memory device, first to third reset voltages are applied to write different data '01', '10' or '00' having an off state, respectively. Can be. For example, a first reset voltage for writing data '01' to a multi-bit nonvolatile memory device is about 3.2 V, a second reset voltage for writing data '10' is about 3.3 V, and data '00' The third reset voltage for writing 'may be about 3.4 volts.

In operation 130, the reset current IRESET flowing through the variable resistance element 10 to which the reset voltage VRESET is applied is sensed. Specifically, the read voltage VREAD is applied to the variable resistance element 10 to which the reset voltage VRESET is applied, and the reset current IRESET flowing to the variable resistance element 10 to which the read voltage VREAD is applied is sensed. can do. In this case, the read voltage VREAD may correspond to the read voltage VREAD shown in FIG. 8. The read voltage VREAD shown in FIG. 8 may have a positive voltage level, for example, about 0.5V.

In operation 140, it is determined whether the detected reset current IRESET is included in the first current range I1. Here, the first current range I1 may be predetermined in order to improve the distribution of the reset current IRESET flowing through the variable resistance element 10, that is, the off current. In detail, the first current range I1 may be predetermined in order to secure a sufficient sensing margin between the on current and the off current of the variable resistance element 10. A detailed description of step 140 will be made below with reference to FIGS. 9 through 12.

As a result of the determination, if the detected reset current IRESET is included in the first current range I1, the procedure ends, and if the detected reset current IRESET is not included in the first current range I1, step 120 is performed. To perform. As such, when the detected reset current IRESET is not included in the first current range I1, step 120 may be applied to apply the additional reset voltage VRESET to the variable resistance element 10. In this case, the additional reset voltage VRESET may correspond to the reset voltage VRESET shown in FIG. 8. Therefore, the additional reset voltage VRESET may have the same voltage level as the reset voltage VRESET applied previously and have the same pulse width.

FIG. 9 is a graph illustrating a current flowing through the variable resistance element to explain an example of step 140 included in the operating method of the semiconductor device illustrated in FIG. 7.

Referring to FIG. 9, the X axis represents the number of set cycles or reset cycles, and the Y axis represents current in A units. At this time, the current flowing through the variable resistance element 10 after the set cycle, that is, the current sensed by applying the read voltage VREAD after applying the set voltage VSET to the variable resistance element 10 is set current IST. ). In addition, the current flowing through the variable resistance element 10 after the reset cycle, that is, the current sensed by applying the reset voltage VRESET to the variable resistance element 10 and then applying the read voltage VREAD to the reset current IRESET. ). For example, the set voltage may be applied for about 1 μs with a voltage level of about −5 V, and the reset voltage may be applied for about 1 μs with a voltage level of about 7 V.

In operation 140 illustrated in FIG. 7, it is determined whether the sensed reset current IRESET is included in the first current range I1. According to the present embodiment, the sensed reset current IRESET is the first current range I1. It may be determined whether or not the maximum value I1_max of? For example, the maximum value I1_max of the first current range I1 may be set to about 5E-8A.

If the sensed reset current IRESET is less than or equal to the set maximum value I1_max, it is determined that the sensed reset current IRESET is included in the first current range I1. In FIG. 9, when the detected reset current IRESET is included in the first current range I1, it is indicated by '□'. On the other hand, if the sensed reset current IRESET is not less than or equal to the set maximum value I1_max, that is, greater than the set maximum value I1_max, the sensed reset current IRESET is not included in the first current range I1. You can judge that you do not. In FIG. 9, when the detected reset current IRESET is not included in the first current range I1, it is indicated by '■'.

In addition, in step 140 of FIG. 7, it is determined whether the sensed reset current IRESET is included in the first current range I1. According to the present embodiment, the sensed reset current IRESET is in the first current range. It may be determined whether or not the minimum value I1_min of I1 is equal to or greater than. For example, the minimum value I1_min of the first current range I1 may be set to about 8E-9A.

If the sensed reset current IRESET is equal to or greater than the set minimum value I1_min, it is determined that the sensed reset current IRESET is included in the first current range I1. In FIG. 9, when the detected reset current IRESET is included in the first current range I1, it is indicated by '□'. If the detected reset current IRESET is not greater than or equal to the set minimum value I1_min, that is, smaller than the set minimum value I1_min, the sensed reset current IRESET is not included in the first current range I1. You can judge that you do not.

FIG. 10 is a graph illustrating the distribution of data according to the current of the variable resistance element when the determining whether the reset current is within a predetermined current range according to FIG. 9 is performed.

Referring to FIG. 10, the X axis represents a current flowing through the variable resistance element in A units along a log scale, and the Y axis represents the number of data having a corresponding current value. At this time, the area indicated by hatched lines indicates the distribution of data according to the current of the variable resistance element according to the prior art, and the area indicated by dots indicates the distribution of data according to the current of the variable resistance element according to the present embodiment. .

In the present embodiment, when the set voltage VSET is applied, a separate determination step for determining whether the set voltage VSET falls within a predetermined current range is not performed. Not very different from Meanwhile, in the present embodiment, when the reset voltage VRESET is applied, a separate determination step of whether the reset voltage VRESET is included in the predetermined current range is performed, and the reset voltage VRESET is in the predetermined current range. If not included in the range, an additional step of applying a reset voltage VRESET is performed. Accordingly, according to this embodiment, it can be seen that the distribution of data is improved as compared with the conventional case.

FIG. 11 is a graph illustrating a current flowing through the variable resistance element to explain another example of step 140 included in the method of operating the semiconductor device of FIG. 7.

Referring to FIG. 11, the X axis represents the number of set cycles or reset cycles, and the Y axis represents current in A units. At this time, the current flowing through the variable resistance element 10 after the set cycle, that is, the current sensed by applying the read voltage VREAD after applying the set voltage VSET to the variable resistance element 10 is set current IST. ). In addition, the current flowing through the variable resistance element 10 after the reset cycle, that is, the current sensed by applying the reset voltage VRESET to the variable resistance element 10 and then applying the read voltage VREAD to the reset current IRESET. ). For example, the set voltage may be applied for about 1 μs with a voltage level of about −5 V, and the reset voltage may be applied for about 1 μs with a voltage level of about 7 V.

In step 140 illustrated in FIG. 7, it is determined whether the sensed reset current IRESET is included in the first current range I1. According to the present embodiment, the variable resistance element 10 is turned on when the variable resistance element 10 is in an on state. It is possible to determine whether the difference between the ON current flowing through 10 and the sensed reset current IRESET, that is, the sensing margin is greater than or equal to a predetermined level. For example, the predetermined level may be about 1000 times.

When the difference between the ON current flowing through the variable resistance element 10 and the sensed reset current IRESET is equal to or greater than a predetermined level, it is determined that the sensed reset current IRESET is included in the first current range I1. In FIG. 11, when the detected reset current IRESET is included in the first current range I1, it is indicated by '□'. On the other hand, when the difference between the ON current flowing through the variable resistance element 10 and the reset current IRESET is smaller than the predetermined level, it is determined that the detected reset current IRESET is not included in the first current range I1. Can be. In FIG. 11, when the detected reset current IRESET is not included in the first current range I1, it is marked as '■'.

FIG. 12 is a graph illustrating the distribution of data according to the current of the variable resistance element when the determining whether the reset current is included in the predetermined current range according to FIG. 11 is performed.

Referring to FIG. 12, the X axis represents the current flowing through the variable resistance element as A along a log scale, and the Y axis represents the number of data having the current value. At this time, the area indicated by hatched lines indicates the distribution of data according to the current of the variable resistance element according to the prior art, and the area indicated by dots indicates the distribution of data according to the current of the variable resistance element according to the present embodiment. .

In the present embodiment, when the set voltage VSET is applied, a separate determination step for determining whether the set voltage VSET falls within a predetermined current range is not performed. Not very different from Meanwhile, in the present embodiment, when the reset voltage VRESET is applied, a separate determination step of whether the reset voltage VRESET is included in the predetermined current range is performed, and the reset voltage VRESET is in the predetermined current range. If not included in the range, an additional step of applying a reset voltage VRESET is performed. Accordingly, according to this embodiment, it can be seen that the distribution of data is improved as compared with the conventional case. Thus, a sufficient sensing margin can be secured between the set current ISET, that is, the on current and the reset current IRESET, that is, the off current.

13 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to another exemplary embodiment of the present disclosure. 14 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 13.

13 and 14, a method of operating a semiconductor device according to the present exemplary embodiment may be, for example, a method of operating a semiconductor device including the variable resistance element 10 illustrated in FIG. 1. Hereinafter, the method of operating the semiconductor device according to the present exemplary embodiment will be described in detail with reference to the variable resistance element 10 illustrated in FIG. 1. In this case, the variable resistance element 10 will be described in detail with reference to the present embodiment, with a focus on the case where the variable resistance element 10 is used for a multi-bit nonvolatile memory element. In FIG. 14, the X axis represents time in seconds, and the Y axis represents operating voltages applied to the semiconductor device in V units.

In step 210, a set voltage VSET is applied to the variable resistance element 10. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIG. 10. The set voltage VSET shown in FIG. 14 may have a negative voltage level, for example, about −3.0 V. FIG.

In operation 220, the set current ISET flowing through the variable resistance element 10 to which the set voltage VSET is applied is sensed. Specifically, the read voltage VREAD is applied to the variable resistance element 10 to which the set voltage VSET is applied, and the set current IISE flowing through the variable resistance element 10 to which the read voltage VREAD is applied is sensed. can do. In this case, the read voltage VREAD may correspond to the read voltage VREAD shown in FIG. 14. The read voltage VREAD shown in FIG. 14 may have a positive voltage level, for example, about 0.5V.

In operation 230, it is determined whether the sensed set current IST is included in the first current range I1. Here, the first current range I1 may be predetermined in order to improve the distribution of the set current IST flowing through the variable resistance element 10, that is, the on current. In detail, the first current range I1 may be predetermined in order to secure a sufficient sensing margin between the on current and the off current of the variable resistance element 10.

As a result of the determination, step 240 is performed when the detected set current IST is included in the first current range I1, and step 210 when the detected set current IST is not included within the first current range I1. Perform As described above, if the sensed set current IST is not included in the first current range I1, an additional set voltage VSET may be applied to the variable resistance element 10 by performing step 210. In this case, the additional set voltage VSET may correspond to the set voltage VSET shown in FIG. 14. Therefore, the additional set voltage VSET may have the same voltage level as the previously applied set voltage VSET and have the same pulse width.

In step 240, the reset voltage VRESET is applied to the variable resistance element 10. In this case, the reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIG. 14. The reset voltage VRESET illustrated in FIG. 14 may have a positive voltage level, and the voltage level of the reset voltage VRESET may be higher than the voltage level of the read voltage VREAD.

When the variable resistance element 10 is used in a multi-bit nonvolatile memory device, first to third reset voltages are applied to write different data '01', '10' or '00' having an off state, respectively. Can be. For example, a first reset voltage for writing data '01' to a multi-bit nonvolatile memory device is about 3.2 V, a second reset voltage for writing data '10' is about 3.3 V, and data '00' The third reset voltage for writing 'may be about 3.4 volts.

In operation 250, the reset current IRESET flowing through the variable resistance element 10 to which the reset voltage VRESET is applied is sensed. Specifically, the read voltage VREAD is applied to the variable resistance element 10 to which the reset voltage VRESET is applied, and the reset current IRESET flowing to the variable resistance element 10 to which the read voltage VREAD is applied is sensed. can do. In this case, the read voltage VREAD may correspond to the read voltage VREAD shown in FIG. 14. The read voltage VREAD shown in FIG. 14 may have a positive voltage level, for example, about 0.5V.

In operation 260, it is determined whether the detected reset current IRESET is included in the second current range I2. Here, the second current range I2 may be predetermined in order to improve the distribution of the reset current IRESET flowing through the variable resistance element 10, that is, the off current. Specifically, the second current range I2 may be predetermined in order to ensure sufficient sensing margin between the on current and the off current of the variable resistance element 10. Herein, in operation 260, the contents described above with reference to FIGS. 9 through 12 may be applied.

As a result of the determination, if the detected reset current IRESET is included in the second current range I2, the procedure is terminated, and if the detected reset current IRESET is not included in the second current range I2, step 240 is performed. To perform. As such, when the detected reset current IRESET is not included in the second current range I2, step 240 may be applied to apply the additional reset voltage VRESET to the variable resistance element 10. In this case, the additional reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIG. 14. Therefore, the additional reset voltage VRESET may have the same voltage level as the reset voltage VRESET applied previously and have the same pulse width.

15 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to another exemplary embodiment of the present disclosure. 16 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 15. 17 is a graph illustrating another example of operating voltages applied to the semiconductor device of FIG. 17.

15 to 17, a method of operating a semiconductor device according to the present exemplary embodiment may be, for example, a method of operating a semiconductor device including the variable resistance element 10 illustrated in FIG. 1. Hereinafter, the method of operating the semiconductor device according to the present exemplary embodiment will be described in detail with reference to the variable resistance element 10 illustrated in FIG. 1. In this case, the variable resistance element 10 will be described in detail with reference to the present embodiment, with a focus on the case where the variable resistance element 10 is used for a multi-bit nonvolatile memory element. 16 and 17, the X axis represents time in seconds, and the Y axis represents operating voltages applied to the semiconductor device in V units.

In step 310, the set voltage VSET is applied to the variable resistance element 10. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIGS. 16 and 17. The set voltage VSET illustrated in FIGS. 16 and 17 may have a negative voltage level, for example, about −3.0 V. FIG.

In step 320, the reset voltage VRESET is applied to the variable resistance element 10. In this case, the reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIGS. 16 and 17. The reset voltage VRESET illustrated in FIGS. 16 and 17 may have a positive voltage level, and the voltage level of the reset voltage VRESET may be higher than the voltage level of the read voltage VREAD.

When the variable resistance element 10 is used in a multi-bit nonvolatile memory device, first to third reset voltages are applied to write different data '01', '10' or '00' having an off state, respectively. Can be. For example, a first reset voltage for writing data '01' to a multi-bit nonvolatile memory device is about 3.2 V, a second reset voltage for writing data '10' is about 3.3 V, and data '00' The third reset voltage for writing 'may be about 3.4 volts.

In operation 330, the reset current IRESET flowing through the variable resistance element 10 to which the reset voltage VRESET is applied is sensed. Specifically, the read voltage VREAD is applied to the variable resistance element 10 to which the reset voltage VRESET is applied, and the reset current IRESET flowing to the variable resistance element 10 to which the read voltage VREAD is applied is sensed. can do. In this case, the read voltage VREAD may correspond to the read voltage VREAD shown in FIGS. 16 and 17. The read voltage VREAD shown in FIGS. 12 and 13 may have a positive voltage level, for example, about 0.5V.

In operation 340, it is determined whether the sensed reset current IRESET is included in the first current range I1. Here, the first current range I1 may be a current range of data to be written. When the variable resistance element 10 is used in a multi-bit memory element, the first current range I1 is a current range flowing through the multi-bit memory element to which data '01' is written when the data to be written is '01'. When the data to be written is '10', the data '10' may be a current range flowing through the written multi-bit memory device, and when the data to be written is '00', the data '00' is It may be a current range flowing through the written multi-bit memory device.

As a result of determination, when the detected reset current IRESET is greater than the maximum value I1_max of the first current range I1, step 350 is performed, and the detected reset current IRESET is the minimum value of the first current range I1. If less than I1_min, step 360 is performed, and if the detected reset current IRESET is included in the first current range I1, step 370 is performed.

In operation 350, the reset voltage VRESET to be applied to the variable resistance element 10 is changed. In this case, the changed reset voltage VRESET may correspond to the reset voltage VRESET 'shown in FIG. 16. Specifically, in step 360, if the sensed reset current IRESET is greater than the maximum value I1_max of the first current range I1, the voltage level of the applied reset voltage VRESET is written to the variable resistance element 10. It's not enough to program the data you want. Therefore, in this case, the changed reset voltage VRESET 'must be applied to the variable resistance element 10 so that the voltage level is higher than the previously applied reset voltage VRESET.

In step 360, the set voltage VSET is applied to the variable resistance element 10. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIG. 17. In detail, in operation 340, when the sensed reset current IRESET is smaller than the minimum value I1_min of the first current range I1, the set voltage VSET is applied to the variable resistance element 10 again. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIG. 17.

In operation 370, it is determined whether the sensed reset current IRESET is included in the second current range I2. Here, the second current range I2 may be predetermined in order to improve the distribution of the reset current IRESET flowing through the variable resistance element 10, that is, the off current. Specifically, the second current range I2 may be predetermined in order to ensure sufficient sensing margin between the on current and the off current of the variable resistance element 10. Here, in step 370, the contents described above with reference to FIGS. 9 through 12 may be applied.

As a result of the determination, when the detected reset current IRESET is included in the second current range I2, the procedure ends, and when the detected reset current IRESET is not included in the second current range I2, step 320 is performed. To perform. As such, when the sensed reset current IRESET is not included in the second current range I2, step 320 may be applied to apply the additional reset voltage VRESET to the variable resistance element 10. In this case, the additional reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIGS. 16 and 17. Therefore, the additional reset voltage VRESET may have the same voltage level as the reset voltage VRESET applied previously and have the same pulse width.

18 is a flowchart illustrating a method of operating a semiconductor device including a variable resistance device according to another exemplary embodiment of the present disclosure. 19 is a graph illustrating an example of operating voltages applied to the semiconductor device of FIG. 18.

18 and 19, the method of operating the semiconductor device according to the present exemplary embodiment may be, for example, a method of operating the semiconductor device including the variable resistance element 10 illustrated in FIG. 1. Hereinafter, the method of operating the semiconductor device according to the present exemplary embodiment will be described in detail with reference to the variable resistance element 10 illustrated in FIG. 1. In this case, the variable resistance element 10 will be described in detail with reference to the present embodiment, with a focus on the case where the variable resistance element 10 is used for a multi-bit nonvolatile memory element. In FIG. 19, the X axis represents time in seconds, and the Y axis represents operating voltages applied to the semiconductor device in V units.

In step 410, the set voltage VSET is applied to the variable resistance element 10. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIG. 19. The set voltage VSET shown in FIG. 19 may have a negative voltage level, for example, about −3.0 V. FIG.

In step 420, the reset voltage VRESET is applied to the variable resistance element 10. In this case, the reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIG. 19. The reset voltage VRESET illustrated in FIG. 19 may have a positive voltage level, and the voltage level of the reset voltage VRESET may be higher than the voltage level of the read voltage VREAD.

When the variable resistance element 10 is used in a multi-bit nonvolatile memory device, first to third reset voltages are applied to write different data '01', '10' or '00' having an off state, respectively. Can be. For example, a first reset voltage for writing data '01' to a multi-bit nonvolatile memory device is about 3.2 V, a second reset voltage for writing data '10' is about 3.3 V, and data '00' The third reset voltage for writing 'may be about 3.4 volts.

In operation 430, the reset current IRESET flowing through the variable resistance element 10 to which the reset voltage VRESET is applied is sensed. Specifically, the read voltage VREAD is applied to the variable resistance element 10 to which the reset voltage VRESET is applied, and the reset current IRESET flowing to the variable resistance element 10 to which the read voltage VREAD is applied is sensed. can do. In this case, the read voltage VREAD may correspond to the read voltage VREAD shown in FIG. 19. The read voltage VREAD illustrated in FIG. 19 may have a positive voltage level, for example, about 0.5V.

In operation 440, it is determined whether the sensed reset current IRESET is included in the first current range I1. Here, the first current range I1 may be a current range of data to be written. When the variable resistance element 10 is used in a multi-bit nonvolatile memory device, the first current range I1 flows through the written multi-bit memory device when the data to be written is '01'. It may be a current range, when the data to be written is '10', the data '10' may be a current range flowing through the written multi-bit memory device, when the data to be written is '00', the data '00 'May be a current range flowing to the written multi-bit memory device.

As a result of determination, when the detected reset current IRESET is greater than the maximum value I1_max of the first current range I1, step 450 is performed, and the detected reset current IRESET_n is the minimum value of the first current range I1. If less than I1_min, step 410 is performed, and if the detected reset current IRESET is included in the first current range I1, step 460 is performed.

In operation 450, the reset voltage VRESET to be applied to the variable resistance element 10 is changed. In this case, the changed reset voltage VRESET may correspond to the reset voltage VRESET 'shown in FIG. 19. In detail, in operation 440, when the detected reset current IRESET is greater than the maximum value I1_max of the first current range I1, the voltage level of the applied reset voltage VRESET is written to the variable resistance element 10. It's not enough to program the data you want. Therefore, in this case, the changed reset voltage VRESET 'must be applied to the variable resistance element 10 so that the voltage level is higher than the previously applied reset voltage VRESET.

Meanwhile, when the sensed reset current IRESET is smaller than the minimum value I1_min of the first current range I1, step 410 is performed to apply the set voltage VSET to the variable resistance element 10. In this case, the set voltage VSET may correspond to the set voltage VSET shown in FIG. 19.

In operation 460, it is determined whether the sensed reset current IRESET is included in the second current range I2. Here, the second current range I2 may be predetermined in order to improve the distribution of the reset current IRESET flowing through the variable resistance element 10, that is, the off current. Specifically, the second current range I2 may be predetermined in order to ensure sufficient sensing margin between the on current and the off current of the variable resistance element 10. Herein, in operation 460, the contents described above with reference to FIGS. 9 to 12 may be applied.

As a result of the determination, if the detected reset current IRESET is included in the second current range I2, the procedure is terminated, and if the detected reset current IRESET is not included in the second current range I2, step 420 is performed. To perform. As such, if the detected reset current IRESET is not included in the second current range I2, step 420 may be performed to apply an additional reset voltage VRESET to the variable resistance element 10.

In this case, the additional reset voltage VRESET may correspond to the reset voltage VRESET or the changed reset voltage VRESET ′ shown in FIG. 19. In detail, in operation 440, when the sensed reset current IRESET is included in the first current range I1, the additional reset voltage VRESET may correspond to the reset voltage VRESET illustrated in FIG. 19. Accordingly, the additional reset voltage VRESET may have the same voltage level as the reset voltage VRESET applied previously and have the same pulse width. Meanwhile, in step 440, when the detected reset current IRESET is not included in the first current range I1 and step 450 is performed, the additional reset voltage VRESET is changed to the changed reset voltage VRESET ′ shown in FIG. 19. ) May correspond to. Accordingly, the additional reset voltage VRESET may have the same voltage level and the same pulse width as the previously applied changed reset voltage VRESET '.

In the above, the method of operating the semiconductor device according to some exemplary embodiments of the present disclosure has been described above, with a focus on the case in which the variable resistance element 10 of FIG. 1 is used in a multi-bit nonvolatile memory device. However, the method of operating the semiconductor device according to some embodiments of the present inventive concept may be similarly applied to the case where the variable resistance element 10 of FIG. 1 is used in a single bit nonvolatile memory device. When the variable resistance element 10 is used in a single bit nonvolatile memory device, the reset voltage VRESET may be, for example, about 3.0V.

20 is a graph illustrating a current distribution of a variable resistance element included in the semiconductor device when the conventional method of operating the semiconductor device is performed.

Referring to FIG. 20, the X axis represents the number of set cycles or the number of reset cycles, and the Y axis represents the current distribution of the variable resistance element in A units. In this case, the set current ISET represents a current flowing through the variable resistance element when the set voltage VSET is applied. For example, the set voltage may be about −3.0 V, thereby providing data '11' to the semiconductor device. Can be written. The first reset current IRESET_1 is shown as '□' and represents the current flowing through the variable resistance element when the first reset voltage VRESET_1 is applied. For example, the first reset voltage VRESET_1 is about 3.2 V. In this way, data '01' may be written in the semiconductor device. The second reset current IRESET_2 is shown as '○' and represents the current flowing through the variable resistance element when the second reset voltage VRESET_2 is applied. For example, the second reset voltage VRESET_2 is about 3.3V. In this way, data '10' may be written in the semiconductor device. The third reset current IRESET_3 is shown as 'Δ' and represents a current flowing through the variable resistance element when the third reset voltage VRESET_3 is applied. For example, the third reset voltage VRESET_3 is about 3.4 V. In this way, data '00' may be written to the semiconductor device.

In FIG. 20, the set current IST maintains a constant level, while the first to third reset currents IRESET_1, IRESET_2, and IRESET_3 have a large dispersion. Therefore, sufficient sensing margin may not be secured between the first reset current IRESET_1 and the second reset current IRESET_2, and thus, data '01' or data '10' cannot be effectively written to the semiconductor device. A problem arises. Also, it can be seen that a sufficient sensing margin is not secured between the second reset current IRESET_2 and the third reset current IRESET_3. Accordingly, data '10' or data '00' can be effectively written to the semiconductor device. Unable problem occurs.

FIG. 21 is a graph illustrating a current distribution of a variable resistance element included in the semiconductor device when the method of operating the semiconductor device according to the embodiment is performed.

Referring to FIG. 21, the X axis represents the number of set cycles or the number of reset cycles, and the Y axis represents the current distribution of the variable resistance element in A units. In this case, the set current ISET represents a current flowing through the variable resistance element when the set voltage VSET is applied. For example, the set voltage may be about −3.0 V, thereby providing data '11' to the semiconductor device. Can be written. The first reset current IRESET_1 is shown as '□' and represents the current flowing through the variable resistance element when the first reset voltage VRESET_1 is applied. For example, the first reset voltage VRESET_1 is about 3.2 V. In this way, data '01' may be written in the semiconductor device. The second reset current IRESET_2 is shown as '○' and represents the current flowing through the variable resistance element when the second reset voltage VRESET_2 is applied. For example, the second reset voltage VRESET_2 is about 3.3V. In this way, data '10' may be written in the semiconductor device. The third reset current IRESET_3 is shown as 'Δ' and represents a current flowing through the variable resistance element when the third reset voltage VRESET_3 is applied. For example, the third reset voltage VRESET_3 is about 3.4 V. In this way, data '00' may be written to the semiconductor device.

In FIG. 21, it can be seen that the set current IST maintains a constant level, and the distribution of the first, second, and third reset currents IRESET_1, IRESET_2, and IRESET_3 is greatly improved compared to FIG. 20. Accordingly, sufficient sensing margin can be secured between the first reset current IRESET_1 and the second reset current IRESET_2, thereby effectively writing data '01' or data '10' into the semiconductor device. In addition, sufficient sensing margin may be secured between the second reset current IRESET_2 and the third reset current IRESET_3, thereby effectively writing data '10' or data '00' into the semiconductor device. As described above, according to the present embodiment, by improving the distribution of the off current of the variable resistance element, the reliability of the semiconductor device including the variable resistance element can be greatly improved.

FIG. 22 is a circuit diagram illustrating a semiconductor device including a variable resistance device according to an example embodiment. FIG.

Referring to FIG. 22, the semiconductor device may be, for example, a nonvolatile memory device, and the unit cell MC1 of the nonvolatile memory device may include a variable resistance element R and a diode D. Here, the variable resistance element R may be implemented substantially the same as the variable resistance element 10 shown in FIG. 1. One end of the variable resistance element R is connected to the bit line BL, and the other end thereof is connected to the diode D. The diode D may operate in both directions, and may perform a selection operation on the unit cell MC1 according to a voltage applied to the word line WL.

When the semiconductor device is a single bit nonvolatile memory device, when a reset voltage is applied to the variable resistor device R, the variable resistor device R may change from low resistance to high resistance so that data '0' may be written. When a voltage is applied, the variable resistance element R is changed from high resistance to low resistance so that data '1' may be written. At this time, when the data '0' is written to the semiconductor device, the reset voltage is repeatedly applied to the variable resistance element R until the current flowing through the variable resistance element R is included in the predetermined current range. Can be applied.

On the other hand, when the semiconductor device is a multi-bit nonvolatile memory device, when the first reset voltage is applied to the variable resistance device R, the variable resistance device R is changed from a low resistance to a first high resistance so that the data '01' is stored. When the second reset voltage having a higher voltage level than the first reset voltage is applied, the variable resistance element R may be changed to a second high resistance so that the data '10' may be written. When a third reset voltage having a high voltage level is applied, the variable resistance element R may be changed to a third high resistance to write data '00', and when the set voltage is applied, the variable resistance element R may be first to first. The data '11' may be written by changing from the third high resistance to the low resistance.

When the data '01' is written to the semiconductor device, the first reset voltage is variable until the current flowing in the variable resistance element R to which the first reset voltage is applied is included in the first current range. The resistance element R may be repeatedly applied. In addition, when an operation of writing data '10' into the semiconductor device is performed, the second reset voltage is maintained until the current flowing in the variable resistance element R to which the second reset voltage is applied is included in the first current range. The variable resistance element R may be repeatedly applied. In addition, when the data '00' is written to the semiconductor device, the third reset voltage is variable until the current flowing in the variable resistance element R to which the third reset voltage is applied is included in the first current range. The resistance element R may be repeatedly applied.

FIG. 23 is a circuit diagram illustrating a semiconductor device including a variable resistance device according to example embodiments. FIG.

Referring to FIG. 22, a semiconductor device may be, for example, a nonvolatile memory device, and the unit cell MC2 of the nonvolatile memory device may include a variable resistance element R and an access transistor T. Referring to FIG. Here, the variable resistance element R may be implemented substantially the same as the variable resistance element 10 shown in FIG. 1. One end of the variable resistance element R is connected to the bit line BL, and the other end thereof is connected to the access transistor T. The access transistor T has a gate connected to the word line WL, a drain connected to the other end of the variable resistance element R, and a source connected to the source line SL. In this case, the access transistor T may be turned on or off according to a voltage applied to the word line WL to perform a selection operation on the unit cell MC2.

When the semiconductor device is a single bit nonvolatile memory device, when a reset voltage is applied to the variable resistor device R, the variable resistor device R may change from low resistance to high resistance so that data '0' may be written. When a voltage is applied, the variable resistance element R is changed from high resistance to low resistance so that data '1' may be written. At this time, when the data '0' is written to the semiconductor device, the reset voltage is repeatedly applied to the variable resistance element R until the current flowing through the variable resistance element R is included in the predetermined current range. Can be applied.

On the other hand, when the semiconductor device is a multi-bit nonvolatile memory device, when the first reset voltage is applied to the variable resistance device R, the variable resistance device R is changed from a low resistance to a first high resistance so that the data '01' is stored. When the second reset voltage having a higher voltage level than the first reset voltage is applied, the variable resistance element R may be changed to a second high resistance so that the data '10' may be written. When a third reset voltage having a high voltage level is applied, the variable resistance element R may be changed to a third high resistance to write data '00', and when the set voltage is applied, the variable resistance element R may be first to first. The data '11' may be written by changing from the third high resistance to the low resistance.

When the data '01' is written to the semiconductor device, the first reset voltage is variable until the current flowing in the variable resistance element R to which the first reset voltage is applied is included in the first current range. The resistance element R may be repeatedly applied. In addition, when an operation of writing data '10' into the semiconductor device is performed, the second reset voltage is maintained until the current flowing in the variable resistance element R to which the second reset voltage is applied is included in the first current range. The variable resistance element R may be repeatedly applied. In addition, when the data '00' is written to the semiconductor device, the third reset voltage is variable until the current flowing in the variable resistance element R to which the third reset voltage is applied is included in the first current range. The resistance element R may be repeatedly applied.

24 is a cross-sectional view illustrating an example of the semiconductor device of FIG. 23.

Referring to FIG. 24, an isolation layer 505 is provided in a predetermined region of the semiconductor substrate 500 to define an active region. A drain region 510 and a source region 515 are spaced apart from each other in the active region. The gate insulating layer 520 is disposed on the active region between the drain region 510 and the source region 515, and the gate electrode 525 is disposed on the gate insulating layer 520. In this case, the gate electrode 525 may extend to serve as a word line or be connected to the word line. The gate electrode 525, the drain region 510, and the source region 515 constitute an access transistor T.

A first interlayer insulating layer 530 is formed on the access transistor T, and first and second contact plugs CP1 and CP2 are formed in the first interlayer insulating layer 530. The source region 515 may be connected to the source line SL by the first contact plug CP1, and the drain region 510 may be connected to the lower electrode 540 by the second contact plug CP2.

The second interlayer insulating layer 560 is formed on the first interlayer insulating layer 530, and the lower electrode 540, the variable resistance material layer 545, and the upper electrode 550 are formed in a portion of the second interlayer insulating layer 560. Are formed sequentially. The upper electrode 550 may be connected to the bit line 570 through the third contact plug CP3. The lower electrode 540, the variable resistance material layer 545, and the upper electrode 550 constitute a variable resistance element R, and the variable resistance element R corresponds to the variable resistance element 10 of FIG. 1. .

In the above, the case where the variable resistance device according to the embodiments of the present invention is included in a semiconductor device such as a single bit nonvolatile memory device or a multibit nonvolatile memory device has been described above. However, the variable resistance device according to the embodiments of the present invention may be included in a logic gate and applied to a logic circuit. In this case, the area of the logic circuit may be reduced and the degree of integration may be improved. Specifically, the variable resistance device according to an embodiment of the present invention may be applied to a memristor. Therefore, the operation method of the memristor can be implemented substantially similarly to the operation of the semiconductor device illustrated in FIGS. 7 to 19. Here, the memristor represents an element having a characteristic in which the resistance changes according to the stored direction and amount of the current and the like, which stores the direction and amount of the current and the like.

25 is a block diagram illustrating a semiconductor device including a variable resistance device according to example embodiments.

Referring to FIG. 25, a nonvolatile memory device 100 may include a memory cell array including a plurality of unit cells (eg, MC1 of FIG. 22 or MC2 of FIG. 23) arranged in a matrix form along rows and columns. 101, a row decoder 102 for activating unit cells in the memory cell array 101 sequentially, row by row, a column decoder 103, and a column decoder for activating unit cells in the memory cell array 101 sequentially by row The sense amplifier 104 amplifies the current value output from the 103, the buffer 105 stores a reference current value, the current value amplified from the sense amplifier 104 and the reference current value stored in the buffer 105 A comparator 106 for comparing, a write circuit 108 for applying a set / reset signal to the activated unit memory cells via the row decoder 102 and the column decoder 103, the buffer 105, and the comparator 106 And control the operation of the write circuit 108. May include a control circuit 107.

For example, after the reset voltage is applied to the variable resistance element in the unit cell by the write circuit 108 (step 120 in FIG. 7), the row decoder 102 is used to sense the reset current (step 130 in FIG. 7). ) Activates one row of memory cell array 101, and column decoder 103 activates any column of memory cell array 101. Therefore, the current value (ie, reset current) of the OFF state of the unit cell in violation of the activated rows and columns can be sensed. The current value sensed by the column decoder 103 may be amplified by the sense amplifier 104 and then provided to the comparator 106.

Thereafter, to determine whether the reset current is within the first current range (step 140 of FIG. 7), the comparator 106 may compare the sensed current value with the reference current value. The reference current value may be a predetermined current value to improve the distribution of the off current, and the reference current value may be stored in the buffer 105. In order to store the reference current value, a reference element (not shown) such as a passive element or a transistor may be used.

Comparator 106 may compare the sensed current value (ie, reset current) with the first current range and provide the result to control circuit 107. For example, when the sensed current value (ie, reset current) is included in the first current range, the comparator 106 may transmit the output signal of the first state to the control circuit. Conversely, when the sensed current value (ie, reset current) is not included in the first current range, the comparator 106 may deliver the output signal of the second state to the control circuit.

The control circuit 107 operates to implement the operating method according to the above-described embodiments. For example, when the control circuit 107 receives the output signal of the first state from the comparator 106, it is determined that the reset operation is normally performed (the ending step of Fig. 7). On the other hand, when the control circuit 107 receives the output signal of the second state from the comparator 106, the control circuit 107 additionally performs the steps (120, 130 and 140 of FIG. 7). In order to do so, the write circuit 108, the sense amplifier 104, the buffer 105, the comparator 106, and the like can be controlled. Therefore, a sensing margin can be sufficiently secured between the 'on' state and the 'off' state of the variable resistance element (10 of FIG. 1 and 10 ′ of FIG. 2).

The control circuit 107 may store the reference current value in the buffer 105. When the semiconductor device intends to achieve a high sensing margin, the control circuit 107 may set a reference current value to narrow the first current range and store the reference current value in the buffer 106. When the semiconductor device intends to achieve a relatively low sensing margin, the control circuit 107 may set a reference current value to increase the first current range and store the reference current value in the buffer 106.

26 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 26, the memory card 600 includes a controller 610 and a memory 620, which may be arranged to exchange electrical signals. For example, when the controller 610 issues a command, the memory 620 may transmit data. The memory 620 may include a nonvolatile memory device including a variable resistance device according to any one of the embodiments of the present invention described above.

The memory card 600 may include various types of cards, for example, a memory stick card, a smart media card (SM), a secure digital (SD), and a mini secure digital card ( It can be used in a memory device such as a mini secure digital card (mini SD), or a multi media card (MMC).

27 is a block diagram schematically illustrating an electronic system according to an embodiment of the present invention.

Referring to FIG. 27, the electronic system 700 may include a processor 710, a memory 720, an input / output device 730, and an interface 740. The electronic system 700 may be a mobile system or a system for transmitting or receiving information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player or a memory card. Can be.

The processor 710 may execute a program and control the electronic system 700. Here, the processor 710 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device.

The input / output device 730 may be used to input or output data of the electronic system 700. The electronic system 700 may be connected to an external device, such as a personal computer or a network, using the input / output device 730 to exchange data with the external device. Here, the input / output device 730 may be, for example, a keypad, a keyboard, or a display.

The memory 720 may store code and / or data for the operation of the processor 710, and / or may store data processed by the processor 710. Here, the memory 720 may include a nonvolatile memory device including a variable resistance device according to any one of the above-described embodiments of the present invention.

The interface 740 may be a data transmission path between the electronic system 700 and another external device. The processor 710, the memory 730, the input / output device 730, and the interface 740 may communicate with each other via the bus 750.

For example, electronic system 700 may be a mobile phone, MP3 player, navigation, portable multimedia player (PMP), solid state drive (SSD) or household appliance (household). appliances).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

Claims (28)

A method of operating a semiconductor device including a variable resistance element,
Applying a first voltage to the variable resistance element such that the resistance of the variable resistance element is changed from a first resistance to a second resistance that is different from the first resistance;
Sensing a first current flowing through the variable resistance element to which the first voltage is applied;
Determining whether the first current is within a predetermined first current range; And
And applying an additional first voltage having the same voltage level as the first voltage to the variable resistance element when the first current is not within the predetermined first current range. The method of claim 1,
The first resistor is a set resistor, the second resistor is a reset resistor, and the second resistor is larger than the first resistor. The method of claim 1,
The sensing of the first current flowing through the variable resistance element may include applying a read voltage having an absolute magnitude smaller than the first voltage, thereby flowing the first current flowing through the variable resistance element to which the first voltage is applied. Operating method of a semiconductor device, characterized in that for detecting. The method of claim 1,
The application time of the first voltage is a method of operating a semiconductor device, characterized in that 1 μs to 1 ns. The method of claim 1,
And the additional first voltage has the same pulse width as the first voltage. The method of claim 2,
The first current range is predetermined between an on current flowing through the variable resistance element when the variable resistance element has the first resistance and an off current flowing through the variable resistance element when the variable resistance element has the second resistance. And a predetermined sensing margin of the sensing margin. The method of claim 2,
The first current range may include a first off current flowing through the variable resistance element when the variable resistance element has the second resistance, and a variable resistance element when the variable resistance element has a third resistance greater than the second resistance. And a predetermined sensing margin is secured between the second off currents flowing in the semiconductor device. The method of claim 1,
Detecting the first current and determining whether the first current is within the predetermined first current range with respect to the variable resistance element to which the additional first voltage is applied. Method of operation of a semiconductor device comprising a. The method of claim 8,
Applying the additional first voltage to the variable resistance element, sensing the first current, and the first current until the first current is within the predetermined first current range; And repeating the step of determining whether it is within the first current range. The method of claim 1,
Before performing the step of determining whether the first current falls within the predetermined first current range, determining whether the first current falls within a second current range that is a current range of data corresponding to the second resistance. The method of operating a semiconductor device further comprising. The method of claim 10,
And wherein the first current range is included in the second current range. The method of claim 10,
Changing the voltage level of the first voltage when the first current is greater than the maximum value of the second current range. The method of claim 12,
And applying the first voltage having the voltage level changed and sensing the first current to the variable resistance element repeatedly. The method of claim 10,
If the first current is less than a minimum value of the second current range, applying a second voltage to the variable resistance element such that the resistance of the variable resistance element is changed from the second resistance to the first resistance. Method of operation of a semiconductor device comprising a. The method of claim 14,
And repeating the step of applying the first voltage and sensing the first current to the variable resistance element to which the second voltage is applied. The method of claim 1,
Determining whether the first current is within the predetermined first current range,
Determining whether the first current is equal to or less than a maximum value of the predetermined first current range; And
And determining whether the first current is equal to or greater than a minimum value of the predetermined first current range. The method of claim 1,
The determining whether the first current is within the first current range may include determining whether a difference between the on current flowing through the variable resistance element and the first current is greater than or equal to a predetermined level when the variable resistance element has the first resistance. It is determined whether or not the operation method of a semiconductor device. The method of claim 1,
Applying a second voltage to the variable resistance element such that the resistance of the variable resistance element is changed from the second resistor to the first resistor; And
And detecting a second current flowing through the variable resistance element to which the second voltage is applied. The method of claim 18,
The sensing of the second current flowing through the variable resistance element may include applying a read voltage having an absolute value smaller than the first voltage and the second voltage to supply the second voltage applied to the variable resistance element to which the second voltage is applied. 2 A method for operating a semiconductor device, characterized by sensing current. The method of claim 18,
The application time of the second voltage is a method of operating a semiconductor device, characterized in that 1 μs to 1 ns. The method of claim 18,
The applying of the first voltage to the variable resistance element is performed after the step of sensing the second current. The method of claim 18,
Determining that the second current is within a third current range; And
If the second current is not within the third current range, further comprising applying an additional second voltage having the same voltage level as the second voltage to the variable resistance element. How it works. The method of claim 22,
And when the second current is within the third current range, applying the first voltage to the variable resistance element. The method of claim 22,
And sensing the second current and determining whether the second current is within the third current range with respect to the variable resistance element to which the additional second voltage is applied. How the device works. As a variable resistance element,
A first electrode and a second electrode; And
Disposed between the first electrode and the second electrode, and when a first voltage is applied between the first electrode and the second electrode, the first resistance is changed from a first resistor to a second resistor that is larger than the first resistor; A variable resistance material layer that changes from the second resistor to the first resistor when a voltage is applied,
When the variable resistance material layer has the second resistance, the variable voltage is repeatedly applied to the variable resistance material layer until the current flowing through the variable resistance element is within the first current range. Resistance element. 26. The method of claim 25,
The variable resistance material layer is changed from the second resistor to a third resistor larger than the second resistor when a third voltage having a voltage level higher than the first voltage is applied,
When the variable resistance material layer has the third resistance, the variable voltage is repeatedly applied to the variable resistance material layer until a current flowing through the variable resistance element is within a second current range. Resistance element. A variable resistance element that changes from a first resistor to a second resistor larger than the first resistor when a first voltage is applied, and changes from the second resistor to a first resistor when a second voltage is applied; And
A selection device connected in series with the variable resistance device;
And when the variable resistance element has the second resistor, repeatedly applying the first voltage to the variable resistance element until a current flowing through the variable resistance element is within a first current range. The method of claim 27,
The variable resistance element is changed from the second resistor to a third resistor larger than the second resistor when a third voltage having a voltage level higher than the first voltage is applied,
When the variable resistance element has the third resistor, the variable resistance element is repeatedly applied to the variable resistance element until the current flowing through the variable resistance element is within the second current range. .

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