KR20120072952A - Multicore system and memory management device for multicore system - Google Patents

Abstract

PURPOSE: A multi-core system and a memory management device thereof are provided to reduce unnecessary network traffic and simplify a system structure by selectively loading a page which is accessed by a processor on a cache. CONSTITUTION: A first TLB(Translation Lookaside Buffer) exception processor(211) duplicates a page descriptor having a loading location determining field to a TLB of a first processor. The TLB indicates a page which the first processor accesses and indicates wether the page is loaded to a cache of the first processor from a memory area. If the page is a write-shared page, a second TLB exception processor(212) transfers an interrupt message to the second processor.

Description

Multicore system and memory management device for multicore system}

It relates to the coherency policy techniques of multicore systems and multicore systems that include multiple processing cores.

In general, a multicore system refers to a processor that has two or more processing cores to process several tasks at once. Multi-core processors have been in the spotlight recently because they are advantageous in terms of performance and power savings over single-core processors.

Multi-core systems include a variety of heterogeneous types that can be used as symmetric multi-core systems (SMP, Symmetric Multi-Processing) with multiple cores, and General Purpose Processors (GPPs) such as Digital Processing Processors (DSPs) or Graphic Processing Units (GPUs). There is an asymmetric multi-processing system (AMP) consisting of cores.

In a multicore system, each processing core executes a task independently. As a result, data inconsistencies may occur when different processing cores simultaneously access a memory area. To avoid such data inconsistencies, most multicore systems employ a coherent cache architecture.

Representative coherent cache architectures include snooping-based coherent cache and directory-based coherent cache.

Snooping-based coherent caches are the most commonly used techniques in real-world processors, providing coherence by snooping which memory blocks are accessed by each processing core on a shared bus. In the case of snooping-based coherent caches, all memory requests are delivered to all processors using a shared bus, making them unsuitable for chip multi-process (CMP) integration with a large number of processing cores.

Directory-based coherent cache is a technique that sends a coherent message to only those processing cores when there is a directory that records which processing core has access to what authority in each memory block stored in the cache. Therefore, scalability is better than snooping-based coherent cache, but the complexity of hardware design is so high that it is not suitable for CMP.

A memory management apparatus of a multicore system applicable to a CMP in which a large number of processing cores are integrated, and a multicore system to which such a memory management apparatus is applied are provided.

A memory management apparatus according to an aspect of the present invention is a load position indicating a page to be accessed by a first processor and indicating whether the page is loaded from a memory area into a cache of the first processor or into a local store of the first processor. A first TLB exception handler that copies the page descriptor with decision fields to the translation lookaside buffer (TLB) of the first processor, and a write-shared page where the page must ensure page coherence page), forward the interrupt message to the second processor so that the cache of the second processor that accessed the page is flushed and the TLB of the second processor is invalidated, and flush the cache of the first processor according to the response of the second processor. And a second TLB exception processing unit that modifies the load location determination field.

In addition, a multicore system according to an aspect of the present invention may include a first core comprising a first processor, a first cache not providing memory consistency, and a first local store providing memory consistency, a second processor, A second core comprising a second cache that does not provide memory coherence, and a second local store that provides memory coherence, and according to the load position determination bits of the page descriptors regarding pages that the first or second processor is trying to access. It may include a memory management unit for copying the page to the first or second cache or to the first or second local store.

According to the disclosure, the system accesses the pages that are accessed by the processor by selectively loading and managing them in the local store where the consistency policy is supported and the cache where the consistency policy is not supported, according to the necessity of guaranteeing the consistency of the pages. The structure can be simplified.

1 illustrates a multicore system according to one embodiment of the invention.
2 illustrates a memory management apparatus of a multicore system according to an exemplary embodiment of the present invention.
3 illustrates a load position determination field of a page descriptor according to an embodiment of the present invention.
4 through 7 illustrate a memory management operation of a multicore system according to an embodiment of the present invention.

The virtual memory area accessed by the processor in the virtual memory is divided into pages. Among these pages, a page in which coherence should be guaranteed is accessed by a plurality of processors, and at least one of the pages may perform a write operation on the page. Such a page is called a write shared page.

According to a memory system design in accordance with an aspect of the present invention, consistency for write shared pages may be provided by a local store. The local store can be a temporary store for each processor controlled by software. This local store is different from the cache controlled by the hardware.

Each processor's page request is made by a page descriptor that is copied into a translation lookaside buffer (TLB), which contains a specific field that indicates whether the page should be loaded into the local store or into a cache that does not provide consistency. It may include.

Hereinafter, specific examples for carrying out the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a multicore system according to one embodiment of the invention.

Referring to FIG. 1, the multicore system 100 includes a plurality of cores 110, a memory manager 120, and a main memory 130.

Each core 110 is connected in a tile or mesh structure. Each core 110 accesses a memory block of the main memory 130 in page units. The memory manager 120 performs various exception processing and operations of the core 110 to allow the cores 110 to access a specific page of the main memory 130 and perform a read / write operation while ensuring page coherence. To control.

Each core 110 includes a processor 111, TLBs 112, 113, L1 caches 114, 115, L2 cache 116, local store 117, DMA 118, and router / switch 119 ).

The processor 111 accesses a page of the main memory 130 through a page descriptor stored in translation lookaside buffers (TLBs) 112 and 113.

The TLBs 112 and 113 store page descriptors for pages to be accessed by the processor 111. The TLBs 112 and 113 may be divided into an I-TLB 112 storing a page descriptor of a page related to an instruction and a D-TLB 113 storing a page descriptor of a page related to data.

The L1 caches 114 and 115 temporarily store pages that the processor 111 wants to access. The processor 111 may quickly access a page through the L1 caches 114 and 115. The L1 caches 114 and 115 may be divided into an L1 instruction cache 114 that stores a page related to an instruction and an L1 data cache 115 that stores a page related to data.

The L1 data cache 115 may not provide data coherence. In other words, when the processor 111 accesses a page through the L1 data cache 115, the processor 111 may freely read and write data without considering data consistency.

The L2 cache 116 temporarily stores a page to be accessed by the processor 111. The L2 cache 116 is a cache that can be shared by a processor existing in another core and may be configured as Non-Unified Cache Access (NUCA). That is, the L2 cache 116 may be divided into slices and distributed to each core 110.

The local store 117 temporarily stores the page to be accessed by the processor 111. The local store 117 is managed by the memory manager 120 and may provide data consistency by managing the memory manager 120. In other words, when the processor 111 accesses a page through the local store 117, the page accessed by the processor 111 may be guaranteed page consistency by the memory manager 120.

The DMA 118 manages data transfer between the main memory 130 and the local store 117, and the router / switch 119 sends and receives network messages between the cores 110.

According to the present embodiment, a page that a processor 111 of a core 110 tries to access may be loaded into a cache (eg, 115) or a local store 117. Whether a page is loaded into cache 115 or into local store 117 may be determined according to a particular field of the page descriptor for that page. Also in accordance with this embodiment, the cache 115 does not provide page consistency and the local store 117 may provide page consistency.

This provides page consistency because certain fields in the page descriptor of that page are appropriately adjusted according to the need for ensuring page consistency for a page, and therefore the load location of the page is determined by the cache 117 or local store 117. At the same time, network traffic can be reduced to ensure consistency.

2 illustrates a memory management apparatus of a multicore system according to an exemplary embodiment of the present invention. This may be an example of some configurations of the memory manager 120 or the DMA 118 of FIG. 1.

1 and 2, the memory management apparatus 200 includes an exception processor 201 and a consistency guaranteeer 202.

When the processor 111 refers to the D-TLB 113 to access a page, the exception processor 201 may be called when the page descriptor of the page does not exist in the D-TLB 113.

The exception processing unit 201 may include a first exception processing unit 211 and a second exception processing unit 212.

The first exception processing unit 211 copies the page descriptor of the page that the processor 111 wants to access to the D-TLB 113. In this case, the page descriptor may have a predetermined load position determination field according to an embodiment of the present invention. The load position determination field may consist of one or two bit regions. The load location determination field indicates whether the page indicated by the page descriptor is loaded into the L1 data cache 115 or into the local store 117.

In addition, according to an aspect of the present invention, the first exception processing unit 211 may set a lock of the page descriptor while copying the page descriptor, and release the lock when the exception processing ends.

The second exception processor 212 determines whether the page indicated by the page descriptor is a write-shared page to which page coherence should be guaranteed. For example, when a plurality of processors have accessed the page and at least one processor has accessed the page for a write operation, the second exception processor 212 may set the page as a write sharing page.

If the page is a write shared page, the second exception handler 212 generates an interrupt message, forwards the generated interrupt message to other processors that have accessed the page, and receives a response to the message from other processors. Wait until. The generated interrupt message can be a request message that causes the cache of other processors that have accessed the page to be flushed and the TLB invalidated.

Each processor that receives the interrupt message flushes its cache (including invalidation), invalidates its TLB, and sends a response message. According to the response message, the second exception processor 212 flushes the L1 data cache 115 of the processor 111 and modifies the load position determination field of the page descriptor.

The consistency guarantee unit 202 controls the local store 117 of each core 110 to ensure page consistency according to a predetermined consistency protocol. For example, the consistency guarantee unit may allow the contents of the local store 117 to be reflected in the main memory 130 at a specific point in time according to the release coherency protocol, or invalidate the D-TLB 113 of the processors that have accessed the write shared page. .

3 illustrates a load position determination field of a page descriptor according to an embodiment of the present invention.

Referring to FIG. 3, C bits and L bits may be designated in the rich bit area of the page descriptor. For example, load position determination bit 11 indicates that the load position of the page indicated by the page descriptor is L1 cache and L2 cache. The load position determination bit 10 indicates that the load position of the page indicated by the page descriptor is the L2 cache. The load position determination bit 01 indicates that the load position of the page indicated by the page descriptor is a local store. Load position determination bit 11 indicates that the page indicated by the page descriptor is accessed by the processor directly, rather than via a cache or local store. In FIG. 3, the initial default value of the load positioning bit may be given as 11.

4 through 7 illustrate an operation of a memory device of a multicore system according to an exemplary embodiment of the present invention.

In FIG. 2 and FIG. 4, the processor # 1 refers to the D-TLB 410 to read the page A 401, but the exception processing unit 201 is called because a TLB miss occurs. The exception processor 201 copies the page descriptor 402 of the page A 401 to the D-TLB 410 of the processor # 1 in the memory area 130.

In this case, the exception processing unit 201 may set a lock on the page descriptor 402 until the page descriptor 402 is copied to the D-TLB 410 and the corresponding page is loaded.

Once the page descriptor 402 is copied to the D-TLB 410, processor # 1 accesses page A 401 via cache 420 or local store 430. In this case, since the load position determination field of the page descriptor 402 is '1', which is the default value, the page A 401 is loaded into the cache 420.

When the page A 401 is loaded, the exception processing unit 201 determines whether the page A 401 is a write-shared page. For example, the exception processing unit 201 may determine whether a plurality of processors have accessed the page indicated by the page descriptor 402 having the load position determination field '1', and at least one processor having accessed the page. It may be determined whether the page A 401 is a write shared page according to whether or not it has approached for a write operation. Page A 401 is not a write-sharing page because only processor # 1 is accessed by page A 401.

Subsequently, in FIG. 2 and FIG. 5, the processor # 2 refers to the D-TLB 510 to write the page A 501, but an exception processing unit 201 was called because a TLB miss occurred. The exception processing unit 201 copies the page descriptor 502 of the page A 501 to the D-TLB 510 of the processor # 2 in the memory area 130.

Once page descriptor 502 is copied to D-TLB 510, processor # 2 accesses page A 501 through cache 520 or local store 530. At this time, since the load position determination field of the page descriptor 502 is '1', which is the default value, the page A 501 is loaded into the cache 520.

When the page A 501 is loaded, the exception processing unit 201 determines whether the page A 501 is a write-shared page. For example, since processor # 1 has already accessed page A 401 in FIG. 4, and processor # 2 has performed a write operation on the same page A 501 in FIG. 5, the exception processing unit 201 may execute page A ( It may be determined that 501 is a write sharing page.

When page A 501 is determined to be a write shared page, the exception handler 201 transmits an interrupt message to another processor that has accessed page A 501, that is, processor # 1. Upon receiving this interrupt message, processor # 1 invalidates and flushes page A stored in cache 420 and invalidates the page descriptor stored in TLB 410 in FIG. Processor # 1 then sends a response message to processor # 2.

In addition, in response to the response message of the processor # 1, the exception processing unit 201 invalidates and flushes page A stored in the cache 520 in FIG. 5, and determines a load position of the page descriptor 502. Change the field to '0'.

Subsequently, in FIGS. 2 and 6, when processor # 1 tries to access page A 601 again, TLB miss is generated again because the TLB 610 is invalidated through FIGS. 4 and 5. The exception processor 201 called according to the TLB miss copies the page descriptor 602 of the page A 601 to the TLB 610 of the processor # 1.

Once page descriptor 602 is copied to D-TLB 610, processor # 1 accesses page A 601 via cache 620 or local store 630. At this time, since the load position determination field of the page descriptor 602 is changed to '0' through FIG. 6, the page A 601 is loaded into the local store 630.

2 and 7, when processor # 3 approaches page A 701, the page descriptor 702 of page A 701 is copied to the TLB 710 of processor # 3, as in FIG. It is possible for page A 701 to be loaded into the local store 730.

6 and 7, since the same page A 601 and 701 are simultaneously loaded into the local store 630 of the processor # 1 and the local store 730 of the processor # 3, the page according to the operation of the processor may be used. Coherence may not be guaranteed at (601) (701).

2, 6, and 7, the consistency guarantee unit 202 controls the local store 630 of the processor # 1 and the local store 730 of the processor # 3 to ensure page consistency. In other words, the consistency guarantee unit 202 may allow other processors to see the changes made by any one processor at a specific point in time according to a coherent protocol.

For example, according to the release consistency model, in FIG. 6, the local store (eg, FIG. 5 of FIG. 5) reflects the contents of the local store 630 to main memory 130 at the release point and accesses page A 601. It is possible to set the write sharing page stored at 520 and 730 of FIG. 7 to invalid. Each processor # 1, # 2, and # 3 can then check that the write-shared page stored in their local store is set to invalid, and then invalidate that page descriptor in the TLB for the write-shared page set to invalid. . However, this is merely an example of a release consistency model, and the consistency guarantee unit 202 may control page access order of each local store and each processor according to other consistency policies.

When the process as shown in FIGS. 5 to 7 is repeated, it can be seen that an operation for guaranteeing consistency is selectively performed through the local store only for pages that need to be guaranteed. In other words, the pages accessed by the processor are selectively loaded and managed according to the necessity of ensuring the consistency of the pages in the local store with the consistency policy and the cache without the consistency policy, thereby reducing unnecessary network traffic and simplifying the system structure. Can be.

Meanwhile, the embodiments of the present invention can be embodied as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device and the like, and also a carrier wave (for example, transmission via the Internet) . In addition, the computer-readable recording medium may be distributed over network-connected computer systems so that computer readable codes can be stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for implementing the present invention can be easily deduced by programmers skilled in the art to which the present invention belongs.

Furthermore, the above-described embodiments are intended to illustrate the present invention by way of example and the scope of the present invention will not be limited to the specific embodiments.

Claims (10)

A TLB of the first processor with a page descriptor having a load positioning field indicating whether the first processor is to access the page and whether the page is to be loaded from the memory area into the cache of the first processor or into the local store of the first processor. a first TLB exception processing unit for copying to a translation lookaside buffer; And
If the page is a write-shared page where page coherence should be ensured, an interrupt message is issued to flush the cache of the second processor that accessed the page and invalidate the TLB of the second processor. A second TLB exception processing unit for transmitting to a second processor, flushing the cache of the first processor and modifying the load location determination field according to a response of the second processor; Memory management apparatus of a multicore system comprising a.
The method of claim 1,
A consistency guarantee unit controlling local stores of the first and second processors to ensure page consistency according to a predetermined consistency protocol; Memory management apparatus of the multi-core system further comprising.
The method of claim 1, wherein the first TLB exception processing unit
And setting a lock on the page descriptor while copying the page descriptor to the TLB.
The method of claim 1, wherein the second TLB exception processing unit
And determining whether the page is a write shared page according to whether at least two processors have accessed the page and at least one of the processors has accessed the write operation.
The method of claim 1, wherein the second TLB exception processing unit
In response to the response of the second processor, a memory of a multicore system that modifies the load location determination field so that the page is loaded into the local store of the first or third processor when the first or third processor accesses the page. Management device.
The method of claim 1, wherein the load position determination field is
Memory management apparatus of a multicore system including at least one bit area.
The method of claim 2, wherein the consistency guarantee unit
The memory management apparatus of the multi-core system reflects the modified page in the memory region according to the release coherence protocol so that the modified page in the local store of one processor can refer to.
A first core comprising a first processor, a first cache that does not provide memory coherency, and a first local store that provides memory coherency;
A second core comprising a second processor, a second cache not providing memory coherency, and a second local store providing memory coherency;
A memory manager configured to copy the page to the first or second cache or to the first or second local store according to the load position determination bits of the page descriptor regarding the page to be accessed by the first or second processor; Multicore system comprising a.
8. The memory device of claim 7, wherein the memory manager
And modifying the load location determination bits when the page is a write-shared page where page coherence should be guaranteed.
8. The memory device of claim 7, wherein the memory manager
And controlling the first and second local stores to ensure page consistency according to a given consistency protocol.

Images