KR20120070440A - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

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Publication number
KR20120070440A
KR20120070440A KR1020100131998A KR20100131998A KR20120070440A KR 20120070440 A KR20120070440 A KR 20120070440A KR 1020100131998 A KR1020100131998 A KR 1020100131998A KR 20100131998 A KR20100131998 A KR 20100131998A KR 20120070440 A KR20120070440 A KR 20120070440A
Authority
KR
South Korea
Prior art keywords
high voltage
voltage
overlay window
cell array
test mode
Prior art date
Application number
KR1020100131998A
Other languages
Korean (ko)
Inventor
윤정혁
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100131998A priority Critical patent/KR20120070440A/en
Publication of KR20120070440A publication Critical patent/KR20120070440A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

Abstract

PURPOSE: A semiconductor device is provided to increase test efficiency by normally performing a write operation. CONSTITUTION: A voltage generating unit(124) supplies a first high voltage to a cell array. An overlay window controlling unit(142) generates a preliminary overlay window control signal. A voltage control unit selects a first high voltage or a second high voltage in response to a test mode signal. A level shift unit(144) outputs an overlay window control signal in response to the first high voltage or the second high voltage and the overlay window control signal. A temporary storage array temporarily stores write information by receiving the overlay window control signal.

Description

Semiconductor device {Semiconductor Apparatus}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits and, more particularly, to semiconductor devices using embedded functions.

Recently, a voltage higher than an external driving voltage (VDD) for the purpose of improving the performance of an overlay window resister storing the light information stored in the cell array once more in a semiconductor device using an embedded function. In some cases, a high voltage VPP is used to drive the in-cell array region.

On the other hand, when the test mode signal for testing the characteristics of the cell array region, the level of the high voltage (VPP) is sometimes lowered, at this time, the voltage level of the overlay window control signal for controlling the overlay window register is also lowered.

In this case, the overlay window operation does not work properly, the embedded function does not operate, and the write operation itself does not occur, and thus the characteristics of the cell array cannot be evaluated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor device for increasing test efficiency.

In an embodiment, a semiconductor device may include a power generator configured to supply a first high voltage to a cell array; And light information provided to the cell array by selectively receiving a second high voltage having a higher level than the first high voltage supplied from the power generation unit or the first high voltage supplied from the high voltage pad in response to a test mode signal. It includes an overlay window unit for storing the.

In another embodiment, a semiconductor device may include a cell array; A voltage generator configured to generate a first high voltage to drive the cell array; An overlay window unit for storing light information stored in the cell array; And a voltage adjuster connected between the cell array and the voltage generator and configured to provide the first high voltage or a second high voltage below the first high voltage according to a test mode signal.

In the semiconductor device according to the present disclosure, the overlay window operation may be normally performed by providing the overlay window unit with a second high voltage applied to the test mode signal for testing the cell array.

According to an exemplary embodiment of the present invention, a semiconductor device includes a voltage adjusting unit to selectively provide a first high voltage applied by a voltage generator or a second high voltage applied by a high voltage pad in response to a test mode signal to test the cell array. In this case, the first high voltage may be maintained in the overlay window unit.

Accordingly, the semiconductor device according to the present invention can normally perform a write operation and at the same time proceed with the test mode signal for measuring the characteristics of the cell array.

1 is a block diagram illustrating a semiconductor device in accordance with an embodiment of the present invention;
2 is a detailed circuit diagram illustrating a part of a semiconductor device according to an embodiment of the present invention;
3 is a block diagram showing a semiconductor device according to another embodiment of the present invention; and
4 is a detailed circuit diagram illustrating a portion of a semiconductor device according to another embodiment of the present invention.

1 is a block diagram illustrating a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 1, a semiconductor device 100 according to an embodiment of the present invention includes a cell array 122, a voltage generator 124, and an overlay window unit 140.

The cell array 122 may be configured of a plurality of memory banks (not shown), each of the memory banks may be configured of a plurality of memory blocks (not shown), and each of the memory blocks may have a matrix form. It includes a plurality of phase change memory cells (not shown) arranged.

The voltage generator 124 may generate a first high voltage VPP1 for driving the cell array 122.

The overlay window 140 is a means for storing write information including write addresses and write data stored in the cell array 122 once again in order to shorten the write time.

The overlay window 140 may generate the overlay window control signal ctl by a high voltage which is a high voltage of the external driving voltage VDD.

In this case, the level of the overlay window control signal ctl is one of the first high voltage VPP1 and the second high voltage VPP2 having a level higher than or equal to the first high voltage VPP1 used to drive the cell array 122. May have a voltage.

As illustrated in FIG. 1, the overlay window unit 140 includes an overlay window control unit 142 that generates a preliminary overlay window control signal Pre_ctl according to an external driving voltage VDD, and a preliminary overlay window provided by the overlay window control unit 142. An overlay generated by the level shift unit 144 and the level shift unit 144 that output the overlay window control signal ctl in response to the control signal Pre_ctl and the voltage signal A provided by the voltage adjusting unit 148. The first or second high voltage selected by the overlay window resistance array 146 and the test mode signals TM and TMB that receive the window control signal ctl and store the light information stored in the cell array 122. And a voltage adjusting unit 148 for providing a voltage signal A having VPP1 and VPP2 to the level shifting unit 144.

Here, the voltage adjusting unit 148 is more specifically, as shown in FIG. 2, of the node N11 connected between the cell array 122 and the voltage generating unit 124 in response to the test mode bar signal TMB. A first selector 148a for providing a potential, that is, a first high voltage VPP1, to the level shifter 144 and the second voltage provided from the high voltage pad 150 in response to the test mode signal TM. And a second selector 148b for providing a high voltage VPP2 to the level shifter 144.

More specifically, as illustrated in FIG. 2, the first selector 148a according to the present exemplary embodiment may be an NMOS transistor T21 that receives a test mode bar signal TMB as a gate signal. The drain of the NMOS transistor T21 may receive the first high voltage VPP1 applied from the node N11 connected between the cell array 122 and the voltage generator 124, and the source of the NMOS transistor T21 may be provided. It may be connected to the level shifter unit 144.

In addition, as shown in FIG. 2, the second selector 148b according to the present exemplary embodiment may be formed of, for example, a transmission gate TM21 turned on by the test mode signals TM and TMB. When the test mode signals TM and TMB are enabled, the second selector 148b may level the second high voltage VPP2 having a level higher than or equal to the first high voltage VPP1 from the high voltage pad 150. ) Can be provided.

In some embodiments, when testing the cell array 122 in the core region, the semiconductor device 100 may lower the level to a level lower than the first high voltage VPP1. Conventionally, when testing the cell array, when the first high voltage VPP1 is lowered, the level of the overlay window control signal may be lowered because the first high voltage applied to the overlay window portion is lowered. As a result, the overlay window did not work and the embedded function did not work. In addition, since the write operation is not performed, there is a case in which the characteristics of the cell array itself cannot be evaluated.

Therefore, the semiconductor device 100 according to the present invention provides the overlay window unit 140 with the second high voltage VPP2 applied from the high voltage pad 150 to the test mode signal for testing the cell array 122. You can make the window work normally. Accordingly, the semiconductor device according to the present invention can normally perform a write operation and at the same time proceed with the test mode signal for measuring the characteristics of the cell array.

3 is a block diagram illustrating a semiconductor device according to example embodiments of the inventive concepts.

As shown in FIG. 3, the semiconductor device 200 according to an embodiment of the present invention includes a core driver 220 and an overlay window 240.

The core driver 220 according to the present invention includes a cell array 222, a voltage generator 224 that provides a voltage for driving the cell array 222, and a voltage adjuster 226.

The cell array 222 may be composed of a plurality of memory banks (not shown), each memory bank may be composed of a plurality of memory blocks (not shown), and each memory block is arranged in a matrix form. A plurality of phase change memory cells (not shown).

The voltage generator 224 generates a first high voltage VPP1 for driving the cell array 222 and provides it to the cell array 222 and the overlay window unit 240.

The voltage adjustor 226 is formed between the cell array 222 and the voltage generator 224, and is applied to the first high voltage VPP1 applied by the voltage generator 224 in response to the test mode bar signal TMB. The second high voltage VPP2 applied from the high voltage pad (226b of FIG. 4) may be selected and provided to the core driver 220.

The voltage adjusting unit 226 according to the present invention includes an NMOS transistor T41 that receives a test mode bar signal TMB as a gate signal, as shown in FIG. 4. More specifically, the voltage adjusting unit 226 is configured to control the 42nd node (eg, by the second high voltage VPP2 provided from the high voltage pad 226b when the test mode bar signal TMB is disabled, that is, when the test mode signal enters). The potential of N42 is increased, and accordingly, the overlay window 240 may be provided with the voltage signal B having the second high voltage.

On the other hand, the voltage adjustor 226 overlays the first high voltage VPP1 generated by the voltage generator 224 when the test mode bar signal TMB is activated, that is, when the test mode signal does not proceed. 240 may be provided.

Meanwhile, the overlay window unit 240 according to the present invention is a means for separately storing write information including a write address and data in order to shorten the write time.

The overlay window 240 may generate the overlay window control signal ctl by a high voltage that is a high voltage of the external driving voltage VDD.

In this case, the level of the overlay window control signal ctl may have the first high voltage VPP1 used to drive the cell array 222.

More specifically, as shown in FIG. 3, the overlay window 240 according to the present invention includes an overlay window control unit 242 and an overlay window control unit that generate the preliminary overlay window control signal Pre_ctl according to the external driving voltage VDD. A level shift unit 244 for level shifting the preliminary overlay window control signal Pre_ctl provided in 242 and the first high voltage VPP1 provided in the voltage adjusting unit 226 to generate an overlay window control signal ctl; The overlay window resistance array 246 may receive the overlay window control signal ctl generated by the level shift unit 244 and store light information stored in the cell array 222.

As such, the present invention may provide the core driver 220 with a high voltage having different levels according to the test mode and the normal mode. When the cell array 222 of the core driver 220 is tested, a level lower than the first high voltage VPP1 may need to be provided to the cell array 22. In the past, the first high voltage VPP1 may be used. Lowering the first high voltage VPP1 applied to the overlay window unit 240 lowers the level of the overlay window control signal ctl. This causes a problem in the overlay window operation of temporarily storing the light information, so that the embedded function does not operate. In addition, since the write operation is not normally performed, the characteristics of the cell array 222 may not be evaluated.

However, the semiconductor device 200 according to the present invention includes a voltage adjusting unit 226 at the first high voltage VPP1 or the high voltage pad 226b applied by the voltage generating unit 224 in response to the test mode signal. By selectively applying the applied second high voltage VPP2 to the core driver 220, the first high voltage VPP1 may be maintained in the overlay window 240 even when the cell array 222 is tested. Accordingly, since the overlay window operation is normally performed, the write operation is normally executed and the test mode signal for measuring the characteristics of the cell array may be advanced.

As those skilled in the art can realize the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100, 200: semiconductor device
122, 222: cell array
124, 224: voltage generator
140 and 240: overlay window portion
142, 242: overlay window control
144, 244: level shift portion
146, 246: overlay window resistor array
148, 226: voltage regulator

Claims (8)

A power generator configured to supply a first high voltage to the cell array; And
In response to a test mode signal, light information provided to the cell array may be received by selectively applying a second high voltage having a level higher than the first high voltage supplied from the power generation unit or the first high voltage supplied from the high voltage pad. A semiconductor device comprising an overlay window unit for storing. The overlay window unit,
An overlay window controller configured to generate a preliminary overlay window control signal in response to an external driving voltage;
A voltage controller configured to select the first high voltage or the second high voltage in response to the test mode signal;
A level shift unit configured to output an overlay window control signal in response to the preliminary overlay window control signal output from the overlay window control unit and the first high voltage or the second high voltage provided from the voltage adjusting unit; And
And a temporary storage array configured to receive the overlay window control signal output from the level shift unit and temporarily store write information. The method of claim 2,
The voltage control unit,
A first selector configured to output the first high voltage provided at a node connected between the cell array and the power generator to the level shifter in response to the test mode signal; And
And a second selector configured to output the second high voltage applied from the high voltage pad to the level shifter in response to the test mode signal. The method of claim 3,
The first selection unit,
And when the test mode signal is deactivated, the semiconductor device is turned on. The method of claim 3,
The second selector is turned on when the test mode signal is activated. Cell arrays;
A voltage generator configured to generate a first high voltage to drive the cell array;
An overlay window unit for storing light information stored in the cell array; And
And a voltage adjuster connected between the cell array and the voltage generator and configured to provide the first high voltage or a second high voltage less than or equal to the first high voltage according to a test mode signal. The method of claim 6,
The voltage control unit,
The semiconductor device provides the first high voltage provided from the voltage generator to the cell array in the normal mode. The method of claim 7, wherein
The voltage control unit,
And in the case of the test mode signal, providing the second high voltage provided from a high voltage pad to the cell array.
KR1020100131998A 2010-12-21 2010-12-21 Semiconductor apparatus KR20120070440A (en)

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KR1020100131998A KR20120070440A (en) 2010-12-21 2010-12-21 Semiconductor apparatus

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Application Number Priority Date Filing Date Title
KR1020100131998A KR20120070440A (en) 2010-12-21 2010-12-21 Semiconductor apparatus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466391B2 (en) 2014-01-09 2016-10-11 SK Hynix Inc. Semiconductor device having fuse array with disconnectable voltage generator and method of operating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9466391B2 (en) 2014-01-09 2016-10-11 SK Hynix Inc. Semiconductor device having fuse array with disconnectable voltage generator and method of operating the same

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