KR20120069953A - Non-volitile memory device and method thereof - Google Patents

Non-volitile memory device and method thereof Download PDF

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Publication number
KR20120069953A
KR20120069953A KR1020100131300A KR20100131300A KR20120069953A KR 20120069953 A KR20120069953 A KR 20120069953A KR 1020100131300 A KR1020100131300 A KR 1020100131300A KR 20100131300 A KR20100131300 A KR 20100131300A KR 20120069953 A KR20120069953 A KR 20120069953A
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KR
South Korea
Prior art keywords
program
read
memory controller
memory device
register
Prior art date
Application number
KR1020100131300A
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Korean (ko)
Inventor
정병관
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020100131300A priority Critical patent/KR20120069953A/en
Publication of KR20120069953A publication Critical patent/KR20120069953A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits

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  • Read Only Memory (AREA)

Abstract

The nonvolatile memory device includes a host interface, a memory controller connected to the host interface, the memory controller including a program register, and a memory area controlled by the memory controller, wherein the program register read operation during a program operation on the memory area. If you need to perform this, temporarily store the program operation related information.

Description

Non-Volatile Memory Device and Method Thereof

The present invention relates to a nonvolatile memory device and a control method thereof, and more particularly, to a nonvolatile memory device and a control method thereof for controlling a program operation.

In general, nonvolatile semiconductor memory devices, such as NAND flash memory devices, include electrically erasable and programmable memory cells.

NAND flash memory features dozens of microseconds per kilobyte and hundreds of us program time.

When a user wants to read a specific page arbitrarily in the NAND flash memory, the program operation that is currently in progress is interrupted by using a reset signal, and the read operation is performed by a new read command. Or, once the program operation was all completed, the read operation had to be performed.

In the former case, the program operation currently in progress is interrupted, and therefore, the NAND flash memory device has been inefficiently used because the program must be executed again from the beginning using the program command after the read operation due to abnormal termination.

In the latter case, since the read operation can be performed once the program is completed, the waiting time for the read may be as long as the program time, that is, several hundred us or more.

As described above, since there is a limit in easily controlling the program and read operations of the chip, it is difficult to proactively respond to a sudden change in the external environment and a request, and thus there is a high possibility of malfunction of the chip.

An object of the present invention is to provide a nonvolatile memory device for controlling a program operation and a control method thereof.

In order to achieve the technical object of the present invention, a host interface, a memory controller connected to the host interface and including a program register and a memory area controlled by the memory controller, the program register is a program for the memory area If a read operation is to be performed during execution, the program operation related information currently stored is temporarily stored.

According to another aspect of the present invention, there is provided a method of controlling a nonvolatile memory device, the method including: applying a read command during a program, storing program related information in progress when the read command is generated, and suspending a program operation; And performing a read operation according to the read command, and continuously performing the program operation by using the program related information when the read operation is completed.

According to an embodiment of the present invention, the operation efficiency of the nonvolatile memory device can be increased by easily controlling the switching of the program operation and the read operation.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention;
2 is a diagram illustrating the relationship between a program and a read command according to FIG. 1;
3 is a flowchart illustrating a method of controlling a nonvolatile memory device according to an exemplary embodiment of the present invention.

Hereinafter, the present invention will be described with reference to a block diagram or a flowchart for describing a nonvolatile memory device and a control method according to an embodiment of the present invention.

In addition, each block diagram may represent a portion of a module, segment, or code that includes one or more executable instructions for executing a specified logical function (s). It should also be noted that in some alternative implementations, the functions mentioned in the blocks may occur out of order. For example, the two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the corresponding function.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention. The nonvolatile memory device will be exemplified as a memory device using NAND flash memory.

Referring to FIG. 1, the nonvolatile memory device 100 includes a host interface 110, a buffer unit 120, an MCU 130, a memory controller 140, and a memory region 150.

First, the host interface 110 is connected to the buffer unit 120. The host interface 110 transmits and receives a control command, an address signal, and a data signal between an external host (not shown) and the buffer unit 120. The interface method between the host interface 110 and an external host (not shown) is any one of serial Serial Technology Attachment (SATA), parallel Parallel Advanced Technology attachment (PATA), and SCSI, Express Card, and PCI-Express methods. Can be and is not limited.

The buffer unit 120 buffers output signals from the host interface 110 or temporarily stores mapping information between logical addresses and physical addresses, block allocation information of a memory area, the number of times of block deletion, and data received from the outside. The buffer unit 120 may be a buffer using static random access memory (SRAM) or dynamic random access memory (DRAM).

The microcontrol unit 130 may transmit and receive a control command, an address signal, a data signal, and the like between the host interface 110, or may control the memory controller 140 by such signals.

Meanwhile, the memory controller 140 receives input data and a write command from the host interface 110 as usual, and controls the input data to be written to the memory area 150. Similarly, when the memory controller 140 receives a read command from the host interface 110, the memory controller 140 reads data from the memory area 150 and outputs the data to the outside.

In particular, the memory controller 140 according to an embodiment of the present invention includes a program register 145.

The program register 145 is a storage location for temporarily storing program related information currently being executed.

In other words, when a new read command is generated during the program, the program completed information up to now can be stored in the program register 145. Thus, the program currently in progress is suspended and a read operation by a new read command is performed. When the read operation is completed, the program may be continuously executed from the previous program completion operation by using the information stored in the program register 145.

In more detail, when a read command is generated during a program, the program register 145 stores current program related information and the like. For example, if the program is completed from logical address 0 to 1 but the read command occurs during the program at address 2, the logical address and physical address information of the address where the program is completed is stored. Thereafter, after the read operation is completed, the program operation may be started from the logical address 2 with reference to the information stored in the program register 145 instead of executing the program again from the beginning. Detailed description thereof will be described later with reference to the accompanying drawings.

The memory area 150 is controlled by the memory controller 140 to perform write, delete, and read operations of data. The memory region 150 may be a NAND flash memory. According to an embodiment of the present invention, a cell of a NAND flash memory may be a single level cell (SLC) or a multi level cell (MLC). The memory area 150 may include a plurality of chips formed of a plurality of blocks including a plurality of pages.

2 is a diagram illustrating a relationship between a program and a read command according to FIG. 1.

Referring to FIG. 2, the control of the program and read operations according to an embodiment of the present invention will be described in detail.

For convenience of description, it will be exemplified as executing a program from logical addresses 0 to 5.

First, a program command is issued (①).

Accordingly, the program is sequentially executed from the logical address 0 (②).

At this time, a case in which another block needs to be read occurs, and a read command is issued (3).

The program operation currently in progress is suspended by the newly generated read command RD START (4). At the same time, the program related information which is currently being processed is stored in the program register (see 145 of FIG. 1).

Read operation is performed to read the logical address 256 from the desired logical address 255 (⑤).

After reading the information of the desired block, read completion (RD END) is made (6).

After the read is completed, the program operation is continuously performed at the previous programmed logical address (⑦).

As described above, according to an embodiment of the present invention, if a new read command is generated during a program, it is necessary to wait until the program is completed or to force the program operation to end and perform the read operation, and then start the program from the beginning again. none. As will be appreciated by those skilled in the art, the program time is very long compared to the read time. Therefore, it is true that, when a read command to be processed urgently generated during a program is generated, proper control for this is difficult.

However, according to an embodiment of the present invention, if the program operation is suspended after temporarily storing the program related information which has been in progress up to now, the program operation is continuously performed by using the stored program related information after the read completion. Since it can be performed subsequently, the operation efficiency of the nonvolatile memory device is high.

Meanwhile, although the concept of controlling a simple program and read operation has been described herein, a method of applying the same may be various.

3 is a flowchart illustrating a method of controlling a nonvolatile memory device according to an exemplary embodiment of the present invention.

1 to 3, a control method of a nonvolatile memory device according to an embodiment of the present invention will be described.

Apply a program command (S10).

Initial conditions for executing a program are set according to the authorized program command (S20). For example, it may be an initial value voltage of a program pulse, a program pulse number, a program voltage to be increased, and the like.

It is determined whether there is a read command newly generated during the program (S30).

If a new read command is issued (Yes), program related information, etc., which has been programmed so far, is stored in the program register 145, and the program is suspended. If the read operation is performed (S32), and all the desired blocks are read, the read operation is completed (S34).

If no new read command is generated (No), a program pulse is applied to perform a program operation (S40).

Each time a program pulse is applied, it is determined whether a read command is newly generated during the program (S50).

As in the above-described method, if a new read command is generated (Yes), program related information, etc., which has been completed so far, is stored in the program register 145, and the program is suspended. If the read operation is performed (S52) and all the desired blocks are read, the read operation is completed (S54).

If a new read command has not been generated (No), a post-program verify operation is performed (S60).

If the program is not yet performed (N0), the operation of applying the program pulse again is repeated (S70). However, if the program is completed (Yes), the program operation is completed.

As described above, according to an embodiment of the present invention, even if a program operation takes a lot of time, the program related information is temporarily stored and used even if it is to be suspended according to an external request to prevent the program from being repeated again. Can be controlled to run the program subsequently.

For convenience of description, it is exemplified here as whether or not a read occurs every program pulse step, but the determination is not limited for each predetermined period pulse. However, a method of controlling the program operation that is currently being performed continuously without ignoring the read operation generated during the program operation satisfies the scope of the embodiments of the present invention.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

110: host interface 120: buffer unit
130: MCU 140: memory controller
145: program register 150: memory area

Claims (6)

A host interface;
A memory controller connected to the host interface and including a program register; And
A memory area controlled by the memory controller,
And the program register temporarily stores information related to a program operation which is currently in progress, when a read operation is to be performed during program execution of the memory area. The method of claim 1,
The memory controller,
When a read operation is to be performed during program execution, the nonvolatile memory device temporarily stores information related to a current program operation in the program register and temporarily suspends a program operation in progress. The method of claim 2,
The memory controller,
A nonvolatile memory device which stops a program operation that is in progress and performs a read operation according to the read command. The method of claim 3, wherein
The memory controller,
And the read operation is completed, and performs a program operation continuously to a previously advanced program operation by using the information of the program register. Applying a read command during the program;
Storing the program related information in progress when the read command is generated and suspending the program operation;
Performing a read operation according to the read command; And
And continuously performing the program operation by using the program related information when the read operation is completed. 6. The method of claim 5,
The program related information may include an initial value voltage of a program pulse, a program pulse number, and a program voltage to be increased.
KR1020100131300A 2010-12-21 2010-12-21 Non-volitile memory device and method thereof KR20120069953A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508400B1 (en) 2015-05-06 2016-11-29 SK Hynix Inc. Storage device and operating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508400B1 (en) 2015-05-06 2016-11-29 SK Hynix Inc. Storage device and operating method thereof

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