KR20120069110A - Semiconductor memory device and method of operating the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device and an operating method thereof are provided to improve an operation property by performing a program operation of a first memory string independently of a second memory string. CONSTITUTION: A first vertical memory string is connected between a pipe transistor and a common source line. A second vertical memory string is vertically connected between the pipe transistor and the bit line. An operation circuit group(130,140,150,160,170) outputs a pipe gate voltage for applying a program voltage, a pass voltage, and a pipe transistor. A control circuit(120) controls an operation circuit group for preventing the connection of the first vertical memory string and the second vertical memory string when the program operation of the second vertical memory string is performed.

Description

Semiconductor memory device and method of operating same

The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a semiconductor memory device including a memory array having a three-dimensional structure and a method of operating the same.

The semiconductor memory device includes a volatile memory device and a nonvolatile memory device. A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure in which a memory device is manufactured in a single layer on a silicon substrate has reached a limit, a semiconductor memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed.

As the structure of the memory device is changed, the operation method also changes. Therefore, new methods for improving the electrical characteristics of a three-dimensional semiconductor memory device have been proposed.

According to an embodiment of the present invention, a program operation of a first memory string vertically connected between a semiconductor substrate and a bit line is performed independently of a second memory string vertically connected between a semiconductor substrate and a common source line, thereby reducing power consumption. Can reduce and improve the operating characteristics.

A semiconductor memory device according to an embodiment of the present invention includes a memory string including a first vertical memory string connected between a pipe transistor and a common source line formed on a semiconductor substrate, and a second vertical memory string vertically connected between the pipe transistor and a bit line. And a program voltage for applying to a selected word line for a program operation of memory cells included in the memory string, a pass voltage for applying to unselected word lines, and a pipe gate voltage for applying to a pipe transistor. And a control circuit configured to control the operation circuit group to disconnect the connection of the first and second vertical memory strings when performing a program operation of the second vertical memory string.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes a first vertical memory string connected between a pipe transistor and a common source line formed on a semiconductor substrate, and a second vertical memory string vertically connected between the pipe transistor and a bit line. Providing memory strings, disconnecting the first and second vertical memory strings using a pipe transistor, and disconnecting the first and second vertical memory strings from the second vertical memory string. And performing a program operation of the selected memory cell of.

According to an embodiment of the present invention, a program operation of a first memory string vertically connected between a semiconductor substrate and a bit line is performed independently of a second memory string vertically connected between a semiconductor substrate and a common source line, thereby reducing power consumption. Can reduce and improve the operating characteristics.

1 is a circuit diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.
3 is a perspective view illustrating a structure of a semiconductor device implementing the circuit of FIG. 2.
4A and 4B are waveform diagrams illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a circuit diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device according to an embodiment of the present invention may include a memory array 110 including a plurality of memory blocks 110B and a program operation or read of memory cells included in the memory cell block 110B. An operation circuit group 130, 140, 150, 160, 170, 180 configured to perform an operation, and a control circuit 120 configured to control the operation circuit group 130, 140, 150, 160, 170, 180. . In the case of the NAND flash memory device, the operation circuit group includes the voltage supply circuits 130 and 140, the page buffer group 150, the column selection circuit 160, and the input / output circuit 170.

The memory blocks 110B of the memory array 110 include a plurality of strings connected between the bit lines BL1 to BLk and the common source line, and a detailed structure thereof will be described later.

The control circuit 120 outputs an internal command signal CMDi for a program operation, a read operation, or an erase operation in response to a command signal CMD input from an external controller (not shown), and according to the type of operation, a page buffer. The control signals PS SIGNALS for controlling the page buffers included in the group 150 are output. In addition, the control circuit 120 outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD.

The voltage supply circuits 130 and 140 may operate in response to the internal command signal CMDi of the control circuit 120 to perform operation voltages (eg, Vpgm, Vpass, Vpg) is supplied to the drain select line DSL, the word lines WL0,..., WLn, the pass gate PG, and the source select line SSL of the selected memory cell block. This voltage supply circuit includes a voltage generator circuit 130 and a row decoder 140.

The voltage generation circuit 130 outputs operating voltages for erase, read, or program operations of the memory cells as global lines in response to the internal command signal CMDi of the control circuit 120. In the program operation, the program lines Vpgm for applying to selected memory cells, a pass voltage Vpass for applying to unselected memory cells, and a pipe gate voltage Vpg for applying to a pipe gate are applied to the global lines. Will output

In response to the row address signals RADD of the control circuit 120, the row decoder 140 may select operating voltages generated by the voltage generation circuit 130 to select one of the memory cell blocks of the memory cell array 110. Transfers to local lines DSL, WL0 to WLn, PG, and SSL of block 110-1.

The page buffer group 150 includes a plurality of page buffers (not shown). The page buffers may be connected to the bit lines BL1 to BLk, and may be connected to each pair of bit lines including the even bit line and the odd bit line. Each page buffer stores the data in the cells Ca0, ..., Ck0 or reads the data from the cells according to the control signals PB SIGNALS of the control circuit 120. Adjust the voltage of BLk).

The column selection circuit 160 selects the page buffers included in the page buffer group 150 in response to the column address signal CADD output from the control circuit 120. Data for storing in the memory cell is input to the page buffer selected by the column selection circuit 160, or data sensed from the memory cell is output from the selected page buffer.

The input / output circuit 170 transfers data to the column selection circuit 160 under the control of the control circuit 120 to input data input from the outside into the page buffer group 150 for storage in memory cells during a program operation. do. The column selection circuit 160 sequentially transfers the transferred data to the page buffers of the page buffer group 150, and the page buffers store the input data in an internal latch. In addition, during the read operation, the input / output circuit 170 outputs data transferred through the column select circuit 160 from the page buffers of the page buffer group 150 to the outside.

Subsequently, the memory block includes memory strings having a three-dimensional structure. The structure of the memory block will be described below.

FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.

Referring to FIG. 2, a memory block includes a plurality of memory strings STa to STd (only four strings are shown for convenience). The unit memory string STa includes a drain select transistor DST having a drain connected to the bit line BL, a source select transistor SST having a source connected to the source line SL, and select transistors (drain select transistor and source). The plurality of memory cells C0 to C15 connected in series between the select transistors are included. Here, the number of memory cells may be changed according to design, and the following description will be given by using 16 memory cells as an example.

The pipe transistor PT is connected between the pair of memory cells C7 and C8 positioned in the middle of the three-dimensional memory string. Accordingly, some of the memory cells C0 to C7 of the memory cells C0 to C15 included in the cell string are connected in series between the source select transistor SST and the pipe transistor PT to form a first vertical memory string STaB. The remaining memory cells C8 ˜ C15 are connected in series between the drain select transistor DST and the pipe transistor PTr to form a second vertical memory string STaU.

The pipe transistor PT is formed on the substrate. The drain select transistor DST and the memory cells C8 to C15 of the second vertical memory string are arranged in series between the bit line BL and the pipe transistor PT in a vertical direction from the substrate. The source select transistor SST and the memory cells C0 to C7 of the second vertical memory string are arranged in series between the source line SL and the pipe transistor PT in a vertical direction from the substrate. The number of memory cells C0 to C7 of the first vertical memory string and the memory cells C8 to C15 of the second vertical memory string are preferably the same. As arranged perpendicularly to the memory cells C0 to C15, the channel direction of the first vertical memory string STaB and the second vertical memory string STaU is perpendicular to the substrate. As the memory cells C0 to C15 of the memory string ST are divided into first and second vertical memory strings, one string includes two vertical channel layers perpendicular to the substrate.

Here, the pipe transistor PTr electrically connects the channel layer of the first vertical memory string STaB and the channel layer of the second vertical memory string STaU. That is, the pipe transistor PTr may divide the channel region of the memory cells C0 to C7 included in the first vertical memory string STaB and the channel region of the memory cells C8 to C15 of the second vertical memory string STaU. Performs an electrical connection. The structure of the semiconductor device including the 3D memory string will be described in more detail as follows.

3 is a perspective view illustrating a structure of a semiconductor device implementing the circuit of FIG. 2.

Referring to FIG. 3, a memory block MS is provided with a plurality of memory strings MS. As will be described later, each memory string MS includes a plurality of electrically rewritable memory cells C0 to C15, and the memory cells C0 to C15 are connected in series. Memory cells C0 to C15 constituting the memory string MS are formed by stacking a plurality of semiconductor layers. Each memory string MS includes a U-shaped channel layer SC, word lines WL0-WL15 and a pipe gate PG.

The U-shaped channel layer SC is formed in a U shape when viewed in the row direction. The U-shaped channel layer SC connects a pair of columnar portions extending substantially perpendicular to the semiconductor substrate Ba and a connection portion JP formed to connect lower ends of the columnar portions CLa and CLb. Include. The columnar portions CLa and CLb may be cylindrical columnar or prismatic. In addition, the columnar portions CLa and CLb may be columnar. Here, the row direction is a direction perpendicular to the stacking direction, and the column direction described later is a direction perpendicular to the stacking direction and the row direction.

The U-shaped channel layer SC is arranged such that lines connecting the central axes of the pair of columnar portions CLa and CLb are parallel to the column direction. In addition, the U-shaped channel layer SC is arranged to form a matrix on a plane formed in the row direction and the column direction.

The word lines WL0 to WL15 of each layer have a form extending in parallel to the row direction. The word lines WL0 to WL15 of each layer are repeatedly formed of lines insulated from each other, separated from each other, and having a predetermined pitch in the column direction. The word line WL0 is formed on the same layer as the word line WL15. Similarly, the word line WL1 is formed on the same layer as the word line WL14, the word line WL6 is formed on the same layer as the word line WL9, and the word line WL7 is formed on the same layer as the word line WL8. do.

Gates of the memory cells C0 to C15 that are provided at the same position in the column direction and form a line in the row direction are respectively connected to the same word lines WL0 to WL15. Although not shown, the end portion in the row direction of each word line WL0 to WL15 is formed in a step shape. Each word line WL0 to WL15 is formed to surround a plurality of columnar portions arranged in a row in the row direction.

An oxide-nitride-oxide (ONO) layer (not shown) is formed between the word lines WL0 to WL15 and the columnar portions CLa and CLb. The ONO layer includes a tunnel insulation layer adjacent to the columnar portions CLa and CLb, a charge storage layer adjacent to the tunnel insulation layer, and a block insulation layer adjacent to the charge storage layer. The charge storage layer functions to accumulate charge like a conventional floating gate. In other words, the charge storage layer is formed to surround the entire surfaces of the columnar portions CLa and CLb and the connection portion JP, and each of the word lines WL0 to WL15 is formed to surround the charge storage layer. .

The drain select transistor DST includes a columnar channel layer CLa and a drain select line DSL. The columnar channel layer CLa is formed to extend in a direction perpendicular to the substrate Ba.

The drain select line DSL is provided above the top word line WL15 among the word lines. The drain select line DSL extends in parallel to the row direction. The drain select line DSL is repeatedly formed of lines having a predetermined pitch that alternates in the column direction so as to sandwich the source select line SSL. The drain select line DSL is formed to surround each of the plurality of columnar channel layers CLa arranged in a row direction with a gap interposed therebetween.

The source select transistor SST includes a columnar channel layer SLb and a source select line SSL. The source select line SSL is provided above the most significant word line WL0 among the word lines. The source select line SSL has a form extending in parallel to the row direction. The source select line SSL is repeatedly formed of lines having a predetermined pitch in the column direction to sandwich the drain select line DSL. The source select line SSL is formed to surround each of the plurality of columnar channel layers CLb arranged in a row direction with a gap interposed therebetween.

The pipe gate PG extends two-dimensionally in the row direction and the column direction to cover the lower portions of the plurality of connection portions JP.

The columnar channel layer CLb is formed adjacent to each other in the column direction. Upper ends of the pair of columnar channel layers CLb are connected to the source line SL. The source line SL is commonly connected to the pair of columnar channel layers CLb.

The bit lines BL may be formed at upper ends of the columnar channel layers CLa and may be connected to the columnar channel layers CLa through the plug PL. Each bit line BL is formed to be disposed above the source line SL. Each bit line BL is repeatedly formed with lines extending in the column direction and having a predetermined interval in the row direction.

A method of operating a semiconductor memory device having the above structure will be described below. 4A and 4B are waveform diagrams illustrating a method of operating a semiconductor memory device according to an embodiment of the present invention. Specifically, the program operation of the semiconductor memory device will be described as an example.

2 and 4A, a precharge voltage is applied to the bit lines BL1 and BL2 from the page buffer group 150 of FIG. 1 under the control of the control circuit 120 of FIG. 1. The page buffer group performs the precharge operation of the bit lines BL1 and BL2 under the control of the control circuit, and selectively performs the discharge operation of the bit lines BL1 and BL2 according to the data stored in the memory cells. do.

When the selected memory string STa includes a memory cell to be programmed (eg, C1), the memory strings STb and STc are unselected during a program operation, and the memory string STd includes a program inhibiting cell. The voltage supply circuits 130 and 140 of FIG. 1 apply a first voltage (eg, 4.5V) to the drain select line DSL for turning on the drain select transistor DST under the control of the control circuit. The ground voltage (eg, 0 V) is applied to the drain select line DSL of the memory strings STb and STc. As a result, the memory strings STa and STd are connected to the bit lines BL1 and BL2, respectively, and the unselected memory strings STb and STc are disconnected from the bit line BL1. Meanwhile, the voltage supply circuits 130 and 140 of FIG. 1 apply a ground voltage (eg, 0V) to the source select lines SSL so that the source select transistor SST is turned off. In addition, a second voltage (eg, 4.5V) is applied to the pipe gate line PG to turn on the pipe transistor PT.

As a result, the program inhibit string STd including the memory string STa and the program inhibit cell selected through the drain select transistors DST with the precharge voltages applied to the bit lines BL1 and BL2 turned on. The channel regions of the two vertical memory strings STaU are transferred. The precharge voltage is transferred to the channel regions of the first vertical memory strings STaB through the turned-on pipe transistor PT. As a result, the channel regions of the first and second vertical memory strings STaB and STaU are precharged.

Subsequently, the voltage of the selected bit line BL1 connected to the memory string STa including the selected memory cell C1 is discharged by the page buffer group under the control of the control circuit. At this time, the unselected bit line BL2 maintains a precharged state. As a result, the voltages of the channel regions of the selected memory string ST are also discharged to the selected bit line BL1 through the pipe transistor PT and the drain select transistor DST.

The voltage applied to the drain select line DSL of the selected memory string STa is lowered from the first voltage (eg, 4.5V) to the third voltage (eg, 2.3V) by the voltage supply circuit. Here, the third voltage may be applied at the same level as the precharge voltage applied during the precharge operation of the bit lines BL1 and BL2. In this case, the voltage of the drain select line DSL may be lowered to 0V from the first voltage and then increased to the third voltage. The voltage supply circuit applies a pass voltage Vpass of about 10V to the word lines WL0 to WL15 of the memory strings STa and STd under the control of the control circuit. As the pass voltage Vpass is applied, the voltage is increased by channel boosting in the channel region of the program inhibiting string STd. However, since the channel region of the selected memory string STa is electrically connected to the selected bit line BL1 to which the ground voltage is applied, the voltage region does not rise and remains discharged.

Thereafter, the program voltage Vpgm is applied to the word line (eg, WL1) selected by the voltage supply circuit according to the control of the control circuit. The selected memory cell C1 of the memory string STa is programmed by the voltage difference between the channel region and the word line. However, since the channel voltage of the program inhibit string STd is increased by channel boosting, the program inhibit cell is not programmed because the voltage difference between the channel region and the word line is low. After the program voltage Vpgm is applied for a predetermined time, the supply of all voltages is stopped and the program operation is completed.

In the above, the case in which the program target cell C1 is included in the first vertical memory string STaB connected between the pipe transistor PT and the source line SL has been described, and the program target cell C1 includes the bit line. A case of being included in the second vertical memory string STaU connected between BL1 and the pipe transistor PT is as follows.

When the pipe transistor PT is turned on even when the program operation of the memory cell C9 included in the second vertical memory string STaU is turned on, the channel of the first vertical memory string STaB of the program inhibition string STd is turned on. In order to generate boosting, a pass voltage must also be applied to the word lines WL0 to WL7. For this reason, since the voltage generation circuit 130 (in FIG. 1) needs to apply the pass voltage to the word lines WL0 to WL7 unnecessarily, power consumption may increase and operation characteristics may decrease. In addition, since the pass voltages must be applied to all the word lines WL0 to WL15, the time for increasing the potential of the word lines WL0 to WL15 from 0V to the pass voltage is increased.

Therefore, by performing the program operation of the second vertical memory string STaU independently of the first vertical memory string STaB, power consumption may be reduced and operation characteristics may be improved. More specifically described as follows.

2 and 4B, 0V is applied from the voltage supply circuits 130 and 140 of FIG. 1 to the pipe gate line PG according to the control circuit 120 of FIG. 1 so that the pipe transistor PT is turned off. The precharge voltage is applied to the bit lines BL1 and BL2 from the page buffer group 150 of FIG. 1 under the control of the control circuit.

When the selected memory string STa includes a memory cell to be programmed (for example, C9), the memory strings STb and STc are unselected during a program operation, and the memory string STd includes a program inhibiting cell. According to the control of the control circuit, the voltage supply circuits 130 and 140 of FIG. 1 may receive a first voltage (eg, 4.5V) for turning on the drain select transistors DST of the memory strings STa and STd. DSL), and a ground voltage (eg, 0V) is applied to the drain select lines DSL of the unselected memory strings STb and STc. As a result, the second vertical memory strings STaU of the memory strings STa and STd are connected to the bit lines BL1 and BL2, respectively, and the unselected memory strings STb and STc are the bit lines BL1. And the connection is cut off. Meanwhile, the voltage supply circuits 130 and 140 of FIG. 1 apply ground voltages (eg, 0V) to the source select lines SSL so that the source select transistors SST are turned off.

As a result, the program inhibit string STd including the memory string STa and the program inhibit cell selected through the drain select transistors DST with the precharge voltages applied to the bit lines BL1 and BL2 turned on. The channel regions of the two vertical memory strings STaU are transferred. However, since the pipe transistor PT is turned off, the precharge voltage is not transmitted to the channel region of the first vertical memory strings STaB. Thus, only the channel regions of the first vertical memory strings STaB of the memory strings STa and STd are precharged.

Subsequently, the voltage of the selected bit line BL1 connected to the memory string STa including the selected memory cell C9 is discharged by the page buffer group under the control of the control circuit. At this time, the unselected bit line BL2 maintains a precharged state. As a result, the channel region of the second vertical memory string STaU of the selected memory string STa is discharged to the selected bit line BL1 through the drain select transistor DST.

The voltage applied to the drain select line DSL of the selected memory string STa is lowered from the first voltage (eg, 4.5V) to the third voltage (eg, 2.3V) by the voltage supply circuit. Here, the third voltage may be applied at the same level as the precharge voltage applied during the precharge operation of the bit lines BL1 and BL2. In this case, the voltage of the drain select line DSL may be lowered to 0V from the first voltage and then increased to the third voltage.

In addition, the voltage supply circuits 130 and 140 of FIG. 1 apply a pass voltage Vpass of about 10V to the word lines WL8 to WL15 of the memory strings STa and STd under the control of the control circuit. . As the pass voltage Vpass is applied, the channel voltage is increased by channel boosting in the channel region of the second vertical memory string of the program inhibiting string STd. However, since the channel region of the second vertical memory string STaU of the selected memory string STa is electrically connected to the selected bit line BL1 to which the ground voltage is applied, the voltage is discharged without rising. Keep it.

Meanwhile, the pass voltage Vpass is not applied to the word lines WL0 to WL7 of the first vertical memory strings STaB of the memory strings STa and STd. Therefore, no channel boosting occurs in the channel region, and no voltage difference occurs between the word lines WL0 to WL7 and the channel region.

Thereafter, the program voltage Vpgm is applied to the word line (eg, WL9) selected by the voltage supply circuit according to the control of the control circuit. The selected memory cell C9 of the memory string STa is programmed by the voltage difference between the channel region and the word line. However, since the channel voltage of the program inhibit string STd is increased by channel boosting, the program inhibit cell is not programmed because the voltage difference between the channel region and the word line is low. After the program voltage Vpgm is applied for a predetermined time, the supply of all voltages is stopped and the program operation is completed.

As above, the first vertical memory string of the first vertical memory string is separated from the second vertical memory string of the first vertical memory string that is vertically connected between the semiconductor substrate and the bit line. Program operations are performed independently. Therefore, power consumption can be reduced and operation characteristics can be improved.

110: memory array 110B: memory block
120: control circuit 130: voltage generating circuit
140: row decoder 150: page buffer group
160: column selection circuit 170: input and output circuit
STa to STd: memory string STaB: first vertical memory string
STaU: second vertical memory string

Claims (15)

Memory strings including a first vertical memory string connected between a pipe transistor and a common source line formed in the semiconductor substrate, and a second vertical memory string vertically connected between the pipe transistor and the bit line;
An operating circuit configured to output a program voltage for applying to a selected word line for a program operation of memory cells included in the memory string, a pass voltage for applying to unselected word lines, and a pipe gate voltage for applying to a pipe transistor group; And
And a control circuit configured to control the operation circuit group to disconnect a connection of the first and second vertical memory strings when performing a program operation of the second vertical memory string.
The method of claim 1,
The operation circuit group applies the program voltage to selected memory cells of the second vertical memory string, applies the pass voltage to unselected memory cells of the second vertical memory string, and stores the memory of the first vertical memory string. A semiconductor memory device applying a ground voltage to cells.
The method of claim 1, wherein the memory strings,
First to third memory strings coupled between a first bit line and the common source line; And
And a fourth memory string coupled between a second bit line and the common source line.
The method of claim 3, wherein in the program operation,
A first memory cell for programming in the first memory string is included, the second and third memory strings are deselected, and the fourth memory string includes a fourth memory cell for which the program is prohibited;
In the program operation, the operation circuit group connects the second vertical memory strings of the first memory string to the first bit line, and connects the second and third memory strings to the first bit line. Blocking semiconductor memory device.
The method of claim 3, wherein
And the operation circuit group discharges the first bit line after precharging the first and second bit lines.
The method of claim 5, wherein
The second vertical memory string includes memory cells connected in series and a drain select transistor for connecting the memory cells with the bit line.
The operation circuit group applies the first voltage to the drain select transistor when precharging the first and second bit lines, and the drain select transistor when applying the program voltage and the pass voltage to the memory cells. And applying a second voltage lower than the first voltage.
The method according to claim 6,
And a ground voltage is further applied to the drain select line before the second voltage is applied.
The method according to claim 6,
And a level of a precharge voltage applied to the first and second bit lines when precharging the first and second bit lines is the same as the level of the second voltage.
The method of claim 1,
And the control circuit controls the operation circuit group to allow the pipe transistor to connect the first and second vertical memory strings when performing a program operation of the first vertical memory string.
Providing memory strings including a first vertical memory string connected between a pipe transistor formed on a semiconductor substrate and a common source line, and a second vertical memory string connected vertically between the pipe transistor and the bit line;
Disconnecting the first and second vertical memory strings using the pipe transistor; And
And performing a program operation of a selected memory cell of the second vertical memory string while the connection of the first and second vertical memory strings is disconnected.
The method of claim 10, wherein in the step of performing the program operation,
A program voltage is applied to selected memory cells of the second vertical memory string, a pass voltage is applied to unselected memory cells of the second vertical memory string, and a ground voltage is applied to memory cells of the first vertical memory string. Method of operation of a semiconductor memory device.
The method of claim 10, wherein in the step of providing the memory strings,
First to third memory strings coupled between a first bit line and the common source line; And
And a string including a fourth memory string connected between a second bit line and the common source line.
The method of claim 12, wherein in the program operation,
A first memory cell for programming in the first memory string is included, the second and third memory strings are deselected, and the fourth memory string includes a fourth memory cell for which the program is prohibited;
In the program operation, the second vertical memory strings of the first memory string are connected to the first bit line, and the connection between the second and third memory strings and the first bit line is blocked. Method of operation.
The method of claim 12,
And after the first and second bit lines are precharged, the first bit line is discharged.
11. The method of claim 10,
And performing a program operation of a selected memory cell of the first vertical memory string while the first and second vertical memory strings are connected by the pipe transistor.

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