KR20120068468A - Non-volatile memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device is provided to improve an operation speed by increasing an amount of cell currents. CONSTITUTION: A first selection transistor is connected to a bit line(BL). A second selection transistor is connected to a common source line. A plurality of cell transistors are serially connected between the first selection transistor and the second selection transistor. Each word line of the cell transistor is used as a gate input. The first or second selection transistor is a Schottky barrier MOSFET.

Description

Nonvolatile Memory Device {NON-VOLATILE MEMORY DEVICE}

The present invention relates to semiconductor design techniques, and more particularly to a nonvolatile memory device.

In general, a flash memory device is a nonvolatile memory device that can store data even when power is cut off. The flash memory device can be electrically programmed and erased and refreshed at regular intervals. refresh) A memory device that does not require a function. Here, the program refers to an operation of writing data to a memory cell, and the erasing means an operation of erasing data from the memory cell.

Such a flash memory device may be largely classified into a NOR type flash memory device and a NAND type flash memory device according to the structure and operating conditions of the memory cell. In the NOR flash device, a source of each cell transistor is connected to a ground voltage (VSS) terminal to perform a program and erase operation for an arbitrary address, and is mainly used in an application requiring high speed operation. NAND flash memory devices, on the other hand, include a plurality of string-structured memory cells in which a plurality of cell transistors are connected in series, and are mainly used in highly integrated data storage applications.

1A to 1C show a NAND flash memory device according to the prior art in the following order: top view, circuit diagram, and cross-sectional view.

In the present specification, only one memory cell is described for convenience of description, and description is given with an example in which 16 cell transistors included in the memory cell are provided.

Referring to FIGS. 1A to 1C, a NAND flash memory device may include a memory cell 10 having a string structure and a bit line BL connected to one end of the memory cell 10 through a bit line contact plug BLC. And a common source line CSL connected to the other end of the memory cell 100 via a common source line contact plug CSLC.

Here, the memory cell 10 includes the drain select transistor DST connected to the bit line contact plug BLC, the source select transistor SST connected to the common source line contact plug CSLC, and the drain select transistor DST. ) And first through sixteenth cell transistors CT0 through CT15 connected in series between the source select transistor SST. In the drain select transistor DST, the drain select line DSL is connected to the gate, and the source select transistor SST is connected to the source select line SSL gate, and the first through sixteenth cell transistors CT0 through CT15 are connected. The first to sixteenth word lines WL0 to WL15 are connected to respective gates. In particular, referring to FIG. 1C, the junction regions DA, CA, and SA are formed on the semiconductor substrates SI on both sides of the drain select transistor DST, the first through sixteenth cell transistors CT0 through CT15, and the source select transistor SST. ) Is formed. The junction regions DA, CA, and SA may be formed by doping a high concentration of N-type impurities in the P-well P-WELL disposed on the upper surface of the semiconductor substrate SI. A drain region DA formed at one side, a source region SA formed at one side of the source select transistor SST, and a cell junction region CA formed at both sides of the first to sixteenth cell transistors CT0 to CT15. . In this case, the drain select transistor DST is connected to the bit line contact plug BLC through the drain region DA, and the source select transistor SST is connected to the common source line contact plug CSLC through the source region SA. The first to sixteenth cell transistors CT0 to CT15 are electrically connected to adjacent cell transistors through the cell junction region CA.

On the other hand, as the drain select transistor DST and the source select transistor SST, ordinary MOS transistors (MOSFETs) are used, and the first to sixteenth cell transistors CT0 to CT15 use charge trap transistors. In the following description, only ordinary MOS transistors used in the drain select transistor DST and the source select transistor SST will be described so as not to obscure the gist of the present invention.

FIG. 2 is a cross-sectional view illustrating the drain select transistor DST and the NMOS transistor used in the source select transistor SST shown in FIGS. 1A to 1C.

Referring to FIG. 2, a conventional NMOS transistor is disposed through a silicon substrate (P-Si) doped with a P-type impurity and a gate insulating layer (not shown) on top of the silicon substrate (P-Si). The gate G1 and the source S1 and the drain D1 formed by using ion implantation in a predetermined region corresponding to both ends of the gate G2 on the upper surface of the silicon substrate P-Si. do. At this time, a high concentration of N-type impurities (dopants) are used for the source S1 and the drain D1. Here, the silicon substrate P-Si corresponds to the P-well P_WELL of FIG. 1C, the drain D1 corresponds to the drain region DA formed on one side of the drain select transistor DST, and the source S1. ) Corresponds to the source area SA formed on one side of the source select transistor SST.

However, NAND flash memory devices having such a configuration have limitations in improving area and improving operating speed. Therefore, there is an urgent need for technology development to overcome the limitation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having an improved operation speed while improving its area.

According to one aspect of the invention, the present invention provides a semiconductor device comprising: a first select transistor connected to a bit line; A second select transistor connected to the common source line; And a plurality of cell transistors, each word line serving as a gate input and connected in series between the first and second select transistors, wherein at least one of the first and second select transistors is a Schottky barrier MOS transistor ( Schottky barrier MOSFETs. Here, when the first select transistor is a Schottky barrier MOSFET, the drain of the first select transistor is formed of silicide and its source is formed of a predetermined impurity. In addition, when the second select transistor is a Schottky barrier MOSFET, the source of the second select transistor is formed of silicide and the drain thereof is formed of a predetermined impurity.

According to another aspect of the invention, the present invention is a memory cell of a string structure; And a switching transistor for forming a current path in the memory cell having a string structure, wherein the switching transistor is composed of a Schottky barrier MOSFET.

According to the present invention, a first select transistor connected to a bit line and a second select transistor connected to a common source line are configured as a Schottky barrier MOSFET in a string memory cell, thereby providing a general MOS transistor. Compared to the MOSFET), the size is reduced and the cell current amount is increased. Therefore, the overall yield can be increased due to an increase in the net die of the nonvolatile memory device, and the overall operating characteristics can be improved as the operating speed is improved.

1A to 1C are a plan view, a circuit diagram, and a sectional view of a NAND flash memory device according to the prior art.
Fig. 2 is a cross-sectional view for explaining a conventional NMOS transistor used for the drain select transistor and the source select transistor shown in Figs. 1A to 1C.
3A to 3C are a plan view, a circuit diagram, and a sectional view of a NAND flash memory device according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a Schottky barrier MOSFET used in the drain select transistor and the source select transistor shown in FIGS. 3A to 3C.
5A and 5B are graphs showing characteristic curves of a Schottky barrier MOSFET shown in FIG. 4.
6 is a cross-sectional view for describing operation characteristics of a NAND flash memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

3A through 3C illustrate a NAND type flash memory device according to an embodiment of the present invention in plan view, circuit diagram, and cross-sectional view.

In the embodiment of the present invention, only one memory cell will be described for convenience of description, and description will be given with an example in which 16 cell transistors included in the memory cell are provided. In addition, in the embodiment of the present invention for the convenience of description will be described using the same reference numerals for the same components as the prior art.

Referring to FIGS. 3A to 3C, the NAND flash memory device may include a memory cell 110 having a string structure and a bit line BL connected to one end of the memory cell 110 through a bit line contact plug BLC. And a common source line CSL connected to the other end of the memory cell 100 via a common source line contact plug CSLC.

Here, the memory cell 110 includes a drain select transistor NDST connected to the bit line contact plug BLC, a source select transistor NSST connected to a common source line contact plug CSLC, and a drain select transistor NDST. ) And first through sixteenth cell transistors CT0 through CT15 connected in series between the source select transistor NSST. In the drain select transistor NDST, the drain select line DSL is connected to the gate, and in the source select transistor NSST, the source select line SSL is connected to the gate, and the first to sixteenth cell transistors CT0 to CT15 are connected. The first to sixteenth word lines WL0 to WL15 are connected to respective gates. In particular, referring to FIG. 3C, the semiconductor substrate SI on both sides of the drain select transistor NDST, the first through sixteenth cell transistors CT0 through CT15, and the source select transistor NSST, in particular, the upper portion of the semiconductor substrate SI. Junction regions DA, CA, and SA are disposed in the P-well P-WELL disposed on the surface. In more detail, the drain region NDA formed of silicide is disposed on one side of the drain select transistor NDST, and the source region NSA formed of silicide is formed on one side of the source select transistor NSST. Cell junction regions CA doped with N-type impurities are disposed on both sides of the first to sixteenth cell transistors CT0 to CT15. In this case, the drain select transistor NDST is connected to the bit line contact plug BLC through the drain region NDA, and the source select transistor NSST is connected to the common source line contact plug CSLC through the source region NSA. The first to sixteenth cell transistors CT0 to CT15 are electrically connected to adjacent cell transistors through the cell junction region CA.

On the other hand, the first to sixteenth cell transistors CT0 to CT15 use charge trap transistors, and the drain select transistor NDST and the source select transistor NSST use Schottky barrier MOSFETs. It can be seen that. Hereinafter, Schottky barrier MOSFETs used in the drain select transistor NDST and the source select transistor NSST will be described so as not to obscure the gist of the present invention.

4 is a cross-sectional view illustrating a Schottky barrier MOSFET used in the drain select transistor NDST and the source select transistor NSST shown in FIGS. 3A to 3C. A graph showing a characteristic curve between the drain current Id and the drain voltage Vd of the Schottky barrier MOSFET shown in FIG. 4 is shown, and FIG. 5B shows the Schottky barrier MOS shown in FIG. A graph showing a characteristic curve between the drain current Id and the gate voltage Vg of the transistor Schottky barrier MOSFET is shown.

Referring to FIG. 4, a Schottky barrier MOSFET forms a source S2 and a drain D2 with silicide. As a result, a band barrier is lower than that of a conventional MOSFET (see FIG. 2). In other words, the Schottky barrier MOSFET can significantly lower the parasitic capacitor and the parasitic resistance, thereby improving the amount of cell current delivered through the channel, thereby increasing the operating speed. In addition, the Schottky barrier MOSFET can reduce the junction layer and implement the short channel transistor compared to the conventional MOS transistor (see FIG. 2), thereby gaining in area. Can bring As shown in FIGS. 5A and 5B, the Schottky barrier MOSFET has a characteristic curve similar to that of a conventional MOSFET, and thus may be applied to a NAND flash memory device. To show

Hereinafter, the operation of the NAND flash memory device according to the embodiment of the present invention will be described.

6 is a cross-sectional view for describing an operating characteristic of a NAND flash memory device according to an embodiment of the present invention.

In the embodiment of the present invention, a read operation is described as an example, and the selected word line is described using the second word line WL1 as an example.

Referring to FIG. 6, after completing a program operation on a memory cell 110 having a string structure, a read operation is performed on the memory cell 110. That is, in the state where the bit line BL is precharged to the predetermined voltage Vbl, the read voltage Vread is applied to the second word line WL1, and the remaining word lines except for the second word line WL1 ( A pass voltage Vpass is applied to WL0, WL2 ˜ WL15, and an operating voltage Von of a Schottky barrier MOSFET is applied to the drain select line DSL and the source select line SSL. If the second cell transistor CT1 is not programmed, the second cell transistor CT1 is turned on by the read voltage Vread applied through the second word line WL1. In addition, the drain select transistor DST, the first to sixteenth cell transistors CT0 to CT15, and the source select transistor SST are all turned on, so that the drain region NDA, the cell junction region CA, and the source region are turned on. As the channel is formed between the NSAs, the cell current Icell flows from the bit line BL to the common source line CLS. In this case, as the drain select transistor DST and the source select transistor SST are used as the Schottky barrier MOSFET, the amount of cell current Icell is increased as compared with the conventional MOS transistor (see FIG. 2).

According to the embodiment of the present invention, as the amount of cell current (Icell) is increased, the operation speed is improved to improve the overall operating characteristics, and as the size is reduced compared to the prior art, the net die (net) die is also increased.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

110: memory cell of string structure NDST: drain select transistor
CT0 to CT15: cell transistor NSST: source select transistor
NDA: drain region (silicide) CA: cell junction region
NSA: Source region (silicide) BLC: Bitline contact plug
BL: Bitline CSLC: Common Source Line Contact Plug
CSL: Common Source Line DSL: Drain Select Line
SSL: Source select line WL0 to WL15: Word line
SI: Semiconductor Substrate

Claims (12)

A first select transistor connected to the bit line;
A second select transistor connected to the common source line; And
Each word line is a gate input, and includes a plurality of cell transistors connected in series between the first and second selection transistors.
At least one of the first and second selection transistors is a Schottky barrier MOSFET.
The method of claim 1,
And when the first select transistor is a Schottky barrier MOSFET, the drain of the first select transistor is formed of silicide and its source is formed of a predetermined impurity.
The method according to claim 1 or 2,
And the gate is connected to the drain select line. The method of claim 1,
And the source of the second select transistor is formed of silicide and the drain thereof is formed of a predetermined impurity when the second select transistor is a Schottky barrier MOSFET.
The method according to claim 1 or 4,
And the gate is connected to a source select line of the second select transistor.
The method of claim 1,
When the first and second selection transistors are Schottky barrier MOSFETs, the drain of the first selection transistor is formed of silicide and its source is formed of a predetermined impurity, and the second selection A nonvolatile memory device in which a source of a transistor is formed of silicide and a drain thereof is formed of a predetermined impurity.
The method of claim 6,
The first select transistor has a gate connected to a drain select line,
And the gate is connected to a source select line of the second select transistor.
The method of claim 1,
And the plurality of cell transistors are charge trap transistors.
Memory cells of a string structure; And
A switching transistor for forming a current path in the string cell of the memory structure,
The switching transistor is a Schottky barrier MOSFET.
10. The method of claim 9,
And the switching transistor is disposed on at least one of both ends of the memory cell of the string structure.
10. The method of claim 9,
The switching transistors are disposed at both ends of the memory cell of the string structure,
And a plurality of cell transistors connected in series between the switching transistors respectively disposed at both ends of the memory cell of the switching structure.
The method of claim 11,
And the plurality of cell transistors are charge trap transistors.

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