KR20120060726A - Stacked microelectronic assembly with tsvs formed in stages and carrier above chip - Google Patents

Abstract

PURPOSE: A stacked microelectronic assembly with a stepped TSV(Through-Silicon Via) and a carrier on a chip is provided to improve a process of connecting a front side and a rear side of a semiconductor chip. CONSTITUTION: A microelectronic element(102) includes a front side(104). A plurality of conductive pads(106) are exposed from the front side of the microelectronic element. A first element(110) is electrically connected to the conductive pad. The first element includes a plurality of openings(111) extended to the front of the microelectronic element.

Description

STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP}

The present invention relates to the packaging of microelectronic devices, and more particularly to the packaging of semiconductor devices.

Microelectronic devices are made of thin slabs, commonly referred to as dies or semiconductor chips, composed of semiconductor materials such as silicon or gallium arsenide. Semiconductor chips are generally provided as separate packaged units. In the design of some units, a semiconductor chip is mounted on a substrate or a chip carrier and mounted on a circuit board such as a printed circuit board.

Active circuitry is fabricated on the first side (eg, front side) of the semiconductor chip. Bond pads are provided on the corresponding side of the semiconductor chip to enable electrical connection to the active circuit. The bonding pads are typically arranged in a regular arrangement at the center of the die, such as around the edge of the die or in many memory devices. The bonding pad is generally constituted by a conductive metal such as copper or aluminum having a thickness of approximately 0.5 micron (µm). The bonding pad may comprise a single metal layer or a plurality of metal layers. The size of the bonding pad will vary depending on the type of device, but typically one side will be tens to hundreds of microns.

Through-silicon vias (hereinafter simply referred to as "TSVs") are used to electrically connect the front face on which the bonding pads of the semiconductor chip are disposed and the back face of the semiconductor chip facing away from the front face. Conventional TSV holes can reduce the portion of the first side that can be used to include active circuitry. In this first aspect, the reduction in the effective space available for active circuits can increase the silicon content required to produce the semiconductor chip, which in turn increases the cost of the semiconductor chip.

Size is an important consideration in the physical placement of semiconductor chips. BACKGROUND With the rapid advancement of portable electronic devices, there is an increasing demand for more compact physical placement of semiconductor chips. For example, devices commonly referred to as "smart phones" include global positioning system (GPS) receivers, electronic cameras and the like with powerful data processors, memory, and high resolution displays and associated image processing chips. Auxiliary devices such as local area network access are integrated. Such devices can provide pocket-sized devices with capabilities such as full internet connectivity and entertainment such as full-resolution video, navigation, electronic banking, and the like. Complex handheld devices need to contain numerous chips in a small space. In addition, some chips have many input and output connections, commonly referred to as "I / O". These I / Os must be interconnected with I / O from other chips. Such interconnection requires a short distance and low impedance to minimize signal propagation delay. Components forming the interconnect should not significantly increase the size of the microelectronic assembly. Similar demands exist for other applications such as data servers such as those used in Internet search engines. For example, a structure having an interconnect structure with short distances and low impedance interconnections between composite chips can increase the bandwidth of the search engine and reduce power consumption.

While technological advances have been made in the formation and interconnection of semiconductor vias, further improvements can be made to the process for connecting the front and back sides of the semiconductor chip and to the structures that can result from such a process. .

According to one aspect of the invention, a microelectronic assembly comprises a first element comprising at least one of a semiconductor material or an inorganic dielectric material, attached to the first element, the surface of the first element and A microelectronic element having a major surface facing each other, a plurality of conductive pads exposed on the major surface, and having an active semiconductor element therein, the first element of the first element A first opening extending from an exposed surface toward the surface facing the microelectronic element of the first element and a second opening extending from the first opening to a first conductive pad of the plurality of conductive pads, And a conductive element extending within the first and second openings and contacting at least one conductive pad of the plurality of conductive pads. nductive element). At positions where the first opening and the second opening meet, the interior surface of the first opening and the interior surface of the second opening may extend at different angles with respect to the major surface of the microelectronic element, respectively. have.

According to another aspect of the invention, a microelectronic assembly comprises a first element comprising at least one of a semiconductor material or an inorganic dielectric material, attached to the first element, the surface of the first element A microelectronic element having a major surface facing and having a plurality of conductive pads exposed on said major surface and having an active semiconductor element therein, said first element from an exposed side of said first element A first opening extending toward a surface facing the microelectronic element of and a second opening extending from the first opening through a first conductive pad of the plurality of conductive pads, and the first and second A conductive element extending within the opening and in contact with at least one of the plurality of conductive pads. At positions where the first opening and the second opening meet, the interior surface of the first opening and the interior surface of the second opening may extend at different angles with respect to the major surface of the microelectronic element, respectively. have.

In an embodiment of the invention, the conductive element may coincide with the contour of the inner side of at least one of the first opening and the second opening. In an embodiment of the invention, the conductive element may have a shape different from the contour of the inner side of at least one of the first opening and the second opening. In an embodiment of the invention, the conductive element may have one or more shapes of cylindrical or frusto-conical. In an embodiment of the present invention, the first element may be a carrier having no active semiconductor device therein. In an embodiment of the invention, the first element may further comprise one or more passive circuits therein. In an embodiment of the invention, the one or more passive circuits may include one or more selected from the group comprising inductors, resistors, or capacitors. In an embodiment of the invention, the carrier may mechanically support the microelectronic element.

In an embodiment of the present invention, the first element may have a first thickness, and the microelectronic element may have a second thickness that is less than or equal to the first thickness. In an embodiment of the invention, the major surface of the microelectronic element can be the front face. In an embodiment of the invention, the microelectronic element may comprise a back side facing away from the front side and may have an opening extending from the back side and exposing at least a portion of the one or more conductive pads. A second conductive element extends within the opening of the microelectronic element and can be electrically connected with the conductive pad. In an embodiment of the invention, the microelectronic element includes a plurality of openings and may include a plurality of second conductive elements extending within the second opening and electrically connected to the conductive pads. In an embodiment of the invention, the second conductive element may be electrically connected to the plurality of conductive pads, respectively.

According to yet another aspect of the invention, a microelectronic assembly comprises a first element comprising at least one of a semiconductor material or an inorganic dielectric material, attached to the first element, the surface of the first element A microstructure having a main surface facing the surface, the plurality of conductive pads having an exposed top surface and a bottom surface facing away from the top surface, the active surface having an active semiconductor element therein; An electronic element, a first conductive element extending within the first opening of the first element and in contact with a top surface of at least one conductive pad of the conductive pad, and extending through the second opening of the microelectronic element; It may include a second conductive element in contact with one or more conductive pads of the pad. The first conductive element and the second conductive element may be exposed on opposite facing sides of the microelectronic assembly for electrical conductive interconnection with one or more components external to the microelectronic assembly.

In an embodiment of the present invention, the inner surface of the first opening and the inner surface of the second opening may extend at different first and second angles, respectively, in directions away from the top and bottom surfaces of the one or more conductive pads, respectively. have. In an embodiment of the invention, the microelectronic element comprises a plurality of second openings, the microelectronic assembly extending within the second opening and electrically connected with the conductive pad and extending within the first opening. It may further comprise a plurality of second conductive elements in electrical connection with the first conductive element. In an embodiment of the invention, the first element may further comprise one or more passive circuits therein. In an embodiment of the invention, the opening of the first element comprises a third opening extending from the back surface of the first element toward the front surface and at least a portion of the top surface of the one or more conductive pads extending from the third opening. And a fourth opening that exposes the first conductive element, wherein the first conductive element extends at least within the third opening and through the fourth opening to contact the top surface of the one or more conductive pads.

In an embodiment of the invention, the conductive element may have a shape different from the contour of the inner side of at least one of the first opening and the second opening. In an embodiment of the invention, the conductive element may have one or more shapes of cylindrical or frusto-conical. In an embodiment of the invention, the conductive element has a configuration in which the width is uniformly reduced from a first width near the exposed face of the first element to a second width near the conductive pad of the microelectronic element. Can be. In an embodiment of the invention, the conductive element may coincide with the contour of the inner side of at least one of the first opening and the second opening. In an embodiment of the invention, the portion of the conductive element in the second opening may coincide with the contour of the inner side of the second opening. In an embodiment of the invention, the portion of the conductive element extending within the first opening and the second opening may have one or more shapes of cylindrical or truncated cone.

In an embodiment of the invention, the first portion of the conductive element is uniformly widthd from a first width near the exposed face of the first element to a second width at a first position in the second opening. Reduced, the second portion of the conductive element may have a configuration in which the width is uniformly reduced from a third width near the back side of the microelectronic element to a fourth width at the first location. In an embodiment of the invention, the second opening of the microelectronic element extends through the conductive pad from the backside of the microelectronic element, the second conductive element extends through the conductive pad, and within the first opening. It may be electrically connected to the first conductive element in position. In an embodiment of the invention, the first conductive element can coincide with the contour of the second opening in the microelectronic element. In an embodiment of the invention, the first conductive element may have a different shape than the contour of the second opening in the microelectronic element.

Another aspect of the invention provides a system using a microelectronic structure according to the above-described features of the invention and one or more other electronic components electrically connected to such a structure. For example, the system may include a housing, and the electronic component and the structure may be installed in the housing. The system according to the preferred embodiment in this aspect of the invention can be further miniaturized than the conventional system.

According to another aspect of the present invention, a method of forming a microelectronic assembly includes (a) an attachment for attaching a first element comprising at least one of a semiconductor material or an inorganic dielectric material to the microelectronic assembly. As a step, a first side of the first element is attached to face the major surface of the microelectronic element, and the microelectronic element is adjacent to the major surface and at least one electrically conductive pad having a top surface exposed to the major surface. An attachment step comprising an active semiconductor element; (b) forming a first conductive element extending through the first element and in contact with a top surface of the one or more conductive pads; And (c) a second extending through the microelectronic element before or after performing step (b) and in contact with the major surface with at least one conductive pad of the first conductive pad or the second conductive pad; Forming a conductive element.

In an embodiment of the invention, the first conductive element and the second conductive element may be exposed on surfaces facing in opposite directions of the microelectronic assembly. In an embodiment of the invention, the microelectronic element may comprise a plurality of chips attached to each other in a dicing lane. The method may further comprise separating the microelectronic assembly into units each comprising one or more chips of the plurality of chips along the dicing lane. In an embodiment of the present invention, the first element may be a carrier having no active semiconductor element therein. In an embodiment of the present invention, the first element may further include one or more passive elements therein.

In an embodiment of the invention, the carrier may mechanically support the microelectronic element. In an embodiment of the present invention, the forming of the first conductive element comprises, after performing the attaching step, forming an opening extending through the thickness of the first element and in the opening of the first element, And depositing a metal layer in contact with the top surface of the one or more conductive pads exposed in the opening. In an embodiment of the present invention, forming the second conductive element comprises depositing a second metal layer in the second opening, the second metal layer contacting a bottom surface of at least one conductive pad exposed in the opening of the microelectronic element. It may include.

According to another aspect of the invention, a method of forming a microelectronic assembly includes the steps of: (a) attaching a first element comprising at least one of a semiconductor material or an inorganic dielectric material to the microelectronic assembly; A first surface of the first element facing the major surface of the microelectronic element, the microelectronic element being adjacent to the major surface and a plurality of electrically conductive pads having an upper surface exposed to the major surface. An attachment step having an active semiconductor element; (b) forming a first conductive element extending through the first element and in contact with a top surface of the one or more conductive pads; And (c) before or after performing step (b), reducing the width of the microelectronic element from the backside of the microelectronic element or openings extending from the backside of the microelectronic element in the microelectronic element. It may include performing one or more steps of forming a. A second conductive element in the microelectronic element can be exposed on the backside.

In an embodiment of the present invention, step (c) may comprise reducing the width of the microelectronic element. In an embodiment of the present invention, step (c) may comprise forming an opening extending from the back side of the microelectronic element and exposing the second conductive element. In an embodiment of the invention, said step (c) forms an opening extending from the reduced back side of said microelectronic element and exposing said second conductive element after performing the step of reducing the width of said microelectronic element. It may include the step. In an embodiment of the invention, forming the first opening comprises: forming an opening in the first element extending toward the major surface from the first face of the first element; Forming an additional opening extending from the opening and at least partially exposing the at least one conductive pad, wherein the inner face of the opening and the inner face of the further opening may be arranged to intersect with each other at an angle.

In an embodiment of the invention, the microelectronic element may be guided by a first microelectronic element. The method includes attaching a major surface of the second microelectronic element to the back side of the first microelectronic element, a third extending through the second microelectronic element and at least partially exposing the second conductive element. Forming an opening and forming a third conductive element in contact with the second conductive element in the third opening. In an embodiment of the invention, the first conductive element and the third conductive element may be exposed on surfaces facing in opposite directions of the microelectronic assembly.

According to another aspect of the invention, a method of forming a microelectronic assembly includes an agent extending from a first side of a first element through at least a portion of the first element toward a second side remote from the first surface. Forming a first conductive element in at least a portion of the first surface, the first conductive element having at least a portion exposed thereon, and attaching the first element to a microelectronic element having an active semiconductor element therein, the first element Attaching a first side of the substrate to face the major surface of the microelectronic element, wherein the first conductive element is at least partially positioned over the one or more second conductive elements exposed to the major surface of the microelectronic element Extend through the opening in the microelectronic element and through the one or more second conductive elements, and contact the first conductive element. Forming a third conductive element, and after the attaching step, processing to provide a contact exposed to the second side of the first element and in electrical contact with the third conductive element. can do.

In an embodiment of the present invention, the first conductive element is formed to extend only partially through the first element, and the forming of the contact may include a portion of the first conductive element exposed surface of the first element. Reducing the width of the first element from the exposed side of the first element until exposed to the contact, wherein the contact can be aligned with an opening in the first element. In an embodiment of the invention, the step of providing the contact comprises a portion of the first conductive element protruding a desired distance over the exposed face, the post for electrical interconnection with an external component of the microelectronic assembly. And removing material of the first element from the exposed side until exposed.

In an embodiment of the invention, the method further comprises forming at least one additional opening in the first element extending from the second face to the opening of the first element, wherein forming the contact comprises: Forming a via extending through said additional opening and electrically connected with said first conductive element. In an embodiment of the invention, a portion of the first conductive element extends along a major surface of the first element, and the one or more conductive pads are positioned over a portion of the first conductive element extending along the major surface and The second conductive element may be bonded to a portion of the first conductive element. In an embodiment of the present invention, forming the first conductive element may include simultaneously forming a fourth conductive element with the first conductive element in at least an opening of the first element. Forming the third conductive element includes forming a fifth conductive element in contact with the fourth conductive element through the opening of the microelectronic element and through a second conductive pad of the plurality of conductive pads. can do.

According to another aspect of the present invention, a method of forming a microelectronic assembly includes (a) (i) an opening extending from a first face toward a second face away from the first face at least partially through the first element. A metallic redistribution layer (RDL) formed therein, the first conductive element having a portion exposed to the front, and (ii) extending along one surface of the first element and extending in a direction away from the first conductive element. (B) attaching the first element to a microelectronic element having an active semiconductor element therein, wherein the first side of the first element is formed of the microelectronic element. An attachment step facing the major surface, wherein the RDL is juxtaposed with at least one conductive pad of the plurality of conductive pads exposed to the major surface of the microelectronic element, (c) the e Through the opening of the croissant electronic element and extending through said at least one conductive pad, and forming a second conductive element contacting the RDL; And (d) after performing the attaching step, forming a contact that is exposed to the second side of the first element and is in electrical connection with the first conductive element.

1 is a cross-sectional view showing a microelectronic package according to an embodiment of the present invention attached to a circuit board.
1A is a partial cross-sectional view of the microelectronic package shown in FIG. 1.
FIG. 2 is a partial cross-sectional view illustrating a microelectronic assembly with the microelectronic package of FIG. 1.
3 is a partial cross-sectional view of a microelectronic assembly according to a modification of the embodiment shown in FIG. 1.
3A is a cross-sectional view of a microelectronic package according to a modification of the embodiment shown in FIG. 1.
4 is a partial cross-sectional view of a microelectronic assembly according to a modification of the embodiment shown in FIG. 3.
FIG. 5 is a partial cross-sectional view of a microelectronic assembly according to a modification of the embodiment shown in FIG. 3.
6-16 are partial cross-sectional views illustrating steps of a method of manufacturing a microelectronic assembly according to an embodiment of the present invention.
17 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment of the present invention shown in FIG.
18 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment of the present invention shown in FIG. 17.
19 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment of the present invention shown in FIG. 17.
20 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment of the present invention shown in FIG. 19.
21 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment of the present invention shown in FIG.
22-32 are partial cross-sectional views illustrating respective steps of the method of manufacturing the microelectronic assembly shown in FIG. 21, in accordance with an embodiment of the invention.
33 to 35 are partial cross-sectional views showing steps of a method for manufacturing a microelectronic assembly according to a modification of the embodiment shown in FIG. 21.
36 and 37 are partial cross-sectional views illustrating respective steps in the method of manufacturing the microelectronic assembly according to the modification of the embodiment shown in FIG. 21.
FIG. 38 is a cross-sectional view illustrating a microelectronic package bonded to a circuit board on a circuit board in a variation of the embodiment shown in FIG. 3A.
FIG. 39 is a cross-sectional view illustrating a microelectronic assembly in accordance with a modification of the embodiment shown in FIG. 21.
40 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 39.
FIG. 41 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 21.
FIG. 42 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 41.
FIG. 43 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 42.
FIG. 44 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 43.
FIG. 45 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 2.
46 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIGS. 45 and 3.
FIG. 47 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 46.
48 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 47.
FIG. 49 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 48.
50 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 49.
FIG. 51 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 18.
52 and 53 are partial cross-sectional views showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 46.
54-62 are partial cross-sectional views illustrating each step in the method of manufacturing the microelectronic assembly shown in FIG. 45, in accordance with an embodiment of the present invention.
FIG. 63 is a partial cross-sectional view showing a microelectronic assembly according to a modification of the embodiment shown in FIG. 62.
64 is a schematic diagram of a system according to an embodiment of the present invention.

1 illustrates a microelectronic package 100 according to an embodiment of the present invention. The microelectronic package includes an integrated circuit embedded in a microelectronic element 102, for example a semiconductor chip, which may be a silicon, silicon alloy, or group III-V semiconductor material or II-VI. Other semiconductor materials, such as group semiconductor materials. 1A, which is a detailed enlarged view, microelectronic element 102 includes a front suface 104, referred to as a contact-bearing face, which is the main surface of the microelectronic element ( major surface, and a dielectric layer 105 of the microelectronic element is exposed on this front surface. The dielectric layer 105 is positioned over the semiconductor region 107 where transistors, diodes or other active elements of the microelectronic element are disposed. Referring to FIG. 1, a plurality of conductive pads 106 are exposed on the front face 104.

In one example, dielectric layer 105 has a low dielectric constant k, i.e. a low-k dielectric layer, between and around metal wiring patterns that provide electrical interconnection for microelectronic elements. It may include one or more dielectric materials having a. Low dielectric dielectric materials include porous silicon dioxide, carbon-doped silicon dioxide, polymeric dielectrics, and porous polymeric dielectrics. In a porous low dielectric dielectric layer, the dielectric layer may have a substantial porosity that reduces the dielectric constant of the dielectric material as compared to a nonporous layer of the same material. The dielectric material typically has a dielectric constant significantly greater than 1.0, but the air occupying free space in the porous dielectric material has a dielectric constant of approximately 1.0. This allows some dielectric materials to have a substantial porosity, thereby reducing the dielectric constant.

However, some low dielectric dielectric materials, such as polymeric dielectric materials and porous dielectric materials, are much less resistant to mechanical stress than conventional dielectric materials. In examining certain operating environments and microelectronic elements, stress may be present at or near the limits that the low-k dielectric material can withstand. The microelectronic assembly according to the present invention can improve the protective function of the microelectronic element to the low dielectric dielectric layer by moving the position where the stress is applied to the microelectronic element away from the low dielectric dielectric layer 105. According to this configuration, the stress applied to the low dielectric dielectric layer in manufacturing, operation, and inspection can be much reduced, thereby protecting the low dielectric dielectric layer. As can be seen from FIG. 1, the surface 103 of the first element 110 is attached to the front face 104 by a dielectric material, such as an adhesive. Other adhesive materials may be glass, for example doped and glass having a glass transition temperature of 500 ° C. or less. The first element may be made of a semiconductor material, an inorganic dielectric material, or a material having a coefficient of thermal expansion ("CTE") of 10 parts per million (CPM) or less than 10 ppm / ° C. Typically, the first element 110 is made of the same semiconductor material as the microelectronic element, or of a dielectric material having a CTE of or near the microelectronic element. In this case, the first element may be said to have a thermal expansion coefficient matched with the microelectronic element ("CTE-matched"). As shown in FIG. 1, the first element 110 may include a plurality of “staged vias” for electrically connecting with the conductive pads 106 of the microelectronic element. For example, the first element may have a plurality of first openings 111 extending toward the front face 104 of the microelectronic element from the face 118 exposed outward. There may be a plurality of second openings 113 extending from the first openings 111 towards the conductive pads 106 of the microelectronic element. 1A, at a location where the first opening and the second opening meet, the inner faces 121, 123 of the first opening and the second opening are at different angles 140, 142 with respect to the plane defined by the main surface. Extending, ie equal to the angles 140, 142 relative to any plane 125 parallel to the major surface.

The plurality of conductive elements 114 extend in the first and second openings and are electrically connected to the conductive pads 106. This conductive element 114 is exposed to the exposed face 118 toward the outward direction of the first element. In one example, the conductive element 114 can include a metal member formed by depositing a metal to contact an exposed face of the conductive pad 106. As described in detail below, various metal deposition steps may be used to form conductive elements. The first element may comprise one or more passive circuit elements, such as capacitors, resistors, inductors, or a combination thereof, although not specifically shown in FIG. 1, the microelectronic element and package 100. Can contribute to the function.

As further provided by the package 100, the first element may function as a carrier for mechanically supporting the microelectronic element. Typically, the thickness 112 of the microelectronic element is less than or equal to the thickness 116 of the first element. When the CTE of the first element and the microelectronic element is matched and the first element is attached to the front side of the microelectronic element, the microelectronic element can be made relatively thin compared to the first element. For example, if the first element has a CTE that matches the microelectronic element, the thickness 112 of the microelectronic element can be several microns, which means that the stress applied to the conductive element 114 is not applied to the conductive pad 106. This is because it spreads widely over the size and thickness 116 of the first element, rather than being applied directly). For example, in certain embodiments, the thickness 120 of the semiconductor region 107 of the microelectronic element may be less than 1 micron to several microns. The microelectronic element, the first element attached to the microelectronic element, and the conductive element 114 are installed together in a microelectronic assembly 122 that can be mounted and interconnected in a microelectronic package.

As shown in FIG. 1, the conductive element 114 is formed of a member 128 of a bonding metal, such as solder, tin, indium, or a combination thereof, similar to a flip-chip method. Can be conductively attached to the contact 124 of the dielectric element 126. Accordingly, the dielectric element uses a conductive member 132, such as a solder ball, which projects in a direction away from the dielectric element 126, so that the package 100 contacts the corresponding contact of the circuit board 134. A plurality of terminals 130 may be provided for electrically connecting to 136.

2 is a partial cross-sectional view illustrating a structure of the microelectronic assembly 122. If the first element is composed of a semiconductor material, the dielectric layer 138 may be provided as a coating that conforms to the contour of the inner surfaces 121, 123 of the first opening 111 and the second opening 113. In one example, when the first element is made of semiconductor material, the dielectric layer 138 conforming to the contour of this inner side is electrophoresed on the inner side of the openings 111 and 113 and the exposed side 148 of the first element. It may be selectively formed by electrophoretic deposition. This will be described in more detail later. The conductive layer 114A may then be formed in the opening, for example, by depositing a metal or conductive metal compound in contact with the conductive pad 106 and the dielectric layer 138. After forming the conductive layer, the remaining portion in the opening 111 may be filled with dielectric material 150. Subsequently, the conductive contact 114B may be formed on the dielectric material 150 by depositing a conductive material such as a metal on the dielectric material 150.

3 shows a modification of the embodiment shown in FIG. 2. In this variant, the second conductive element 154 is electrically connected to the conductive pad 106 and exposed to the major surface of the microelectronic element. The major surface of this microelectronic element is the backside 152 of the microelectronic element away from the front face 104. The opening 153 may extend from the backside 152 of the microelectronic element and may be exposed to at least a portion of the conductive pad 106. The dielectric layer 158 may form a film of the opening 153 in the microelectronic element and may electrically insulate the second conductive element 154 from the semiconductor region 107 of the microelectronic element. In the example shown in FIG. 3, the dielectric layer 158 may coincide with the contour of the inner side 159 of the semiconductor region exposed in the opening 153. In addition, like the conductive element 114, the second conductive element may include a conductive layer 154A that extends along the dielectric layer 158, the conductive layer having an inner side 159 of the semiconductor region within the opening 153. Can match the configuration of As specifically shown in FIG. 3, similar to the conductive element 114 described above (FIG. 2), the dielectric layer 160 may be deposited over the conductive layer 154A and the outer conductive contact 154B over the dielectric material. This may be provided. As shown in FIG. 3, the second conductive contact 154B is disposed over at least a portion of the conductive pad 106 and is electrically connected directly or indirectly. As shown in FIG. 3, the inner surfaces 123, 159 of the package layer and the openings of the wafer have contours that match the contours of the dielectric layers 138, 158 and the conductive layers 114A, 154A. Inner surfaces 123 and 159 may extend at substantially different angles 162 and 163, respectively, in the direction away from the front surface of the wafer, i. As a result, the widths 190 and 192 of the openings 113 and 153 where the conductive layers 114A and 154A meet the conductive pads may be substantially smaller than the widths 191 and 193 of the openings 113 and 153. As a result, the conductive pad 106 can be made as small as a substantial distance in the respective directions 181 and 183. In one example, the openings 113, 153 may have the smallest widths 190, 192 at portions that meet each surface of the conductive pad 106.

As can be better understood, the second conductive element 154B is exposed to the surface of the wafer 200 and is used to form an electrically conductive interconnect between the microelectronic assembly (FIG. 3) and the external components of the microelectronic assembly. Can be used for For example, as shown in FIG. 3A, some conductive pads 106A of the microelectronic element 102 of the microelectronic assembly have a conductive element 154 exposed on the backside of the microelectronic element and a bonding metal such as solder. 155 may be electrically interconnected with a conductive member 194, such as a conductive pad disposed over the second dielectric element 196. Dielectric element 196 may further include other members, such as conductive traces 198, which may be electrically connected with the conductive pads. As shown in FIG. 3A, a conductive pad 106B may be provided among the conductive pads that does not include the conductive element 154 connected to the conductive pad and exposed on the backside of the microelectronic element 102.

4 shows a variant in which the second conductive element 164 is provided as a solid conductive structure. In this case, the second conductive element 164 may at least substantially fill the remaining portion after forming the dielectric layer 158 in the space of the opening of the microelectronic element that matches the contour of the inner face. As shown in FIG. 4, the conductive contact or pad portion 164B of the second conductive element may extend beyond the opening 153 along the backside 152 of the microelectronic element.

5 shows another variation in which the second conductive element includes a conductive layer 166 extending along the dielectric layer 158. As in the embodiments described above, the dielectric layer 158 and the conductive layer 166 may coincide with the contours of the inner side 159 of the opening. As shown in FIG. 5, a conductive member 168, which may be a bonding metal such as solder, tin, indium, or a combination thereof, may be connected to the conductive layer. Conductive member 168 may at least substantially fill the opening and may protrude beyond the backside 152 of the microelectronic element, as shown in FIG. 5.

With reference to FIG. 6, a method of manufacturing a microelectronic assembly according to any of the embodiments described above is described. As shown in FIG. 6, the semiconductor wafer 200 or a portion of the wafer may include a plurality of microelectronic elements 102 connected to each other in a dicing lane 201. The microelectronic element typically has a plurality of conductive pads 106 each exposed on the front face 104. As shown in FIG. 7, the first element 110, such as an unpatterned semiconductor wafer, a glass wafer, or another element having a CTE less than 10 ppm / ° C., may be used as an adhesive 108 or a temperature below 500 ° C. It is adhered to the front face 104 using a dielectric adhesive material such as doped glass having a relatively low melting temperature. This first element 110 generally has a CTE that is equal to or close to the CTE of the semiconductor wafer 200. For example, when the semiconductor wafer 200 is made of silicon, the first element 110 may be made of silicon to CTE match with the wafer 200. Alternatively, the first element 110 of doped glass may be CTE matched with the semiconductor wafer 200. In one example, when the first element 110 is CTE matched with the wafer 200, the dielectric adhesive material may be CTE matched with the wafer 200.

After bonding the first element 110 to the wafer 200, the thickness of the first element 110 can be reduced to a thickness 116 as shown in FIG. 8. The first element 110 can be reduced in thickness by grinding, lapping, polishing, or a combination thereof. In one example, the reduced thickness 116 achieved during this process may be the final thickness of the first element 110.

The steps of a method of manufacturing a microelectronic assembly according to an embodiment of the present invention are then described using a series of partial cross-sectional views. These steps are typically performed at the wafer level, ie before cutting the semiconductor wafer (see FIG. 6) into individual microelectronic elements 102. However, only a part of each microelectronic element is shown in the drawings. The description of the method of manufacturing the microelectronic assembly below, regardless of what is specifically described, and also whether the process referred to in the description below is for a wafer or a microelectronic element (semiconductor chip), chip level or wafer level It is to be understood that this applies to all manufacturing techniques.

9 shows a manufacturing step following the step shown in FIG. 8. As shown in FIG. 9, an opening 170 is formed that extends from the outer surface 148 of the first element 110 to the surface 108A of the dielectric adhesive layer 108 disposed over the conductive pad 106. The opening 170 is formed in a stepped manner, in which the first opening 111 extends from the exposed surface 148 of the first element 110 toward the front surface 104 of the microelectronic element and the second opening 113. ) Extends from the first opening toward the front face 104 of the microelectronic element. As an example, the process of forming the first and second openings 111 and 113 will first be described as follows: first, "sand blasting" (sand blasting) to inject a stream of etching, laser ablation, or fine abrasive particles towards the package layer. first opening can be formed by, for example, blasting). Subsequently, the treatment process may include forming a dielectric layer (not shown) to cover the inner surface of the first opening 111, forming a hole in the dielectric layer, and exposing the surface of the adhesive layer 108. And forming a second opening 113 by etching the package layer through the hole until the second opening 113 is formed. In the case of etching the first element 110 to form the second opening, the dielectric layer of the first opening acts as a mask, and the portion of the package layer exposed in the hole of the dielectric layer is etched. This dielectric layer prevents portions away from the holes in the package layer from being etched. Subsequently, as shown in FIG. 10, a portion of the adhesive layer 108 disposed over the conductive pad 106 and exposed in the second opening 113 is removed to move outward from the microelectronic element 102 of the conductive pad. At least a portion of the upper surface 172 facing toward is exposed.

For processes for forming the first and second openings, all of U.S. Patent Publication No. 20080246136A1, U.S. Application 12 / 842,717, 12 / 842,612, 12 / 842,669, 12 / 842,692, 12 / 842,587, filed July 23, 2010 or Some of which are outlined and are hereby incorporated by reference in their entirety. However, the first and second openings extend through the package layer and the adhesive layer rather than the microelectronic element, and the second opening exposes a portion of the upper surface facing outward of the conductive pad, not the lower pad surface. Is not disclosed.

As shown in FIG. 11, a dielectric layer 138 is formed that extends along the inner surfaces 121, 123 of the first and second openings. This dielectric layer is disposed on the outward facing surface 148 of the first element 110. In one example, electrophoretic deposition techniques are used to form the dielectric coating 138 to coincide with the face 148 of the package layer and the inner faces 121, 123 of the opening. In such a configuration, such dielectric coating may be deposited only on the exposed conductive and semiconductive surfaces of the assembly. During the deposition process, the semiconductor device wafer is maintained at a desired electrical potential and the electrode is immersed in a bath to maintain the bath at another desired potential. The assembly includes an outwardly facing surface 148 and an inner surface 121 of the first opening 111 as well as an inner surface 123 of the second opening 113 to expose the conductive or semiconductive device wafer. On one side, it is maintained in the bath under appropriate conditions for a time sufficient to form an electrodeposited conformal dielectric layer 138. Electrophoretic deposition occurs while a sufficiently strong electric field is maintained between the surface to be coated and the bath. Electrophoretic deposition coating is self-limiting in that such coating is performed until it reaches a predetermined thickness, which is governed by parameters such as voltage and concentration of the deposition and deposition stops.

Electrophoretic deposition forms a continuous, uniform thickness of a conformal coating on the conductive and / or semiconducting outer surface of the assembly. In addition, when forming such an electrophoretic deposition coating, on the surface 108A of the dielectric adhesive layer 108 positioned on the top surface 172 of the conductive pad 106, due to its dielectric properties (non-conductive), such electrophoresis is performed. You may vapor-deposit so that a electrophoretic vapor deposition coating may not be formed. In other words, the property of electrophoretic deposition is that when a layer of dielectric material has a sufficient thickness and dielectric properties, it does not form on the layer of dielectric material over the conductor. Typically, electrophoretic deposition will not occur on dielectric layers having thicknesses above approximately 10 microns to several tens of microns. The conformal dielectric layer 138 may be formed of a cathodic epoxy deposition precursor. Alternatively, polyurethane or acrylic deposition precursors may be used. Various electrophoretic deposition coating precursor compositions and sources are shown in Table 1 below.

Electrodeposition coating name POWERCRON  645 POWERCRON  648 CATHOGUARD  325 Manufacturer MFG PPG PPG BASF type Cathodic cathode cathode Polymer Epoxy Epoxy Epoxy Material Pennsylvania Pittsburgh Pennsylvania Pittsburgh Michigan Southfield Application data Pb / Pf-free Pb-free Pb or Pf-free Pb-free HAPs, q / L 60-84 Compliant VOC, q / L (minus wafer) 60-84 <95 Cure 20 minutes at 175 degrees 20 minutes at 175 degrees Membrane properties color Black color Black color Black color Thickness, μm 10-35 10-38 13-36 Pencil hardness 2H + 4H Bath feature Solid,% wt. 20 (18-22) 20 (19-21) 17.0-21.0 pH (25C) 5.9 (5.8-6.2) 5.8 (5.6-5.9) 5.4-6.0 Conductivity (25C) ㎲ 1000-1500 1200-1500 1000-1700 P / B rate 0.12-0.14 0.12-0.16 0.15-0.20 Working temperature, C 30-34 34 29-35 Hours, seconds 120-180 60-180 120+ Anode SS316 SS316 SS316 volt 200-400 > 100 Electrodeposition coating name ELECTROLAC LECTRASEAL DV494 LECTROBASE  101 Manufacturer MFG MACDERMID LVH COATINGS LVH COATINGS type cathode anode cathode Polymer Polyurethane urethane urethane Material Connecticut Waterberry UK Birmingham UK Birmingham Application data Pb / Pf-free Pb-free Pb-free HAPs, q / L VOC, q / L (minus wafer) Hardening 20 minutes at 149C 20 minutes at 175C 20 minutes at 175C Membrane properties color Clear (dyed) Black color Black color Thickness, μm 10-35 10-35 Pencil hardness 4H Bath features Solid,% wt. 7.0 (6.5-8.0) 10-12 9-11 pH (25C) 5.5-5.9 7-9 4.3 Conductivity (25C) ㎲ 450-600 500-800 400-800 P / B rate Working temperature, C 27-32 23-28 23-28 Hours, seconds 60-120 Anode SS316 316SS 316SS volt 40, max 50-150

As another example, the dielectric layer can be formed electrolytically. This process is similar to the electrophoretic deposition process, except that the thickness of the deposited layer is not limited to values close to the conductive or semiconducting surface to be formed. According to this, an electrolytically deposited dielectric layer can be formed with a thickness selected according to the requirements, and processing time is one factor of the thickness achieved.

The dielectric layer 138 formed in this manner may coincide with the contours of the inner faces 121, 123 of the first and second openings.

After forming the dielectric layer 138, a conductive layer 114A (see FIG. 11) may be formed in the openings 111 and 113, which, when formed on top of the conformal dielectric layer 138, may form a first layer. And the contours of the inner faces 121, 1123 of the second opening. An additional dielectric material 150 is deposited to form the dielectric layer, and the formation of the metal layer 114B over the dielectric layer completes the formation of the conductive element 114 exposed on the outward facing surface of the package layer. This conductive element extends in the first and second openings 111, 113 and is electrically connected to the conductive pad 106. These multiple conductive elements 114 may be formed simultaneously in each opening of the package layer, and the conductive elements are electrically connected to each conductive pad 106 of the wafer 200.

Then, as shown in FIG. 12, the temporary carrier 180 or handle wafer may be attached to the exposed side of the first element 110 positioned over the exposed contact 114B of the conductive element 114. Can be. The carrier 180 can be attached using, for example, an adhesive 182 that can be removed after the subsequent process described below.

As shown in FIG. 13, the thickness of the wafer 200 can be reduced to such an extent that it can be the final thickness 112 of the wafer. To reduce the thickness of the wafer, grinding, lapping, or polishing processes may be used. In one example, the reduced thickness may range from 0.5 micron to several microns. In one embodiment, the final thickness 112 of the wafer 200 is buried in the wafer 200, adjacent to the front side and separating the top 186 of the wafer having the thickness 112 from the bottom 188 in the opposite direction. Can be controlled by the presence of the dielectric layer 184 (see FIG. 12). In one example, buried dielectric layer 184 is a buried oxide layer provided in a semiconductor-on-insulator (SOI) or silicon-on-insulator (silicon on insulator) wafer structure prior to fabricating the active semiconductor device of wafer 200. Can be. In this case, the wafer bottom 188 may be a monocrystalline or polycrystalline semiconductor material. Subsequently, after reaching the manufacturing step shown in FIG. 13, the carrier 180 and the adhesive 182 are removed, resulting in the microelectronic assembly 122 shown in FIG. 2.

Alternatively, the step of fabricating the microelectronic assembly including the second conductive element 154 as shown in FIG. 3 may be performed without separating the carrier from the first element 110. Specifically, as shown in FIG. 14, an opening 153 extending in the thickness direction of the semiconductor region of the wafer 200 can be formed. As shown in FIG. 14, this opening may be formed in a selective manner with respect to the dielectric layer 105 of the wafer. The dielectric layer 105 may include a plurality of interlevel dielectric (ILD) layers provided with metal wires, which may be provided with metal wires or one or more passivation layers over the ILD layer. ) May be located, both the installation of the metal wire and the placement of the passivation layer. Thus, opening 153 does not extend through dielectric layer 105 and exposes a portion of dielectric layer 105.

Next, as shown in FIG. 15, opening 153 extends through dielectric layer 105 to expose at least a portion of bottom surface 174 of conductive pad 106. The lower surface 174 is directed opposite to the upper surface 172 of the conductive pad on which the first conductive element 114 extends, as shown in FIG. 15. Then, as shown in FIG. 16, to form a second conductive element 154 electrically connected to the conductive pad 106 and generally electrically insulated from the wafer 200 by the dielectric layer 158. A conformal conductive layer can be formed of the dielectric layer 158 and typically made of a metal or conductive metal compound. Subsequent processing may include forming the dielectric layer 160 on the conductive layer 154A, and the conductive contact 154B, which is generally made of a metal or a conductive metal compound, may be formed on the dielectric layer 160. have.

Thereafter, when the carrier and the adhesive layer 182 are separated, a microelectronic assembly as shown in FIG. 3 is obtained.

As a variation of the embodiment described above, as shown in FIG. 16, a conformal conductive layer 154A is formed over the dielectric layer 158, and an additional dielectric layer 160 is formed over the conductive layer in the opening of the wafer 200. Instead, without the additional dielectric layer 160 separating the contact from the conductive pad, the second conductive element 164 (FIG. 1) to provide a conductive contact exposed to the backside 152 of the wafer and extending to the conductive pad 106. 4) may be formed.

FIG. 17 is a variation of the embodiment shown in FIG. 16, in which a second opening 213 in the first element 110 exposes the first and second conductive pads 206. As shown in FIG. 17, a plurality of conductive elements 214 can be formed that extend from the conductive pads 206 to a surface above the exposed face 218 facing outward of the first element 110. The plurality of conductive elements 214 can substantially or fully fill the remaining space in the openings 211 and 213 and the dielectric layer 138 extending along the inner faces of the first and second openings 211 and 213. The additional dielectric layer 250 may be electrically insulated from each other. As shown in FIG. 17, a portion of conductive element 214 may extend like a pad or trace over additional dielectric layer 250 in opening 211. However, in other examples, the conductive element may be configured in which only a portion is exposed to a position beyond the opening 211 of the package layer.

Also, as in the embodiment described above (see FIGS. 2 and 3), the optional second conductive element 254 may extend from the conductive pad 206 and may be disposed on the backside of the wafer or microelectronic element 102. Exposed, it can be configured to enable electrical interconnection with external components.

FIG. 18 shows a variant of the embodiment (FIG. 17) in which a dielectric fill material is omitted when forming the second conductive element. In the example of FIG. 18, the conductive material is formed continuously between the conductive pad 206 and the surface 254A of the exposed conductive material for interconnection with external components. In one example, the second conductive element 254A may have a structure described above with reference to FIG. 5, that is, the conductive member 168 is connected to the conductive layer 166 in the opening and exposed to the surface of the microelectronic assembly. .

19 shows a variant in which a plurality of second openings 313A, 313B extend from the first opening 311 of the first element 110. The second opening may be coated with the dielectric layer 328 on the inner side of the second opening, for example, by laser drilling or other substantially vertical patterning method, such as reactive ion etch ("RIE"). After forming so that it can form. Conductive elements 314A, 314B may substantially or fully fill the remaining portion of second openings 313A, 313B after forming dielectric layer 328. As shown in FIG. 19, the conductive elements 314A, 314B may be in contact with the edge of the conductive pad 306 exposed on the surface of the wafer 200. The second conductive element 354 exposed on the backside of the wafer may be located on the dielectric layer 360 in the opening, or the second conductive element 356 may need to include a dielectric layer between the exposed side of the conductive element and the conductive pad. May have a structure as shown in FIG. 20.

21 illustrates a microelectronic assembly according to another embodiment of the present invention in which the conductive element 414 having the contact pads 416 exposed to the outer surface 418 of the package layer 410 has a concave shape. In other words, the conductive element 414 has a relatively large width 420 adjacent to the conductive pad 406 of the wafer 401 and a relatively small width 421 adjacent to the outer surface 418 of the package layer. It may have a shape that changes between). As in this embodiment (eg, FIGS. 1 and 3), the package layer may comprise a semiconductor material, with a dielectric layer 428 between the inner side of the opening 411 and the conductive element 414. Located. As shown in FIG. 21, the second conductive element 454 exposed to the outer surface of the wafer 401 may extend through the conductive pad 406 in the direction of the thickness 408 of the conductive pad 406. In one example, as shown in FIG. 21, the second conductive element 454 is in electrical contact with the first conductive element 414 at the height of the assembly between the neighboring faces of the wafer 401 and the package layer 410. It may include a connection 412.

Hereinafter, the process of forming a microelectronic assembly (FIG. 21) is demonstrated. In the initial stages of the manufacturing process of the microelectronic assembly (FIGS. 22-23), it extends from the major surface of the package layer 410, such as a semiconductor wafer, towards the second major surface 423 of the package layer facing away from it. An opening 411 is formed. Then, as shown in FIG. 24, a dielectric layer may be formed that covers the inner side of the opening and is positioned over the surface 403 of the wafer. Thereafter, a metal layer, conductive compound, or a combination thereof may be deposited into the opening to fill the opening and form the first conductive element 430. Multiple such conductive elements 430 extending from the surface 403 of the wafer toward the surface 423 may be formed simultaneously.

Thereafter, as shown in FIG. 25, the package layer 410 may be adhered to the device wafer 400 including the active semiconductor device, wherein a plurality of conductive pads 406 are exposed on the front surface 404 of the device wafer. It is. The conductive element 430 of the package layer 410 can be mated with the corresponding conductive pad 406 of the device wafer, where at least a portion of the conductive element 430 is to be located on each conductive pad 406. Can be.

Subsequently, as shown in FIG. 26, the thickness of the device wafer 400 can be reduced to a thickness 417, as described above with respect to FIG. 2, to provide a wafer 401 having a reduced thickness. As shown in FIG. 27, an opening 453 extending through the semiconductor region of the wafer 401 can be formed. For example, an etching process may be used that is selectively performed on a dielectric layer (not shown), for example, a passivation layer that may be located below the bottom surface 406A of the conductive pad and a series of ILD layers.

Next, as shown in FIG. 28, the additional thickness extending through the adhesive layer 405, the conductive pad 406, and the dielectric layer (not shown) between the reduced thickness wafer 401 and the package layer 410. An opening can be formed. Next, as shown in FIG. 29, the dielectric layer 452 is formed in the opening, for example, by an electrodeposition technique as described above. The second conductive element 454 is then formed in contact with the first conductive element 430. A portion of the second conductive element 454 is positioned on the back side 451 of the reduced thickness wafer 401, and the dielectric layer 452 is positioned between the semiconductor region and the second conductive element 454.

As shown in FIG. 30, the temporary support wafer or carrier 440 may be attached to the back surface 451 of the wafer 401 using the temporary adhesive 419. Subsequently, as shown in FIG. 31, at least a portion of the first conductive element 430 is formed on the outer surface 418 of the package layer 410 by, for example, grinding, lapping or polishing the thickness of the package layer 410. May be reduced until at least partially exposed. The additional dielectric layer 434 and conductive pad 432 (see FIG. 32) may then be selectively formed in contact with the top of the dielectric layer 434 and the first conductive element, thereby providing a structure as shown in FIG. 32. have. The temporary carrier 440 can then be separated from the device wafer 401 to provide a completed microelectronic assembly, such as shown in FIG. 21, for example.

As shown in FIG. 33, as a modification of the above-described manufacturing method (FIGS. 21 to 32), a wet etch step or another etching step may be performed together with the process shown in FIG. 28. The wet etching step may be performed in a manner that does not invade the material exposed to the exposed surfaces of the first conductive element 430 and the conductive pad 406. In this case, the wet etching step creates an undercut region 442 between the first conductive element 430 and the adjacent conductive pad 406.

34, a dielectric layer 452 is formed, and a region 464 of a metal or conductive metal compound is deposited over the first conductive element 430, and the inside of the undercut region and the conductive pad 406. ) And the surface of dielectric layer 452 to produce a structure as shown in FIG. By depositing the metal region 464 of the second conductive element into the undercut region 442, the metal region may have a larger surface area in contact with the conductive pad 406 of the wafer 401. In this way, process tolerance in the connection of the final structure between the conductive pad 406 and the first and second conductive elements can be improved and the reliability can be improved. Subsequently, additional processes such as those described above (FIGS. 31-32) may be performed to produce microelectronic assemblies as shown in FIG.

As another variation, when the thickness of the package layer 410 is thinned, as shown in FIG. 36, the thickness 460 of the package layer may be further reduced, with the remaining height of the package layer from the front surface 404 of the device wafer. 462 is less than the maximum height 464 of the first conductive element 430 from the front side of the device wafer. Subsequently, a portion of the dielectric layer 428 exposed over the reduced height 462 of the package layer may be removed from the structure to form a structure as shown in FIG. 37, in which a plurality of conductive posts 470 may be formed. It has a substantial portion projecting onto the exposed face 422 of the package layer. In addition, the conductive post 470 may be used for electrodeposition or deposition of a metal having substantially rigidity in the normal microelectronic element operating temperature range such as copper, nickel, aluminum, or a high melting point metal such as tungsten or titanium. By forming, the conductive post 470 can have substantially rigid properties.

FIG. 38 shows another interconnection configuration of the microelectronic assembly according to this variant (FIGS. 36 and 37). As shown in FIG. 38, the substantially rigid conductive post 470 of the microelectronic assembly 480 is installed in a corresponding contact 484 on the dielectric element 426 via a solder-mass 482. Can be. Contact 484 may then be electrically connected to coupling unit 486 such as solder balls, such as tin, indium, or a combination thereof, other members of bonding metal, exposed to lower surface 488 of dielectric element 426. Can be. As shown in FIG. 38, the coupling unit 486 may be used to connect the package 490 to a corresponding contact 492 exposed at the surface 493 of the circuit board 494.

FIG. 39 illustrates a microelectronic assembly 590 according to another variant in which all of the conductive pads 501, particularly the conductive pad 560A, of the wafer do not need to be connected to the first conductive element 530. When forming the first conductive element of the package layer 510 to form the microelectronic assembly 590, the first conductive element at a position corresponding to the conductive pad 506A may be omitted. As described above with respect to FIG. 27, after adhering the device wafer to the package layer and forming an opening 453 over the conductive pad, a block layer, such as a resist pattern, may be formed by the conductive layer forming the conductive pad 506B. It may be used to adjust the position extending through and the position where no hole is formed with respect to the conductive pad 506A.

40 illustrates another variation in which an electrically conductive redistribution layer (“RDL”) 640 may be formed over the surface of the dielectric layer disposed on the package layer 610. The RDL may include electrically conductive traces 642 and pads 644. As shown in FIG. 40, the trace 642 can electrically connect one or more first conductive elements 630 to one or more electrically conductive pads 644 and electrically connect to one or more second conductive elements 654A. . In one example, as shown in FIG. 40, a portion of the second conductive element 654B need not be electrically connected to the first conductive element of the microelectronic assembly 690. As shown in FIG. 40, a portion of the second conductive element may be electrically connected to a source of reference potential, such as ground, through an electrically conductive metal layer 656. In one example, the metal layer 656 may be a bonding layer made of solder, tin, indium, or a combination thereof. Also, as an example, the metal layer 656 electrically connects and couples one or more second conductive elements with a metal ground plane that can function as a heat spreader with thermal conductivity for the microelectronic assembly 690. Can be used.

In a microelectronic assembly according to another variation of the embodiment described above (FIGS. 21-32), two or more first conductive elements 714A, 714B may be along the inner side of the opening 711 of the package layer 710. 41 and 42 extending, a portion including portions 716A, 716B extending through a separate opening between the exposed side of the dielectric layer of the microelectronic assembly 790 and the first opening 711. 1 can be a conductive element. The first conductive elements 714A, 714B can include electrically conductive pads 720A, 720B exposed at the surface 718 of the dielectric layer 718, with reference to FIGS. 41 and 42, above the dielectric layer 718. Can be located. The second conductive elements 754A, 754B of the assembly shown in FIG. 41 are combined with the second conductive elements 755A, 755B shown in FIG. 42, and the second conductive elements in the embodiment described above in connection with FIGS. 17 and 18. There is a similar difference. Specifically, the exposed contact surfaces of pads 754A and 754B (FIG. 41) are located on a dielectric layer over each of the pads 706A and 706B that are connected, in the assembly of FIG. 42, pads 706A that are not connected. 706B) on a dielectric layer.

43 illustrates a number of first conductive elements 814A, 814B extending along the inner side of the stepped opening in the package layer 810 from a connection to the conductive pads 806A, 806B of the wafer, and exposed on the package layer. Conductive pad 832. In this case, the stepped opening includes a first opening 811 extending from the first major surface 812 of the package layer 810 adjacent to the device wafer 801 and a first major surface from the first opening 811. And a second opening 813 extending to at least a second major surface 816 of the package layer 810 located away from it. The first and second openings may have surfaces 821 and 823 extending in various directions that define the vertices 826 that the surfaces 821 and 823 touch. Dielectric material 850 generally covers first conductive elements 814A, 814B. Interconnecting the first conductive elements 814A, 814B to the conductive pads 806A, 806B may be as described above with reference to FIG. 41.

FIG. 44 illustrates an embodiment (FIG. 43) similar to the above-described embodiment (FIG. 42), wherein the second conductive elements 855A, 855B have contact surfaces that are not separated from the conductive pads 806A, 806B by the dielectric material. A modification is shown.

45 illustrates a microelectronic assembly 990 according to a variation of the embodiment described above with reference to FIG. 2. In this example, the first electrically conductive element 914 extending from the conductive pad 906 of the device wafer 901 has an opening 911 extending together through the package layer 910 in the thickness direction 922 of the package layer. , 913, does not match the contour of the inner face. As shown in FIG. 45, the first conductive element may have a cylindrical or truncated conical portion extending in the thickness direction of the package layer to contact the top surface 907 of the conductive pad 906.

Dielectric region 928 is generally provided in openings 911 and 913 in contact with top surface 907 of conductive pad 906, the first conductive element extending through the dielectric region. A portion 928A of the dielectric region may be located over the outward facing surface 926 of the package layer. Electrically conductive pads 916 exposed to the surface of dielectric region 928 may be provided as part of conductive element 914 and may be disposed on top of dielectric region 928. Alternatively, the electrically conductive pad 916 need not be provided.

The microelectronic assembly 990 can be fabricated in a manner similar to that described above with reference to FIGS. 6-13, except that the dielectric region 928 is formed to fill the openings 911, 913 by depositing a dielectric material. . This dielectric region 928 may generally be made of a polymeric material that can be made compliant as determined by the combination of the thickness of the dielectric region and the elastic modulus of the material. After forming the dielectric region, an aperture is formed extending through the dielectric region 928 to expose at least a portion of the conductive pad 906. This hole may be in the form of at least one of a cylindrical or truncated cone. An electrically conductive layer or filling, such as a metal or conductive metal compound, may be provided in the aperture to form a longitudinally extending portion of the first conductive element 914. An exposed conductive pad portion 916 may then be formed over the surface of the dielectric layer 928.

46 shows a modification of the embodiment shown in FIG. 45. In this variant, the second electrically conductive element 954 is similar to the second conductive element 164 described above with respect to FIG. 4, and is exposed to the exposed side of the device wafer 901 and has a conductive pad 906. Is electrically connected).

FIG. 47 is a variation of the embodiment shown in FIG. 46, in which the second dielectric region 938 is positioned above the bottom surface 909 of the conductive pad 906 in the opposite direction to the top surface 907. In this case, the longitudinally extending cylindrical or truncated conical portion 914A of the first conductive element is part of the electrically conductive pad exposed through the conductive pad 906 to the backside 950 facing outward of the device wafer 901. 918 can be extended. In this case, the longitudinally extending portion 914A may not coincide with the contour of the inner surface of any of the openings 911, 913, 915 of the package layer and the element wafer. The fabrication of the microelectronic assembly (FIG. 47) differs in that the dielectric regions 928, 938 are formed in the openings 911, 913, 915, and then through the conductive pad 906 and the dielectric regions 928, 938. Opening cylindrical or truncated openings are formed using techniques such as laser ablation or fine abrasive particle streams (eg, "sand blasting"). Thereafter, for example, conductive pads 916 and 918 can be formed that can be exposed on opposite sides of the microelectronic assembly.

FIG. 48 illustrates a microelectronic assembly 1090 according to a variation of the embodiment shown in FIG. 47, where the second conductive element 1054 may extend through the thickness of the conductive pad 1006. For example, in the manufacturing process of the microelectronic assembly 1090, the conductive pad 1006 in the direction from the bottom surface 1050 of the device wafer 1001, for example, by etching, laser ablation, streaming fine abrasive particles, or the like. The method may include forming an opening 1015 in the device wafer 1001, including patterning a semiconductor device. Such patterning may be limited by the presence of the adhesive layer 1008 between the device wafer and the package layer 1010. After forming the dielectric layer 1038 in the opening 1015, a second conductive element 1054 extending within the opening 1015 can be formed.

FIG. 49 illustrates a variation where the first electrically conductive element 1114 and the second electrically conductive element 1154 meet at a location within the thickness of the package layer 1110. In this case, the second conductive element 1154 extends through the electrically conductive pad 1106 of the device wafer 1101.

As shown in FIG. 50, in a variation of the embodiment (FIG. 49), the second conductive element 1254 includes a portion 1254B that matches the contour of the inner side of the opening 1215 of the device wafer 1201. can do. However, as shown in FIG. 50, the portion 1254A extending within the thickness of the package layer 1210 does not have to coincide with the contour of the inner face of the opening 1213 through which this portion 1254A extends.

FIG. 51 shows a microelectronic assembly according to a variant of the embodiment described above (FIG. 43), in which the first and second conductive pads 1306a, 1306b of the microelectronic element 1310 are formed of a first element. At least substantially exposed within the relatively wide through opening 1313 of 1310. Conductive elements 1314A, 1314B, which are separated from the pads, extend along the inner side of the opening and may be exposed in openings 1316A, 1316B of dielectric layer 1318 positioned over major surface 1320 of the first element.

FIG. 52 shows steps of a method of manufacturing a conductive element according to another variation of the embodiment described above (FIG. 51). In this case, one of the techniques described above is used to form an opening 1313 that extends through the thickness of the first element and is filled with dielectric material 1318. As shown in FIG. 53, a conductive element 1314 similar to the element described above (FIG. 45) may be formed, extending through dielectric region 1318 to contact conductive pads 1306A and 1306B. Optionally, electrically conductive pads 1315A, 1315B may be provided on top of conductive elements 1314A, 1314B, which are typically exposed for interconnection with external components.

With reference to FIG. 54, the method to manufacture a microelectronic assembly by the modification of the above-mentioned embodiment (FIGS. 22-34) is demonstrated. As shown in FIG. 54, an opening 1413 extends from the major surface of the first element 1410 (eg, an element having a CTE less than 10 ppm / ° C.). In one example, the first element may be made of a semiconductor material or a dielectric material. The first element 1410 is then filled with a dielectric material, which may form a layer over the major surface 1420 of the first element. Referring to FIG. 55, a first element 1410 is assembled by adhesion with a microelectronic element 1402 having an electrically conductive pad 1406. Only one of the electrically conductive pads is shown in FIG.

Subsequently, similar to that described above (FIG. 26), as shown in FIG. 56, the reduced thickness 1411 of the microelectronic element is achieved by grinding, lapping, polishing, or a combination thereof as described above. This structure is then assembled with the carrier 1430 (FIG. 57), the thickness of the first element 1410 over the opening 1413, and the opening 1413 being the surface 1417 of the first element (FIG. 58). May be reduced until exposure.

Dielectric layer 1419 may be formed on top of surface 1417, as shown in FIG. 59. An opening 1432 may then be formed extending over the surface 1417 (FIG. 60) and through the dielectric material in the opening 1416 to expose a portion of the conductive pad 1406. Generally, a portion of the upper face 1409 (ie, the face facing away from the microelectronic element 1402) is exposed in the opening 1432. However, in some cases, opening 1432 may extend through pad 1406 such that the inner side of the opening in pad 1406 is exposed.

FIG. 61 shows a subsequent step of depositing metal in one or more steps to form an electrically conductive element 1414 and an electrically conductive pad 1420 on the electrically conductive element 1414. The pad 1420 may or may not be disposed on the surface of the first element 1417 and the dielectric layer 1419. Figure 61 shows an example in which the conductive element is not hollow, i.e. filled with metal. After performing the steps shown in FIG. 61, the carrier is removed from the microelectronic element 1402 to produce a structure as shown in FIG. 62.

FIG. 63 is a variation of the embodiment shown in FIG. 62, in which the conductive element 1424 is formed of a hollow formed by depositing a metal, for example, to cover the inner side of the opening 1432. hollow) can be a structure. The conductive element in the example shown in FIG. 62 or 63 may have an annular structure that matches the contour of the opening 1432 of the dielectric material but does not match the contour of the opening 1413 originally created in the first element 1410. have. Conductive pad 1430 may be positioned over conductive element 1424 and may extend in one or more transverse directions 1440 away from conductive element. The lateral direction is the direction in which the surface 1417 of the first element extends.

The construction and fabrication of the microelectronic assembly and the construction of the microelectronic assembly as a higher level assembly are described in US Provisional Application No. 61 / 419,037, US Application No. 12 / 958,866, 2010, filed December 2, 2010. Disclosed in one or more of US Provisional Application Nos. 12 / 842,717, 12 / 842,651, 12 / 842,612, 12 / 842,669, 12 / 842,692, 12 / 842,587, filed July 23, And structural and fabrication steps, the contents of which are incorporated herein by reference. The structure described above provides a special three dimensional interconnect capability. These capabilities can be used with any type of chip. In one example, a combination of the following chips may be included in a structure as described above: (i) a processor and a memory used with the processor; (ii) multiple memory chips of the same type; (iii) multiple memory chips of various types, such as DRAM and SRAM; (iv) an image processor and an image processor used to process an image from the image sensor; (v) application specific integrated circuits (“ASICs”) and memories. The structure described above can be used in the construction of various electronic systems. For example, system 1500 according to a further embodiment of the present invention includes a structure 1506 as described above in conjunction with other electronic components 1508 and 1210. In the example shown, component 1508 is a microelectronic element and component 1510 is a display screen, although any other component may be used. Of course, although only two parts are shown in FIG. 64 for simplicity, the present system can be configured to include any number of such parts. The structure 1506 described above can be the microelectronic assembly described above in connection with any of FIGS. 1 or 2-63. As another example, all of them may be provided, and any number of such structures may be used. The structures 1506 and components 1508 and 1510 may be installed in a common housing 1501 schematically shown in dashed lines, and electrically interconnected with each other as necessary to form a desired circuit. The illustrated system includes a circuit board 1502, such as a flexible printed circuit board, which includes a plurality of conductors 1504 that connect components together, but FIG. 64 shows only one of them. This configuration is merely an example, and any suitable structure for constructing an electrical connection may be used. The housing 1501 is shown to be a portable housing that can be used in a cellular telephone or PDA, with the screen 1510 exposed on the surface of the housing. The structure 1506 includes a light-sensitive element such as an imaging chip, and may include an optical element such as a lens 1511 for directing light to the structure. 64 is merely an example, and a system generally considered as a fixed structure such as a desktop computer, a router, or the like can also be made using the structure described above.

It should be understood that the above-described features and other modifications or combinations may be used without departing from the scope of the present invention, and the above description is intended to be illustrative, not limiting, of the scope of the present invention.

While the present invention has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present invention. Thus, many modifications may be made to the illustrated embodiments by one skilled in the art and other configurations may be made without departing from the scope of the invention as defined by the claims.

Claims (1)

In a microelectronic assembly,
A first element comprising at least one of a semiconductor material or an inorganic dielectric material;
A major surface attached to the first element, the major surface facing the surface of the first element, a plurality of conductive pads exposed on the major surface, and an active semiconductor device A microelectronic element;
A first opening extending from the exposed side of the first element toward the side facing the microelectronic element of the first element and extending from the first opening to a first conductive pad of the plurality of conductive pads Second openings; And
A conductive element extending within the first and second openings and contacting at least one conductive pad of the plurality of conductive pads
Including;
At a location where the first opening and the second opening meet, an interior surface of the first opening and an interior surface of the second opening extend at different angles with respect to the major surface of the microelectronic element, respectively; ,
The conductive element has a shape of at least one of cylindrical or frusto-conical,
Wherein the first element has a first thickness and the microelectronic element has a second thickness less than or equal to the first thickness,
Microelectronic assembly.

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