KR20120054994A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20120054994A
KR20120054994A KR1020100116439A KR20100116439A KR20120054994A KR 20120054994 A KR20120054994 A KR 20120054994A KR 1020100116439 A KR1020100116439 A KR 1020100116439A KR 20100116439 A KR20100116439 A KR 20100116439A KR 20120054994 A KR20120054994 A KR 20120054994A
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South Korea
Prior art keywords
forming
semiconductor device
groove
manufacturing
film
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KR1020100116439A
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Korean (ko)
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전요한
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에스케이하이닉스 주식회사
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Priority to KR1020100116439A priority Critical patent/KR20120054994A/en
Publication of KR20120054994A publication Critical patent/KR20120054994A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The method of manufacturing a semiconductor device of the present invention includes the steps of forming a groove for forming through silicon vias on a substrate, forming an MPS film on the surface of the groove, forming an oxide film on the surface of the MPS film, and conducting the groove. Landfilling the material.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including through silicon vias.

Recently, with the miniaturization, high performance of electronic products, and the increase in demand for mobile mobile products, the demand for ultra-large-capacity semiconductor memories is increasing. In general, a method of increasing a storage capacity of a semiconductor memory includes a method of increasing a storage density of a semiconductor memory by increasing the degree of integration of a semiconductor chip, and a method of mounting and assembling several semiconductor chips in one semiconductor package. While the former requires a lot of effort, capital and time, the latter can easily increase the storage capacity of the semiconductor memory by only changing the packaging method. In the latter case, there are many advantages in terms of capital, R & D effort, and development time, compared to the former. Therefore, semiconductor memory manufacturers use a multi chip package in which several semiconductor chips are mounted in one semiconductor package. Efforts have been made to increase the storage capacity of semiconductor memory devices.

As a method of mounting a plurality of semiconductor chips in one semiconductor package, there are a method of mounting the semiconductor chip horizontally and a method of mounting the semiconductor chip vertically. However, due to the characteristics of electronic products seeking miniaturization, most semiconductor memory manufacturers prefer stack type multi chip packages in which semiconductor chips are stacked vertically and packaged.

Multi-layer chip package technology can reduce the manufacturing cost of the package through a simplified process and have advantages such as mass production, while lacking a wiring space for electrical connection inside the package due to the increase in the number and size of the stacked chips. have. That is, the conventional multilayer chip package is manufactured in a structure in which a bonding pad of each chip and a conductive circuit pattern of the substrate are electrically connected to each other by a wire in a state where a plurality of chips are attached to a chip attaching region of a substrate. Space for wire bonding is required, and a circuit pattern area of a substrate to which wires are connected is required, resulting in an increase in the size of a semiconductor package. In view of these considerations, a package structure using a through silicon via (TSV) has been proposed as an example of a method of manufacturing a semiconductor device. Packages employing through silicon vias have a structure in which through silicon vias are formed in each chip at the wafer stage, and then physically and electrically connected between the chips vertically by the through silicon vias.

1A to 1B are cross-sectional views of some processes of a semiconductor device employing a conventional through silicon via. After forming the through silicon via 12 in which the metal material such as copper is embedded in the silicon wafer 10, the metal layer 14, which is a metal wiring, is deposited and patterned thereon. The temperature is raised to the temperature of the cooling process. However, after forming through silicon vias in which metal materials such as copper are embedded, the upper metal wirings may be formed by protrusions P of copper constituting the through silicon vias by heat in subsequent deposition and patterning processes of metal layers (wiring layers). Delamination, poor contact, and the like, which cause defects such as contact failure and RC delay.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device that reduces defects and improves reliability of semiconductor devices employing through-silicon vias.

In addition, a method of manufacturing a semiconductor device capable of increasing the adhesion of the conductive material filling the through silicon vias and preventing the protrusion of the conductive material due to the thermal process and the like, such as peeling of the metal wires and defects such as RC delay, can be prevented. To provide.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a groove for forming through silicon vias on a substrate, forming an MPS film on the surface of the groove, and forming an oxide film on the surface of the MPS film. Forming and filling the groove with a conductive material.

In an embodiment, the step of forming a groove for forming through silicon vias on the substrate may be performed by DRIE or laser etching.

In an embodiment, the forming of the MPS film on the surface of the groove may be performed using Si 2 H 6 gas.

In an embodiment, the forming of the MPS film on the surface of the groove may be performed at a temperature of 550 to 700 ° C. using a Si 2 H 6 gas of 2 to 20 sccm.

In an embodiment, the oxide layer may include at least one of SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5, or SOG material.

In one embodiment, the step of forming an oxide film on the surface of the MPS film may be performed by chemical vapor deposition or atomic layer chemical vapor deposition.

In one embodiment, the step of filling the groove with a conductive material may be any one or more of vacuum deposition, sputtering, chemical vapor deposition (CVD), electroless plating, electroplating, dispensing, and screen printing. It can be carried out by a process comprising.

In one embodiment, the conductive material may include copper.

The semiconductor device manufacturing method according to the present invention increases the adhesion (adhesion) of the conductive material filling the through-silicon via to prevent defects such as peeling or RC delay of the metal wiring due to the protrusion of the conductive material to yield and reliability There is an advantage that can be improved.

1A to 1B are cross-sectional views of some processes of a semiconductor device employing a conventional through silicon via.
2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Hereinafter, a process cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2D.

First, a groove V for forming through silicon vias is formed in the substrate 100 (FIG. 2A). The grooves V may be formed by reactive ion etching (RIE). To this end, a photoresist may be applied and patterned to form a photoresist pattern (not shown), and the groove V may be formed using the photoresist pattern as an etching mask. In addition to the typical Deep Reactive Ion Etching (DRIE) method, the Bosch process may be used. The Bosch process induces anisotropic etching by adding a polymer coating using C 4 F 8 plasma after SF 6 plasma. In general, the Bosch process generates a scalloping phenomenon in which unevenness occurs in the side surface of the opening, which may serve to additionally prevent protrusion of a conductive material such as copper embedded in pepper. The groove V may also be formed by laser etching. For example, an ND: YAG laser, a CO 2 laser, or the like can be used, and a laser in the ultraviolet (UV) region can be used. Laser etching has the advantage of no lithography and no toxic gases.

Next, a metastable polysilicon (hereinafter referred to as MPS) layer is formed (FIG. 2B). The MPS layer 102 is formed ruggedly on the surface of the groove V to increase its surface area and form hemispherical grains (HSG). The MPS layer 102 may be formed through chemical vapor deposition (CVD) at a temperature of 550 to 700 ° C. using Si 2 H 6 gas of 2 to 20 sccm. The heat up time can be about 50 seconds, the vent time can be about 10 seconds, and the time to prepare the seed layer for MPS growth is 50? 300 seconds or so, annealing time is 100? You can proceed in about 400 seconds.

Next, an oxide film 104 is formed to facilitate the subsequent embedding of the conductive material (FIG. 2C). The oxide film 104 may include any one or more of SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5, or SOG material, and may be a single layer film or a multilayer film. The formation method may be a chemical vapor deposition (CVD), atomic layer chemical vapor deposition (ALCVD: Atomic Layer Chemical Vapor Deposition), spin coating (coating method) such as spin coating, dip coating (dip coating), thermal oxidation method, etc. can be used. have.

SiO 2 film formation by chemical vapor deposition can be formed by APCVD, LPCVD, or PECVD using SiH 4 and O 2 as reaction sources, or PECVD using SiH 4 and N 2 O as reaction sources. have. In addition, TEOS (Tetraethyl orthosilicat) and O 3 , SiH 2 Cl 2 and N 2 O can be used as reaction sources. The SOG materials are silicate SOG formed by the condensation reaction of Si (OH) 4 , siloxane SOG materials containing organic dopants of -CH 3 or -C 2 H 5 , hydrogen silsesquioxanes (HSQ), and silsesquioxane SOG of methylsilsesquioxane (MSQ). Substances and the like can be used. The liquid SOG solution (sol, sol) may be applied onto the substrate 100 and then rotated at high speed (spin coating, sol gel coating) to form a uniform film. In addition, a spin on dopant (SOD) material including a dopant added to the SOG may be used. More specifically, it may be a polysilazane-based SOG material. The polysilazane-based SOG material is composed of Si-N, Si-H, and NH bonds in a basic skeleton. Baking in an atmosphere containing oxygen and water replaces the Si—N bond with a Si—O bond. There is an advantage that the silicon oxide film can be easily obtained by coating such a SOG material and performing a curing process later. Hardening of the SOG material may be performed by heat treatment at a temperature of 500 ° C. or higher, preferably 600 ° C. or higher for 20 minutes to 1 hour. On the other hand, the step of drying at a temperature range of 200 ℃ to 300 ℃ before the heat treatment at a high temperature for outgassing may be more rough. As such, the oxide film 104 including SiO 2 may be formed through the hardening process of the SOG material. HSQ and MSQ is attached 1.5 oxygen atoms and 1 hydrogen or a methyl group per silicon atom [RSiO 3/2] n ( R: H or CH 3) as having a chemical structure of 3 attached to the silicon atoms of the monomer alkoxy or The sol gels are converted into hydroxyl groups (-OH) under water, acid and base catalysts (hydrolysis) and grow into pre-polymers by condensation between these hydroxyl groups or alkoxy-hydroxylgroups. It is synthesized by sol-gel reaction. The synthesized pre-polymer can be dissolved in a general organic solvent to obtain a thin film having a desired thickness by spin coating, and a stable oxide film can be obtained by thermal curing. HSQ and MSQ can be thermally cured at around 400 ° C. In another example, a SiO 2 film may be formed by thermal oxidation. When silicon is heated in an O 2 or H 2 O atmosphere, a thermal oxide film made of SiO 2 is formed.

In the case of the Al 2 O 3 film, it may be formed through chemical vapor deposition or atomic layer chemical vapor deposition (ALCVD). As an example of atomic layer chemical vapor deposition, first, an aluminum source, Tri Methyl Aluminum (TMA, Al (CH 3 ) 3 ), is 0.1? After flowing for 5 seconds to adsorb to the surface of the lower electrode, a purge step may be performed to remove excess aluminum (Al) source that does not contribute to the above-mentioned adsorption reaction by using a purge gas. . Next, after the O 3 gas, which is a reaction gas, is flowed to react with the aluminum source adsorbed on the surface, a purge step may be performed to remove the unreacted O 3 gas by using a purge gas. The above-described process may be repeatedly performed to form an Al 2 O 3 film of a desired thickness. The pressure in the chamber where the atomic layer chemical vapor deposition process proceeds is 0.1? Maintain 10 torr and process temperature is 25? It may be carried out at 500 ℃.

In addition, after the oxide film 104 is formed, a heat treatment for removing impurities in the oxide film 104 may be further performed. The heat treatment may be by conventional furnace heat treatment or RTP (Rapid Thermal Process) process.

Next, a conductive material is filled in the groove V to form the through silicon via 106 (FIG. 2D). Conductive materials include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), and tin ( Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr) and molybdenum (Mo) may be a single layer film or a multilayer film containing at least one metal selected from the group consisting of However, a single layer film or a multilayer film containing copper is preferable. The embedding of the conductive material may be carried out by a process including any one or more of vacuum deposition, sputtering, chemical vapor deposition (CVD), electroless plating, electroplating, dispensing, and screen printing. There is no limit to the method of landfill.

For example, the groove V may be buried by copper electroplating and a step of forming a seed metal layer prior to copper electroplating may be added. For example, the electrolytic plating solution may include a copper ion source, sulfuric acid (H 2 SO 4 ) to control electrical conductivity, hydrochloric acid (HCl) to control a reduction reaction, and other additives. It may further include. That is, the sulfuric acid (H 2 SO 4) and inserting the CuSO 4 as a copper ion source in water is CuSO 4 Cu 2 + ions, and SO 4 2 - are decomposed into ions.

After copper electroplating, gold (Au) electroplating may be further performed to improve electrical characteristics. On the other hand, the gold-copper component tends to be easily worn due to its weak strength, and when gold is plated directly on the copper, the gold component moves to the copper side and the copper component moves to the gold side, thereby losing the original purpose of improving conductivity by gold plating. Because of this, nickel electroplating may be performed before electrolytic gold plating. The plating solution for gold electroplating may use chloroaurate or gold sulfite as a gold source, and may be used by adding a cyan or non-cyanide compound as a complex, but is not limited thereto. There is no limitation on the method of forming the nickel layer by nickel electroplating. , For example, NiSO 4? 6H 2 O 120 ~ 230g / L, NiCL 2 5 ~ 35g / L, H 3 PO 4 5 ~ 35 g / L aqueous solution or NiSO 4? 6H 2 O 120 ~ 230g / L , including the , Na 4 Cl It may be an aqueous solution containing 10 ~ 30g / L, ZnSO 4 ~ 7H 2 O 20 ~ 50g / L, the nickel layer can be formed under the aqueous solution temperature of 25 ~ 50 ℃, pH 4 ~ 7 conditions However, the present invention is not limited thereto.

For example, the grooves V may be filled with a conductive material containing copper by electroless plating, or the seed metal layer may be formed by electroless plating.

The plating solution used for copper electroless plating may include a copper ion source, a pH adjuster, a reducing agent, and may further include an ethylenediamine tetraacetic acid (EDTA), a surfactant, and the like as a complexing agent. A copper ion source 4 CuSO? 5H 2 O, CuSO 4, etc. can be mentioned, pH adjusting agent KOH, NaOH, etc., to form the reducing agent formaldehyde (HCHO), etc., but the present invention is not limited to this. Copper electroless plating can be achieved by reducing copper with a reducing agent (eg, formaldehyde) by the following reaction.

Cu 2 + + 2HCHO + 4OH - → Cu + 2H 2 O + 2HCO 2 -

Moreover, catalysts, such as a palladium (Pd) and a palladium / tin (Pd / Sn) compound, can be used. When the pH is raised by the pH adjuster (approximately pH 11 or more), strong reduction of formaldehyde occurs and electrons are generated. The electrons flow to the copper ions, and the copper ions are deposited on the palladium catalyst to apply the copper layer.

Thereafter, metal wiring, an interlayer insulating film, or the like may be formed using a known semiconductor process technology. In the semiconductor device manufacturing method of the present invention, the contact area of the copper (conductive layer) forming the through-silicon via can be widened to suppress protruding by heat in the subsequent process, and this can be caused by the peeling of the upper metal wiring, the RC delay, and the like. Can solve the problem.

100 ... substrate 102 ... MPS layer
104 Oxide 106 Through Silicon Via

Claims (8)

Forming a groove on the substrate for forming through silicon vias;
Forming an MPS film on a surface of the groove;
Forming an oxide film on the surface of the MPS film; And
Filling the groove with a conductive material
Method of manufacturing a semiconductor device comprising a. The method of claim 1,
Forming a groove for forming through-silicon vias on the substrate is performed by DRIE or laser etching. The method of claim 1,
Forming an MPS film on the surface of the groove is a method of manufacturing a semiconductor device using a Si 2 H 6 gas. The method of claim 3,
Forming the MPS film on the surface of the groove is a method of manufacturing a semiconductor device is carried out at a temperature of 550 to 700 ℃ using Si 2 H 6 gas of 2 to 20 sccm. The method of claim 1,
The oxide film is a method of manufacturing a semiconductor device comprising any one or more of SiO 2 , Al 2 O 3 , HfO 2 , Ta 2 O 5 or SOG material. The method of claim 1,
Forming an oxide film on the surface of the MPS film is a method of manufacturing a semiconductor device is performed by chemical vapor deposition or atomic layer chemical vapor deposition. The method of claim 1,
The step of filling the groove with a conductive material may be performed by a process including any one or more of vacuum deposition, sputtering, chemical vapor deposition (CVD), electroless plating, electroplating, dispensing, and screen printing. Method for manufacturing a semiconductor device performed. The method of claim 1,
The conductive material includes a semiconductor device manufacturing method.
KR1020100116439A 2010-11-22 2010-11-22 Method for manufacturing semiconductor device KR20120054994A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101422387B1 (en) * 2013-01-16 2014-07-23 포항공과대학교 산학협력단 Fabrication method of next generation cmos image sensors
US9376541B2 (en) 2013-10-10 2016-06-28 Samsung Electronics Co., Ltd. Non-conductive film and non-conductive paste including zinc particles, semiconductor package including the same, and method of manufacturing the semiconductor package
US9412610B2 (en) 2014-03-07 2016-08-09 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US10128168B2 (en) 2013-11-18 2018-11-13 Samsung Electronics Co., Ltd. Integrated circuit device including through-silicon via structure and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101422387B1 (en) * 2013-01-16 2014-07-23 포항공과대학교 산학협력단 Fabrication method of next generation cmos image sensors
US9376541B2 (en) 2013-10-10 2016-06-28 Samsung Electronics Co., Ltd. Non-conductive film and non-conductive paste including zinc particles, semiconductor package including the same, and method of manufacturing the semiconductor package
US10128168B2 (en) 2013-11-18 2018-11-13 Samsung Electronics Co., Ltd. Integrated circuit device including through-silicon via structure and method of manufacturing the same
US10777487B2 (en) 2013-11-18 2020-09-15 Samsung Electronics Co., Ltd. Integrated circuit device including through-silicon via structure and method of manufacturing the same
US9412610B2 (en) 2014-03-07 2016-08-09 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

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