KR20120054674A

KR20120054674A - Structure of hybridmemory supporting high-speed dram interface and data storing and restoring method

Info

Publication number: KR20120054674A
Application number: KR1020100115900A
Authority: KR
Inventors: 고동범
Original assignee: 고동범
Priority date: 2010-11-20
Filing date: 2010-11-20
Publication date: 2012-05-31

Abstract

The present invention relates to a semiconductor memory storage structure and a method for storing and restoring data. Through the high speed processing characteristics of DRAM memory and the interface compatible with DRAM, it reads and writes the external interface and data, and simultaneously reads and writes the external memory without conflicting with the reading and writing of the external interface. The present invention provides a method of supporting backup and restoration of stored volatile data to a nonvolatile storage medium.

Description

Structure of HybridMemory supporting high-speed DRAM Interface and Data Storing and Restoring Method

The present invention relates to a semiconductor memory storage structure and a method for storing and restoring data. In particular, it supports high-speed read and write characteristics of DRAM memory used as storage media and DRAM interface to read and write data requested from external interface controller, and simultaneously to read and write data from DRAM without conflict with external interface. The present invention relates to a method for supporting backup and restoration of stored volatile data to a nonvolatile storage medium.

The storage media constituting the semiconductor memory disk are divided into DRAM and flash memory, and products are coming out based on the speed and stability of information data according to each characteristic. Flash memory has the characteristics of non-volatile as a storage medium, but it shows a limit on speed for writing short size data, and a limit on the number of writes when repeatedly performing high-speed data processing. DRAM has an advantage in data processing and high speed, but has the disadvantage that all facilities are needed to deactivate due to volatile characteristics.

In the past, DRAM-based semiconductor memory disks and storage used a method of storing data on heterogeneous disks using backup batteries and software for data stability. This method has a drawback to data stability depending on the operating environment of the software, high speed backup of the entire data is difficult, and there is a high risk of data loss, and backup efficiency is increased because backup is performed between disks connected to different interfaces. Falls.

Flash memory-based semiconductor memory disks use multi-channel data access and access repositioning techniques to increase the write limit and speed limit, but they have limitations on speed and stability in systems with increased data volume and multiple access. . When a write operation is performed, the flash memory deletes and rewrites the data in the corresponding block.In the write operation, a high voltage is added to the block for a certain period of time. You won't be able to use the entire block. Stability issues exist in server environments where direct data entry is performed continuously.

In case of composing hybrid type semiconductor memory disk by using DRAM and flash memory together, in the past, DRAM is included in the product to improve performance by using cache type and direct use of DRAM interface as external interface. Rather, it uses a separate interface. As a result, when using the direct DRAM interface, performance is lowered and complexity is increased in system configuration. When performing backup or restore from flash memory to DRAM memory, if there is a request for reading or writing from external interface, there will be a conflict in accessing the DRAM memory, which will delay the request of the external interface or require a separate collision avoidance device.

[Patent Document] Domestic Patent 10-0467102 “Data Storage System”

An object of the present invention is to use a combination of the fast read and write speed of the DRAM and the non-volatile characteristics of the flash memory in order to increase the processing speed of the existing operating software and application software, the operation speed and interface of the DRAM (DRAM) It is to construct high-speed semiconductor storage device that supports it as it is and maintains compatibility with DRAM interface.

In order to solve this problem, the present invention implements a semiconductor memory storage device using a DRAM and a flash memory as a storage medium by combining the DRAM and the flash memory in a hybrid manner to activate the DRAM. Dual-port DRAM is used as a method to use as a storage space and to use flash memory as an inactive area for stably storing data, and to prevent conflicts with external interfaces while using the existing DRAM interface. The DRAM and flash interfaces during the restoration (FIG. 1), single-port DRAM (DRAM) and Req and Ack signals (FIG. 2), internal data buffers or cache and switch blocks (FIG. 3), or during restoration. And using the internal switch to indicate when the restore is complete via the flash interface. 4) and the like, to provide a method of quickly implementing restoration and backup while preventing collisions and maintaining compatibility with the DRAM interface.

As described above, a memory module composed of a DRAM and a flash memory performs data input / output at an interface compatible with the DRAM and enables high-speed data processing, and backs up the input-modified data to the flash memory. This enables stable storage of data.

Even during data restoration to DRAM by rebooting the system, the requested data can be directly supplied from DRAM or sent out from the data backed up to flash memory by using internal data buffer and dummy logic. By eliminating the time when the memory storage device stops working, the processing speed of the operating software and application software is increased, and the data reading and writing speed is faster. Interface compatibility with existing DRAMs improves the availability of semiconductor memory disks by reducing complexity in system design and making it easy to replace existing DRAM and flash storage devices.

As data changes are made in the DRAM, backups are made when schedule changes are made, or power is cut off, the stability of the flash memory backup device is guaranteed by reducing the element lifespan caused by the input workload of the flash memory. The operation speed and stability of the storage device can be improved.

1 is a block diagram showing an embodiment of a hybrid memory module using a dual-port DRAM (DRAM) according to the present invention
2 is a block diagram illustrating an embodiment of a hybrid memory module using a single-port DRAM according to the present invention.
3 is a block diagram illustrating still another embodiment of a hybrid memory module using a single-port DRAM and a switch logic according to the present invention.
FIG. 4 is a block diagram illustrating still another embodiment of a hybrid memory module using a DRAM and a flash interface according to the present invention.

5 is a flowchart illustrating an initialization operation of a hybrid memory module according to the present invention.
6 is a flowchart of a data restoration operation of the hybrid memory module according to the present invention.
7 is a flowchart of a data read operation of the hybrid memory module according to the present invention.
8 is a flowchart of a data write operation of the hybrid memory module according to the present invention.
9 is a flowchart illustrating operations when the power of the hybrid memory module according to the present invention is cut off.
10 is a flowchart of a data backup operation of the hybrid memory module according to the present invention.

“…” Described in the specification. Wealth ”,“… Gi ”,“… Module ”means a unit that processes at least one function or operation, which may be implemented by a combination of hardware or software. Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings. A preferred embodiment of the hybrid memory structure according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an embodiment of a hybrid memory structure using a dual-port DRAM according to the present invention. The hybrid memory storage module includes a DRAM block 120 and a flash block 130, and includes a DRAM controller 102 and a flash controller 103 for managing each memory and back up or restore data of the DRAM. Backup controller 104 and data buffer 106, power on / off detection logic 101, state register 105 for checking the operation status, IO controller for processing input / output data, module operation control and DMA It is composed of an internal control controller 110 including a 107 may be implemented as a memory module or a semiconductor one chip of a semiconductor memory disk.

The IO controller 107 receives a control signal related to reading and writing from the external interface controller 200 and an external signal according to an external state change, such as a DRAM controller 102, a backup controller 104, and a flash controller 103. The controller receives the signal from the interface controller 200 according to the operation state, reads data from the DRAM block through the DRAM controller 102, and transfers the data to the interface controller 200 or data received through the interface controller 200 in the DRAM block. Performs an operation to control writing. At this time, when there is a read and write request of the interface controller 200 during the restoration operation from the flash block to the DRAM block, an access conflict may occur for the DRAM block. As shown in the drawing, the DRAM block 120 is a dual-port DRAM. Configure the request to execute the request without conflict. Since the DRAM block is configured as a dual port, access conflicts between the external interface controller 200 and the internal control controller 110 are eliminated, and the time point at which the internal control controller 110 starts restoration is a read request of the external interface controller 200. If it is started earlier, the internal restoration speed can be faster than the speed of the external interface controller reading. Therefore, the external interface controller 200 performs the post-restore process without waiting for the restoration to be completed or performing the restoration by itself. can do. The IO controller 107 serves to convert read and write commands of the interface controller 200 to the DRAM and flash interfaces, and may perform a security algorithm to protect related contents.

In addition, the state register receives control signals and external signals from the IO controller to determine whether it is in normal operation, whether to proceed with backup, whether to restore data, and whether or not the external interface controller 200 has completed saving the current state during backup. Characterized in that it can be stored and confirmed.

The backup controller 104 backs up the data of the changed DRAM block 120 to the flash memory when the power is cut off or when the write command is input to the IO controller 107 as a control signal, the physical address of the DRAM block in which the write data is stored. Has a log buffer to store the size. The flash block 130 stores the data to be backed up at the same logical block address location as the physical block address of the DRAM block, and during a restore operation for a read request from an IO controller when a data restoration operation is performed by restarting after a power failure. The controller operates in response to the reading of the data, and when the restoration is completed, the backup controller 104 and the IO controller 107 perform internal control to perform an external request in the DRAM block. The backup controller 104 monitors the log buffer when a write command is received from the IO controller 107, and when the log buffer fills more than a certain amount, the backup controller 104 backs up the data of the DRAM block to the flash block. If blocked, the backup is performed regardless of the amount of logs stored in the log buffer. In order to restore the state of the external interface controller 200, which had before power off, when the power is restored, the state of the external controller is stored in a predetermined area of the DRAM, and then all or a part of the DRAM is stored. In order to proceed with the backup of the external interface controller 200 and the internal backup controller 104 performs a backup and restore using a state register. Alternatively, in general, the log buffer may be turned off, read and write may be processed only in the DRAM block, and all contents of the DRAM may be backed up to the flash block when the power is turned off.

2 is a diagram illustrating an embodiment of a hybrid memory structure using a single-port DRAM. In order to prevent single-port DRAM from crashing, it sends a req signal to the DRAM controller, receives an Ack, and performs backup and restore. In the case of using the single-port DRAM, by using the Req signal and the Ack signal, a method for recognizing a section not used by the external interface controller 200 may be provided to restore the partial section. After some restoration, the Req signal is deactivated, the Req signal is generated again, and waiting for the Ack signal. Then, the restoration can be performed without collision by equally sharing the external interface and the access section. Or at this time, the external interface controller 200 and the internal control controller 110 alternately access each other after the access time is determined by the external interface controller 200 and the internal control controller 110 during restoration without using the Req signal and the Ack signal. Next, the restoration is performed by the method accessed by the internal control controller 110, and after the restoration is completed, the internal control controller 110 notifies the external interface controller 200 by an interrupting method or the like so that the external interface controller 200 can receive the recovery. It is possible to use a method of making the DRAM block accessible by itself.

3 is a block diagram illustrating another embodiment of a hybrid memory structure using a single-port DRAM according to the present invention. The control signal and the data switch 140 may detect the power on / off or the interface controller 200 or the internal backup controller according to a select signal generated according to a situation such as a read or write request from the interface controller 200. The DRAM is accessed by selecting a control signal and a data signal of the single-port DRAM generated from 110). If a read and write request occurs in the DRAM interface controller 200 during flash to DRAM recovery, the internal backup controller 110 reads the data from the flash block using the data buffer 106 as a cache, and stores the data in advance. Then, the interface controller After performing the read and write request from the 200 and the restoration is completed, the read and write request is directly performed from the DRAM. Since the flash is slow, a part of the content is stored in a buffer or a cache and the request of the interface controller 200 is processed. Alternatively, to prevent a single-port DRAM from crashing, it may send a req signal to the DRAM controller, receive an Ack, and then perform backup and restore.

FIG. 4 illustrates a case in which the external interface controller 200 has a DRAM and flash interface, and dummy processing (ignores) a read request of the external interface controller 200 or restores an internal data buffer during restoration using the internal switch 140. When the restoration is completed and the restoration is completed, the external interface controller 200 notifies the external interface controller 200 that the restoration is completed through the flash interface, and the external interface controller 200 knows that the restoration process is completed. And the internal control controller 110 controls to perform the external read and write requests through the DRAM interface.

5, 6, 7, 8, 9, and 10 are flowcharts illustrating operations of a hybrid memory module that is a storage medium of a semiconductor memory storage device according to the present invention. As shown in FIGS. 5, 6, 7, 8, 9, and 10, the operation steps of the hybrid memory module include an operation of initializing, restoring data, reading data, writing data, shutting down external power, and data backup.

In the initialization operation of FIG. 5, when power is input (s100), power on / off logic detects power on and changes the power flag of the state register to '1' (s101). If the auxiliary power flag is '0' (s102), change the recovery flag to '1' because the auxiliary power is not turned on after the power goes out. If the auxiliary power flag is “1” and the state register is '1' (s103), terminate the initialization operation and wait for the next command. If the normal flag is '0', change the restore flag of the state register to '1' and restore the data. Instructs s104 to terminate the initialization operation.

In FIG. 6, when the data restore (s200) command is transmitted to the backup controller, the backup controller executes a restore command, issues a read command to the flash controller, converts a logical address of the flash block into a physical address of the DRAM block, and writes to the DRAM controller. Give a command to write to the DRAM block (s201), check whether all data restoration is completed (s202), and repeat until all data is restored. When the restoration is completed, change the restoration flag of status register to '0' and normal flag to '1' and terminate the operation. When the dual-port DRAM is used, the internal backup controller 110 performs recovery using the remaining ports of the DRAM not used by the external DRAM interface controller 200.

In FIG. 7, when the read data command (s300) is transferred from the interface controller to the module's IO controller (s301) and the normal flag is '0' (s302) in the state register, the read (s303) command is sent to the internal data buffer. Read the data that matches the physical address of or transfer dummy data (no meaningful data) .If flag is 1, send read (s304) command to DRAM controller to read data from DRAM block and finish the operation. do.

In FIG. 8, when a data write (s400) command is transferred from the interface controller to the IO controller (s401), a write command is issued to the DRAM controller, and data received through the IO controller is stored in the DRAM block (s402), and the backup controller The address and data size stored in the DRAM block are recorded in the log buffer (s403). At this time, the backup controller checks whether the log data is over the specified limit in the log buffer 106 (s404), and if the number exceeds the specified number, the backup controller changes the backup flag of the status register to '1' and performs data backup (s405) and ends. . When a write request occurs at the same location as the log data recorded in the log buffer 106, a function of not leaving log data in the log buffer may be selectively applied to increase backup efficiency in the future. If you save.

In FIG. 9, when the external power is cut off while the semiconductor memory device is operating (S500), power off is detected by the power on / off logic to change the power flag of the status register to '0' (s501), and backup power If it is determined (s502), switch to backup power, if any, change the auxiliary power flag of the state register to '1' (s503), and if not, increase the time that the power is on using battery or supercap. The data backup command s504 is received for a time to perform a backup.

When the data backup (s600) command is issued in FIG. 10, the backup controller monitors the power flag of the state register to determine the number of logs stored in the log buffer when the log buffer is stored in the case of (s601). The backup counter value is set (s602), and when the power flag is '0', the number of log data accumulated in the log buffer is set as the backup counter value (s603) regardless of the specified limit of the buffer. After checking the log data recorded in the log (s604), the data is backed up to the logical address of the flash block corresponding to the physical address of the DRAM block (s605), and the backup counter value is decreased by one (s606). If it is not 0 '(s607), the log data is repeatedly checked (s604). If the backup counter is' 0', the backup flag of the status register is changed to '0' and the operation is terminated. The specified limit related to the log buffer storage is set by defining the number of logs or the log buffer capacity. Alternatively, it can be set to have an infinite log buffer to back up the entire DRAM area at power-off.

100: hybrid memory module
101: Power on / off detection and battery power supply block
102: DRAM controller
103: flash controller
104: backup or restore controller
105: status register block
106: data buffer or cache block
107: I / O Controller
110: internal control controller
120: Dual-port (DP) or Single-port (SP) DRAM block
130: flash block
200: DRAM or Flash Interface Controller

Claims

In the memory for storing data,
An input / output controller configured to receive a control signal related to reading and writing data from an external DRAM interface controller;
A DRAM block comprising one or more DRAM memories and storing data generated according to system operation;
A flash memory block for storing backup data of the DRAM block;
A control signal and data switch for selecting signals and data of an external DRAM interface controller and an internal backup controller;
A handshake signal (Req, Ack) controller to prevent access collision of the DRAM;
An access period controller for preventing an access collision of the DRAM;
Internal flash interface logic that informs the controller of the completion of the restore and backup, and
And a backup controller for backing up changes of data stored in the DRAM block to the flash memory or restoring backup data stored in the flash memory to the DRAM block.

The method of claim 1,
A dual-port DRAM block for preventing an access collision of the DRAM block caused by a request of an external interface controller during restoration in the DRAM block;
A data buffer or cache logic for processing a request from a DRAM interface controller during restoration in the backup controller;
Logic for generating dummy data in response to a request of an external flash interface controller during restoration in the internal flash interface logic;
A status register for storing a backup state of an external interface controller and indicating an operating state in the system using a plurality of flags;
A DRAM controller controlling data input / output of the dual-port or single-port DRAM block; And
Flash memory controller for controlling data input and output of the data buffer or cache logic and flash memory
Hybrid memory further comprising one or more of the following.

The method of claim 2,
The backup controller,
When a write command is input from the input / output controller, data stored in the DRAM block is transferred to the flash memory using data information stored in the log buffer,
And receiving a data recovery command from the input / output controller, processing the request of an external DRAM interface controller without collision by using the data buffer and simultaneously transferring data stored in flash to the DRAM block.

In a hybrid memory for backing up data stored in the DRAM memory using a flash memory, a method for restoring the backup data stored in the flash memory to the DRAM memory,
(a) reading a backup data stored in a flash memory when a data restoration command is received according to a reboot of the system;
identifying a physical address of a DRAM block that is the same as a logical address of the flash memory; And
(c) sequentially writing the backup data to a RAM block of the same physical address
(d) storing the backup data in an internal data buffer
(e) generating a handshake signal to avoid collision with external read / write requests during restoration and processing using an internal data buffer or cache.

In the method of reading data from the hybrid memory for backing up the data stored in the DRAM memory using the flash memory,
(a) checking a setting of a normal flag indicating whether the system is operating normally when a command to read data is received; And
(b) read the data stored in the DRAM memory when the normal operation of the system is confirmed through the normal flag; and an internal data buffer having a portion of the flash memory when abnormal operation of the system is confirmed through the normal flag. And reading data stored in the hybrid memory.

In the method of reading data from the hybrid memory for backing up the data stored in the DRAM memory using the flash memory,
(a) confirming completion of data restoration while a data read command is received through the external flash interface controller; And
and (b) informing the external flash interface controller of the completion state through the flash interface when the completion of the restoration operation of the system is confirmed.