KR20120054319A - Spread spectrum clock generator having phase interpolator and generating method of spread spectrum clock using the same - Google Patents

Spread spectrum clock generator having phase interpolator and generating method of spread spectrum clock using the same Download PDF

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KR20120054319A
KR20120054319A KR1020100115640A KR20100115640A KR20120054319A KR 20120054319 A KR20120054319 A KR 20120054319A KR 1020100115640 A KR1020100115640 A KR 1020100115640A KR 20100115640 A KR20100115640 A KR 20100115640A KR 20120054319 A KR20120054319 A KR 20120054319A
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South Korea
Prior art keywords
clock signal
spread spectrum
spectrum clock
counter value
counter
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KR1020100115640A
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Korean (ko)
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김종선
이경록
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홍익대학교 산학협력단
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Abstract

The present invention relates to a spread spectrum clock signal generator and a spread spectrum clock signal generation method, comprising: a delay synchronization circuit unit generating a reference clock signal, and receiving a reference clock signal generated by the delay synchronization circuit unit and performing triangular frequency modulation to spread the signal; And a spread spectrum clock signal generator for generating a spread spectrum clock signal, wherein the spread spectrum clock signal generator changes a frequency of the spread spectrum clock signal by changing a delay of a phase interpolator.
The spread spectrum clock signal generator having a phase interpolator according to the present invention provides a low power programmable spread spectrum clock signal with a small area, unlike a conventional spread spectrum clock signal generator having complicated components, and a phase. There is an advantage in that triangular frequency modulation can be easily performed through an interpolation method.

Description

Spread spectrum clock generator having phase interpolator and method for generating spread spectrum clock signal using same {spread spectrum clock generator having phase interpolator and generating method of spread spectrum clock using the same}

The present invention relates to a spread spectrum clock signal generating apparatus and a spread spectrum clock signal generating method, and more particularly, a phase interpolation which includes a phase interpolator to easily spread triangular frequency modulation to spread a clock band. The present invention relates to a spread spectrum clock signal generating device having a signal and a spread spectrum clock signal generating method using the same.

As the size and resolution of liquid crystal display (LCD) TV panels increase, the clock speed of the digital system and the wire length between the chips increase, and as a result, the Electro Magnetic Interface (hereinafter referred to as 'EMI') is further increased. It is increasing. To reduce this EMI, traditional methods such as adding shielding or using EMI filters are used, but there is a problem that the cost and hardware area are greatly increased.

A more cost effective and well known method of reducing EMI is a spread spectrum clock generator (SSCG), which modulates the clock signal and spreads the clock signal energy over a much wider frequency band. It is a method using.

SSCG is an IC-level approach to meeting regulations such as the Federal Communications Commission (FCC) rules, and conventional SSCGs are typically implemented based on PLLs. However, PLLs usually have larger jitter due to phase noise buildup and are difficult to design due to stability issues. Therefore, PSC-based SSCG has a problem that it is not easy to implement with digital circuits having a large substrate noise.

In order to overcome the problems caused by the jitter characteristic of the PLL, a delay cell array (SCA) based on a delay cell array (DCA) has been proposed. However, DCA-based SSCGs require a large number of cascade inverter delay cells, resulting in increased power consumption (120mW at 100MHz) and area.

The technical problem to be solved by the present invention is the spectrum of the clock signal without distortion of the clock duty cycle ratio by easily performing triangular frequency modulation through the phase interpolation technique based on the delay synchronization circuit (DLL) rather than the phase delay circuit (PLL) Disclosed is a spread spectrum clock signal generation apparatus having a phase interpolator capable of easily reducing electromagnetic interference by spreading the signal.

Another technical problem to be solved by the present invention is to provide a method for generating a spread spectrum clock signal that can easily perform triangular frequency modulation through a phase interpolation technique using a spread spectrum clock signal generator having a phase interpolator. have.

According to an aspect of the present invention, there is provided a spread spectrum clock signal generator including a phase interpolator according to an embodiment of the present invention. And a spread spectrum clock signal generator for generating a spread spectrum clock signal, wherein the spread spectrum clock signal generator changes a frequency of the spread spectrum clock signal by changing a delay of a phase interpolator.

According to another aspect of the present invention, there is provided a spread spectrum clock signal generation method using a spread spectrum clock signal generator having a phase interpolator. When (SSC_EN) is high, the spectrum clock signal spread through triangular frequency modulation is output.

The spread spectrum clock signal generator having a phase interpolator according to the present invention provides a low power programmable spread spectrum clock signal with a small area, unlike a conventional spread spectrum clock signal generator having complicated components, and a phase. There is an advantage in that triangular frequency modulation can be easily performed through an interpolation method.

1 is a block diagram of a spread spectrum clock signal generator having a phase interpolator according to the present invention.
2 is a diagram illustrating a detailed configuration of a digital-to-analog converter of a spread spectrum clock signal generator having a phase interpolator according to an embodiment of the present invention.
3 is a diagram illustrating a detailed configuration of a phase interpolator of a spread spectrum clock signal generator having a phase interpolator according to the present invention.
4A to 4D are diagrams for describing a phase modulation method using a spread spectrum clock signal generator having a phase interpolator according to an embodiment of the present invention.
5A to 5C are diagrams for describing a phase modulation method using a spread spectrum clock signal generator having a phase interpolator according to another embodiment of the present invention.
6A to 6C are diagrams for describing a phase modulation method using a spread spectrum clock signal generator having a phase interpolator according to another embodiment of the present invention.
7A and 7B are diagrams showing the results of triangular frequency modulation simulation according to the present invention.
8 is a diagram showing the results of FFT simulation of the present invention.
9 is a diagram illustrating a modulation frequency according to the resolution of a DAC.

Hereinafter, with reference to the accompanying drawings to describe the present invention in more detail.

1 is a block diagram of a spread spectrum clock signal generator having a phase interpolator according to the present invention.

As shown in FIG. 1, a spread spectrum clock signal generator having a phase interpolator according to the present invention includes a delay synchronization circuit unit 100 and a spread spectrum generator 200.

The delay synchronization circuit unit 100 includes a voltage control delay line VCDL, a phase detector PD, and a charge pump CP. The delay synchronization circuit unit 100 provides the spread spectrum generator 200 with a reference clock signal A / Ab having a frequency of 200 MHz (f c ).

The spread spectrum generator 200 spreads the spectrum by performing triangular frequency modulation on the reference clock signal A / Ab provided from the delay synchronization circuit unit 100, and includes a delay buffer (DB, 210) and a digital signal. An analog counter 220, a current adjustable digital-to-analog converter 230, a digitally adjustable phase interpolator (PI, 240), and a CMOS buffer (250).

The delay buffers DB and 210 receive the reference clock signal A / Ab provided from the delay synchronization circuit unit 100 and generate a delay clock signal B / B b which is delayed for a predetermined time.

The digital-analog counter 220 receives a spread spectrum clock enable signal SSC_EN and a reference clock signal A / Ab having a frequency of f c and outputs an n-bit counter output signal b <n-1: 0. >)

The counter output signal b <n-1: 0> is designed to have an output vector of n bits to adjust the delay of the programmable phase interpolator. In this case, n may be various embodiments, but preferably 6 or more. The modulation frequency is dependent on the n value. As the n value increases, the modulation frequency decreases, and as the n value decreases, the modulation frequency increases.

The current adjustment digital-analog converter 230 receives the counter output signal b <n-1: 0> and generates two bias end currents I a , I b to generate the phase interpolator PI, 240).

2 is a diagram illustrating a detailed configuration of a current adjusting digital-analog converter of a spread spectrum clock signal generator having a phase interpolator according to the present invention.

As shown in FIG. 2, current regulated digital-to-analog converter 230 is biased by the digital-to-analog counter 220 and provides a programmable bias end current I a , I b to the phase interpolator 240. Used to provide.

The phase interpolator (PI, 240) is the reference clock signal (A / A b ) and the delay clock using two bias end currents (I a , I b ) provided by the current adjustment digital-to-analog converter (230) Phase interpolation of the signal B / B b generates a phase interpolation clock signal O / O b having an intermediate phase.

3 is a diagram illustrating a detailed configuration of a phase interpolator of a spread spectrum clock signal generator having a phase interpolator according to the present invention.

As shown in FIG. 3, the phase interpolator (PI) 240 according to the present invention includes a reference clock signal A / A b and a delay clock signal, which are differential signals of two small swings transmitted from the delay buffer 210. by interpolation between the (B / B b) to generate a phase interpolator clock signal (O / O b).

At this time, the phase interpolation clock signal O / O b has its phase dependent on the two bias end currents I a and I b , and the reference clock signal A / A b and the delay clock signal B / B. b ) has an intermediate phase between.

As described above, the phase of the phase interpolator (PI) 240 is digitally adjusted by the order of the digital-analog counter 220 and the current adjusting digital-analog converter 230.

At this time, interpolation between the reference clock signal A / A b and the delay clock signal B / B b is performed according to the change of the two bias end currents I a , I b , where the first bias end current ( The sum of Ia) and the second bias tip current Ib is always constant.

That is, when the second bias tip current Ib increases, the first bias tip current Ia decreases, and the phase of the phase interpolation clock signal O / Ob is the phase of the second delay clock signal B / B b . Getting closer to This can be expressed as the following equation (1).

Figure pat00001

Where 0 <x <1.

The frequency of the spread spectrum clock signal, the final output signal, is moved by changing the interpolation delay of the phase interpolator 240 every cycle. The total frequency spread range (+/− 0.5% to +/− 2%) is also controlled by the propagation delay time of the programmable delay buffer 210. Therefore, unlike conventional PLL-based SSCG or DCA-based SSCG, it is possible to spread the spectrum of the digital clock signal while minimizing power consumption and area.

The CMOS buffer 250 receives a phase interpolation clock signal O / O b , converts the CMOS signal to a CMOS level, and outputs a spread spectrum clock signal SSCLK.

4A and 4D are diagrams illustrating a phase modulation method of a spread spectrum clock signal generator having a phase interpolator according to an embodiment of the present invention.

4A shows the pattern generation of the digital-analog counter 220. In this case, the digital-analog counter 220 may be various embodiments, but for convenience of description, n = 8, that is, an 8-bit digital-analog counter will be described as an example. The 8-bit digital-analog counter has a total of 60 states.

When n = 8, when the spread spectrum clock enable signal SSC_EN is low, the digital-analog counter 220 is reset to the state of output count b <7: 0> = [00000000] = 1. . When the spread spectrum clock enable signal SSC_EN becomes high for the spread spectrum, the digital-analog counter 220 changes its state from 1 to 60 sequentially for each input clock, and the sequence is repeated. Returns to the reset state of.

At this time, the phase interpolator 240 outputs a phase interpolation clock signal O / Ob while depending on a counter value given to each state.

4B is a diagram illustrating an actual delay change of the phase interpolator 240.

Referring to FIG. 4B, the delay change of the phase interpolator 240 shows the frequency modulation of the triangular waveform. The modulation frequency fm is obtained by the following equation (2), where T is the period (= 1 / f c ) of the input reference clock signal A / Ab. On the other hand, the delta (Δ), which is a linearly increasing or decreasing delay change value, is given by the following equation (3).

Modulation Frequency (f m ) = 1 / (T * S n ) Equation (2)

Delta (△) = t bdelay / 2 n Equation (3)

Where t bdelay is the delay time of the programmable delay buffer 210, T is the period of the reference clock signal A / Ab, and S n is the number of states of the counter pattern. At this time, when n = 8, the number of states is 60.

At this time, the frequency range may be determined as follows.

f c + Δf = f max = 1 / (T-15 * Δt) equation (4)

f c -Δf = f min = 1 / (T + 15 * Δt) equation (5)

4C is a table showing a DAC counter pattern and an output vector b <7: 0> for triangular frequency modulation, and FIG. 4D shows modulation with two input signals A and B of the phase interpolator 240 in a time domain. It is a figure which shows the period comparison between phase interpolation clock signal O which is an output signal.

As shown in Figs. 4C and 4D, in the triangular frequency modulation, the period of the phase interpolation clock signal O is T, T + 1 * Δt, T + 2 * Δt, T + 3 * Δt, ㅇ, T + 15 * Δt, T + 14 * Δt, T + 13 * Δt, o, T + 1 * Δt, T, T-1 * Δt, T-2 * Δt, o, T-15 * Δt, T-14 * Δt It can be done every 60 cycles by changing sequentially, such as T-1 * Δt.

In the present invention, the triangular frequency modulation method is used because it has a reasonably flat power density in the frequency domain according to the present invention.

For triangular frequency modulation to occur, the frequency of the reference clock signal must increase and decrease periodically. Referring to FIG. 6, the value of the digital-analog counter according to the present invention has a pattern in the order of 0, 1, 3, 6, 10, 15, 21, 28, 36, o. Accordingly, the delta t of the counter value increases or decreases by 1, such as 1, 2, 3, 4, 5, 6, 7, 8, ㅇ. This changes the degree of phase interpolation in the phase interpolator at every clock period.

If the counter value is in the same order as 0, 1, 2, 3, 4, 5, 6, ㅇ ㅇ and the delta t is fixed to 1, the phase interpolation generated by the phase interpolator PI The degree of is fixed and frequency modulation does not occur.

In the time domain, as shown in FIG. 4D, the clock period changes only when the delta? Is not fixed but increases by one, thereby causing frequency modulation.

A method of generating a spread spectrum clock signal according to an embodiment of the present invention will be described in more detail with reference to FIGS. 4A to 4D.

In the spread spectrum clock signal generation method according to the present invention, in order to have a frequency in which the reference clock signal increases and decreases periodically, the following first to fourth sections must be sequentially performed.

The first section and the second section are sections in which the counter value increases, except that a pattern change occurs in which the increment delta (△) value of the counter value increases and decreases. In the case of n bits, since the counter value may have a value up to 2 n , the counter value incremented in the first section should not exceed 2 n-1 , and the counter value incremented in the second section may exceed 2 n . none.

In the first section, the counter value increases while the increment delta (△) value of the counter value increases linearly by one. At this time, the first section proceeds until the counter value does not exceed 0 to 2 n-1 . This is because the counter value exceeds 2 n at the end of the second section when the counter value exceeds 0 to 2 n-1 in the first section.

4A to 4D, when n = 8, the first section increases the counter value by increasing the counter delta (△) value of the counter value linearly by 1 until 15, thereby increasing the counter value to 2 7 , that is, 128. It proceeds until it reaches 120 (state 16), a value that does not exceed.

Subsequently, in the second section, the counter value increases while the increment delta (Δ) value of the counter value decreases linearly by 1, and the counter value does not exceed 2 n . On the other hand, the second section proceeds until the increment delta (△) value of the counter value becomes zero.

4A to 4D, when n = 8, when the second section ends, the counter value is 2 8 , that is, 225 (state 31) which is a value not exceeding 256.

The third section and the fourth section are sections in which the counter value decreases, except that a pattern change occurs in which the increment delta (△) value of the counter value increases and decreases. For n bits, the counter value cannot exceed the value of 2 n . Therefore, the counter value decreases by the value increased in the first section in the third section and symmetrically in the first section and the second section in which the counter value increases, and the counter value increases by the value increased in the second section in the fourth section. This decreases.

In the third section, the counter value decreases while the increment delta (Δ) value of the counter value decreases linearly by one. 4A to 4D, when n = 8, the third section decreases the counter value by linearly decreasing the increment delta (Δ) value of the counter value by 1 until -15 (state 46).

In the fourth section, the counter value decreases while the increment delta (△) value of the counter value increases linearly by one. At this time, the fourth section proceeds until the counter value becomes 0 (state 60).

On the other hand, as the first to fourth sections are sequentially performed, the counter value is periodically changed to cause triangular frequency modulation.

That is, since the phase interpolator 240 shown in FIG. 3 generates an output signal having any intermediate phase between two inputs due to a change in current, a change in delta t indicates a change in current. . As the delta t increases or decreases linearly with each period, the phase interpolator 240 emits a clock having a different phase every period, and the phase change causes the frequency of the clock to change due to the change of the period. .

5A to 5C and 6A to 6C are diagrams for explaining a phase modulation method in the case of n = 10 and n = 12, which are other embodiments of the present invention.

In the case of n = 10, the number of states becomes 124, and in the case of n = 12, the number of states changes to 252, but the frequency modulation method according to the progress of each section is the same as described with reference to FIGS. 4A to 4D. It will be omitted.

7A and 7B are diagrams showing the results of the triangular frequency modulation simulation of the present invention.

Referring to FIG. 7A, when the spread spectrum clock enable signal SSC_EN is low when the frequency f c of the reference clock signal A / Ab is 200 MHz, the spread spectrum mode does not operate and thus the frequency Since no modulation occurs, the center clock frequency represents 200 MHz, which is the frequency of the reference clock signal. On the other hand, when the spread spectrum clock enable signal SSC_EN is high, triangular frequency modulation occurs while band spreading of the clock signal occurs.

In this case, the center clock frequency varies from 198 MHz to 202 MHz, and thus the frequency spread ratio is about + 1% (+2 MHz) to -1% (-2 MHz).

FIG. 7B illustrates a frequency profile when the spread spectrum clock enable signal SSC_EN is low and high, similarly to FIG. 7A. At this time, the center clock frequency is changed from 196Mz to 204MHz, and the frequency spread ratio is about + 2% (+ 4MHz) to -2% (-4MHz). See FIGS. 7A and 7B. As the delay time of the programmable delay buffer increases, the spreading ratio of the frequency increases.

8 is a diagram showing the results of FFT simulation of the present invention.

The spread of the spectrum can be optimized by selecting the appropriate modulation frequency. In an embodiment, when an 8-bit DAC counter is used, modulation frequency fm = 1 / (5ns * 60) = 3.333 MHz. At this time, EMI reduction at the peak-to-peak level of the spread spectrum can be estimated using Equation (6) below.

EMI reduction (dB) = 10 * log (δ * n * f c / f m ) equation (6)

Here, δ denotes a spreading ratio of the spectrum at the peak-to-peak level, f c denotes a frequency of a reference clock signal, f m denotes a modulation frequency, and n * f c denotes a harmonic frequency.

For example, if the peak-to-peak spreading ratio δ is 0.04 (+/- 2.0%), the EMI reduction estimated by equation (6) is 3.8 dB at 200 MHz (n = 1) and 600 MHz (n = 3), respectively. And 8.5 dB.

Referring to FIG. 8, it can be seen that EMI reductions of 1.28 dB, 6.46 dB, and 9.25 dB were observed at a spreading rate of +/- 2.0% and frequencies of 200 MHz, 600 MHz, and 1 GHz, respectively. As a result, the difference between the value estimated by Equation (6) and the value shown in FIG. 8 corresponds to about 2 dB.

Referring to Equation (6), it can be seen that EMI can be improved by reducing the modulation frequency. On the other hand, the modulation frequency can be reduced by increasing the resolution of the n-bit DAC and the modulation frequency according to the resolution of the DAC is shown in FIG.

9 is a diagram illustrating a modulation frequency according to the resolution of a DAC.

Referring to FIG. 9, when using a 12-bit DAC, the modulation frequency is 793 kHz. In this case, a 7 dB EMI reduction is expected.

As described above, unlike a conventional spread spectrum clock signal generator using a phase delay circuit (PLL), the spread spectrum clock signal generator having a phase interpolator according to the present invention has a triangular structure while minimizing the use of a complex analog circuit. The digital clock signal is spread by frequency modulation.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but the present invention has been described by way of example and is not intended to limit the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention.

Claims (10)

In the spread spectrum clock signal generator,
A delay synchronization circuit unit generating a reference clock signal;
A spread spectrum clock signal generator for receiving a reference clock signal generated by the delay synchronization circuit and generating a spread spectrum clock signal by performing triangular frequency modulation;
And a spread spectrum clock signal generator having a phase interpolator to change a frequency of the spread spectrum clock signal by changing a delay of a phase interpolator. The method of claim 1, wherein the spread spectrum clock signal generator
A delay buffer configured to generate a delay clock signal in which the reference clock signal is delayed for a predetermined time;
A digital-analog counter receiving a spread spectrum clock enable signal SSC_EN and the reference clock signal to generate a counter output signal;
A current adjustment digital-analog converter configured to receive the counter output signal and generate two phase interpolator bias end currents;
A phase interpolator configured to receive the reference clock signal and the delay clock signal and output a phase interpolated clock signal having a phase interpolated; And
And a CMOS buffer for receiving the phase interpolated clock signal, converting the signal to a CMOS level, and outputting a spread spectrum clock signal. 3. The phase interpolator of claim 2, wherein the phase interpolator
And outputting the phase interpolation clock signal having an intermediate phase between the reference clock signal and the delay clock signal by changing the two bias terminal currents. The method of claim 2,
The sum of the two bias end currents is always constant and the weight change of the two bias end currents is digitally controlled by the order of the digital-analog counter and the current adjustment digital-analog converter. A spread spectrum clock signal generator. A method for generating a spread spectrum clock signal using a spread spectrum clock signal generator having a phase interpolator according to any one of claims 2 to 4,
And spreading the spread spectrum clock signal through triangular frequency modulation when the spread spectrum clock enable signal SSC_EN is high. The method of claim 5, wherein the counter output signal is
And spreading out a digital value along a counter pattern of the digital-analog counter for triangular frequency modulation. The method of claim 6, wherein the counter output signal is
And an output vector of n bits (n is a natural number of 6 or more) to adjust the delay of the phase interpolator. The method of claim 7, wherein
A first section in which the counter value increases while the increment delta value of the counter value increases linearly by one;
A second section in which the counter value increases while the increment delta value of the counter value decreases linearly by one;
A third section in which the counter value decreases while the increment delta (△) value of the counter value decreases linearly by one; And
An incremental delta (△) value of the counter value is provided with a fourth section in which the counter value decreases while linearly increasing by one;
3. A method of generating a spread spectrum clock signal according to claim 1, wherein triangular frequency modulation occurs as the counter value periodically changes and increases or decreases as the first to fourth sections sequentially progress. The method of claim 8,
The first section proceeds until the counter value does not exceed 0 to 2 n-1 , and the second section has an increment delta (Δ) value of the counter value without the counter value exceeding 2 n . The method of generating a spread spectrum clock signal, characterized in that it proceeds until it becomes zero. The method of claim 9,
The counter value decreases by the counter value increased in the first section in the third section, and the counter value decreases by the counter value increased in the second section in the fourth section until the counter value becomes zero. A method of generating a spread spectrum clock signal, characterized in that proceeding.
KR1020100115640A 2010-11-19 2010-11-19 Spread spectrum clock generator having phase interpolator and generating method of spread spectrum clock using the same KR20120054319A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112703556A (en) * 2018-07-02 2021-04-23 苹果公司 Phase modulation system and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112703556A (en) * 2018-07-02 2021-04-23 苹果公司 Phase modulation system and method

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