KR20120051919A - Semiconductor apparatus including mos transistor - Google Patents

Semiconductor apparatus including mos transistor Download PDF

Info

Publication number
KR20120051919A
KR20120051919A KR1020100113291A KR20100113291A KR20120051919A KR 20120051919 A KR20120051919 A KR 20120051919A KR 1020100113291 A KR1020100113291 A KR 1020100113291A KR 20100113291 A KR20100113291 A KR 20100113291A KR 20120051919 A KR20120051919 A KR 20120051919A
Authority
KR
South Korea
Prior art keywords
gate
mos transistor
main
pattern
line width
Prior art date
Application number
KR1020100113291A
Other languages
Korean (ko)
Inventor
정재홍
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100113291A priority Critical patent/KR20120051919A/en
Publication of KR20120051919A publication Critical patent/KR20120051919A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor device which includes a metal oxide semiconductor transistor is provided to change the shape of a gate of the transistor which has a biggest line width within a dummy pattern, thereby preventing collapse or deformation of a transistor pattern which has a small gate line width. CONSTITUTION: A gate line width(L21) of a first MOS(Metal Oxide Semiconductor) transistor(T21) is formed smaller than a gate line width(L20) of a second MOS transistor(T22). First and second MOS transistors respectively include first and second active regions(220,240). The first MOS transistor comprises a pair of first sources and a first drain(S21,D21). The first source and the first drain are electrically connected to a data input/output line by contacts(222,224) which are respectively formed on the first source and the first drain. The second MOS transistor comprises a pair of second sources and a second drain(S22,D22).

Description

Semiconductor device including MOS transistor TECHNICAL FIELD

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to semiconductor devices including MOS transistors.

In general, a semiconductor device includes a plurality of MOS transistors, and as they are highly integrated, the gate length of the MOS transistors (hereinafter, referred to as “line width”) is gradually decreasing. As the gate line widths of the plurality of MOS transistors become smaller, semiconductor devices tend to apply dummy patterns as a technique for helping to form patterns of the MOS transistors.

1 is a plan view showing a semiconductor device including a conventional MOS transistor.

As shown in FIG. 1, the semiconductor device 10 includes dummy patterns DM1, DM2, and DM3 formed between the plurality of MOS transistors T1 and T2 and the MOS transistors T1 and T2 and on an outer surface thereof. It includes.

Each of the MOS transistors T1 and T2 is exposed to the gates G1 and G2 formed in a line shape on the semiconductor substrate of each of the active regions 12 and 14 and exposed to both sides of the gates G1 and G2. Source and drains S1, D1, S2, and D2 formed by implanting N-type or P-type conductive impurities into the semiconductor substrate are included.

In addition, the line width L1 of the dummy patterns DM1, DM2, and DM3 corresponds to the gates G1 and G2 of the neighboring MOS transistors T1 and T2 for pattern reinforcement of the MOS transistors G1 and G2. It is formed in the same manner as the line width L2.

However, while the conventional semiconductor device 10 may include the MOS transistors T1 and T2 having the same size as shown in FIG. 1, a plurality of MOS transistors having different sizes as shown in FIG. 2 at the same time. (T3, T4) may be included.

In this case, the first MOS transistor T3 has the gate G3 of the first line width L4, and the second MOS transistor T4 has the gate G4 of the second line width L5 that is larger than the first line width L4. )

The semiconductor device 20 further includes dummy patterns DM4 and DM65 formed of third line widths L3 and L6 having the same size as the first line width L4.

However, the dummy patterns DM4 and DM5 fall together when the gate G4 of the second MOS transistor T4 having the second line width L5 larger than the third line widths L3 and L6 falls down. As a result, the cases where the dummy patterns DM4 and DM5 and the gate G3 of the first MOS transistor T3 formed in the adjacent region also fall together are often generated.

As such, the collapse of the gate can be attributed to the high aspect ratio.

Therefore, it is seeking to prevent the collapse of the derby pattern formed adjacent to the gate pattern of a wide line width.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and provides a semiconductor device including a MOS transistor for reinforcing a pattern of the MOS transistor.

In an embodiment, a semiconductor device including a MOS transistor may include: a plurality of MOS transistors each having a first and second gate line widths having different sizes; And a dummy pattern disposed between the plurality of MOS transistors to form a distance between the plurality of MOS transistors, wherein a gate of the MOS transistor having the second gate line width among the plurality of MOS transistors partially exposes an active region. It includes a MOS transistor having a hole.

A semiconductor device including a MOS transistor according to another embodiment of the present invention includes a MOS transistor having first and second gates having different line widths on a semiconductor substrate having one active region, wherein the first gate The second gate having a larger line width includes a MOS transistor in which holes are formed to protect the pattern of the first gate.

The semiconductor device including the MOS transistor according to the present invention changes the shape of the gate of the transistor having the largest gate line width in the dummy pattern or the semiconductor device, and has a small gate line width from collapse of the transistor having the largest gate line width. It is possible to prevent the transistor pattern from being deformed or collapsed.

1 is a plan view illustrating a semiconductor device including a MOS transistor according to an exemplary embodiment of the present invention;
2 is a plan view showing a semiconductor device including a MOS transistor according to another conventional embodiment;
3 is a plan view showing a semiconductor device including a MOS transistor according to a first embodiment of the present invention;
4 is a plan view showing a semiconductor device including a MOS transistor according to a second embodiment of the present invention;
5 is a plan view showing a semiconductor device including a MOS transistor according to a third embodiment of the present invention;
6 is a plan view showing a semiconductor device including a MOS transistor according to a fourth embodiment of the present invention; and
7 is a plan view showing a semiconductor device including a MOS transistor according to a fifth embodiment of the present invention.

3 is a plan view showing a semiconductor device including a MOS transistor according to a first embodiment of the present invention.

As shown in FIG. 3, the semiconductor device 200 including the MOS transistors according to the first embodiment of the present invention includes first and second MOS transistors T21 and T22 and a dummy pattern DM21.

The plurality of MOS transistors T21 and T22 may be configured of the first and second MOS transistors T21 and T22 as shown in FIG. 3. In the second embodiment of the present invention, the first and second MOS transistors T21 and T22 are limited to two for convenience of description, but in general, it is preferable to include at least two MOS transistors.

Here, since the first and second MOS transistors T21 and T22 of the semiconductor device 200 of the present invention are generally formed differently according to internal device characteristics of the semiconductor device 200, different sizes are shown in FIG. 3 of the present invention. A semiconductor device including first and second MOS transistors T21 and T22 having a structure will be described. Accordingly, the line width L21 of the gate G21 of the first MOS transistor T21 may be smaller than the line width L20 of the gate G22 of the second MOS transistor T22 according to the characteristics of the internal device of the semiconductor device. Can be.

Each of the first and second MOS transistors T21 and T22 generally includes first and second active regions 220 and 240.

More specifically, the first MOS transistor T21 has a first gate G21 formed in a line shape formed on the semiconductor substrate having the first active region 220 and a first active exposed to both sides of the first gate G21. Each region 220 includes a pair of first sources and first drains S21 and D21 formed by implanting N-type or P-type conductive impurities. In addition, the first source and the first drain S21 and D21 may be electrically connected to the data input / output line (not shown) by the contacts 222 and 224 formed in the respective ones.

The second MOS transistor T22 may include the second gate G22 formed on the semiconductor substrate having the second active region 240 and the exposed second active regions 240 exposed to both sides of the second gate G22. And a pair of second sources and second drains S22 and D22 formed by injecting N-type or P-type conductive impurities into the same. In addition, the contacts 242 and 244 formed in the second source and the second drain S22 and D22 are electrically connected to the data input / output line (not shown).

Meanwhile, in the semiconductor device 220 according to the first embodiment of the present invention, the first and second MOS transistors T21 having a smaller line width as they are highly integrated between the first and second MOS transistors T21 and T22 are formed. A dummy pattern DM21 may be further included to protect the first and second gates G21 and G22 of the T22s from an external environment.

In this case, the shape of the dummy pattern DM21 may be, for example, a line shape 'l', and the line width L22 of the dummy pattern DM21 may be the line width L21 of the first gate G21. It can be formed the same as).

Meanwhile, the gate G22 of the second MOS transistor T22 of the present invention is an intermediate region of the active region 340 as shown in FIG. 3 to protect the pattern and the dummy pattern DM21 of the first MOS transistor 21. May have a hole (not shown) that exposes some

In this case, as shown in FIG. 3, the holes may be formed to have the shape of a line, and may be formed to expose the opposite ends of the exposed active region 240 while being disposed on the source side. As shown in FIG. 4, the surface of the intermediate region of the active region 240 may be exposed.

More specifically, as shown in FIG. 3, the gate G22 of the second MOS transistor T22 according to the first exemplary embodiment of the present invention has the first main part 262 and the second main part 264 depending on the hole formation. The first connection part 266a and the second connection part 266b may be divided.

Each of the first and second main parts 262 and 264 extends in a direction parallel to the dummy pattern DM21 and may be formed by being separated by holes.

The first main part 262 is spaced apart from the first MOS transistor T21 by a first distance and has a first line width L23. The second main part 264 is spaced apart from the first MOS transistor T21 by a second distance that is farther than the first distance and has a second line width L25.

In this case, the first line width L23 is formed to be smaller than the second line width L25 and is the same as the line width L21 of the gate G21 of the first MOS transistor T21. The pattern of the first MOS transistor T21 can be maintained from the collapse of the transistor T22.

The first connection part 266a is arranged between the first and second main parts 262 and 264, and is configured to connect upper parts of the first and second main parts 262 and 264 facing each other. Can be. In addition, the first connecting portion 266a may be formed to extend in a direction orthogonal to the first and second main portions 262 and 264.

The second connecting portion 266b is arranged between the first and second main portions 262 and 264, and is formed to have lower portions of the first and second main portions 262 and 264 facing each other. Can be. In addition, the second connecting portion 266b may be formed in a direction parallel to the first connecting portion 266a and extending in a direction orthogonal to the first and second main portions 262 and 264.

Here, the first and second connection parts 266a and 266b may be formed to have the same line width L24.

As such, the first main part 262, the second main part 264, the first connection part 266a and the second connection part of the gate G22 of the second MOS transistor T22 according to the first embodiment of the present invention. 266b may be connected to each other to form a 'ㅁ' shape.

As described above, in the semiconductor device 300 according to the first exemplary embodiment, the first main part 262 having the same line width as the dummy pattern DM21 is disposed in the first region adjacent to the dummy pattern DM21. By arranging the second main part 264 having a larger line width than the dummy pattern DM21 in the second area spaced farther from the dummy pattern DM21, the dummy pattern DM21 is disposed in the second main part. 264 can be protected.

However, since the first main part 262 may fall due to the second main part 264, in order to prevent the upper part and the lower part of the first and second main parts 262 and 264 facing the first main part 262. The first and second connecting portions 266a and 266b for connecting may be formed. However, the first embodiment of the present invention is not limited thereto, and as shown in FIG. 5 showing the third embodiment of the present invention, the first main part 462 may be further separated from the collapse of the second main part 464. It may further include a third connecting portion 466c connecting the intermediate regions of the first and second main portions 462 and 464 facing each other to completely complement.

6 is a plan view showing a semiconductor device including a MOS transistor according to a fourth embodiment of the present invention.

As shown in FIG. 6, the semiconductor device 500 including the MOS transistor according to the fourth embodiment includes the MOS transistor T51. Here, the semiconductor device 500 includes a plurality of transistors which jointly use each other's source and drain regions on one active region 520. The MOS transistor T51 according to the present invention may include a plurality of transistors. It can be said that the transistor of.

Accordingly, the MOS transistor T51 may include the first gate G51 and the second gate G52, the first and second gates spaced apart from each other at a predetermined interval on the semiconductor substrate having one active region 520. And a pair of first to third impurity regions 522, 524, and 526 formed by injecting N-type or P-type conductive impurities into each of the active regions 520 exposed between both sides of the G51 and G52. The first to third impurity regions 522, 524, and 526 may be electrically connected to data input / output lines (not shown), which are upper layers, by contacts 542, 544, and 546 formed in the first to third impurity regions 522, 524, and 526, respectively.

More specifically, a first impurity region 522 is formed at one end of the first gate G51 of the MOS transistor T51, and a third impurity region 526 is formed at the other end of the second gate G52 of the MOS transistor T51. ) Is formed. The second end of the first gate G51 and the second end of the second gate G52 overlap each other, and a second impurity region 524 is formed to form the second end of the first gate G51 and the second gate G52. One end may be connected in common.

In this case, the line width L50 of the second gate G52 of the semiconductor device including the MOS transistor according to the fourth embodiment of the present invention is larger than the line width L51 of the first gate G51 as shown in FIG. 6. Can be.

As a result, when the second gate G52 having the line width L50 larger than the first gate G51 is conventionally collapsed, the first gate G51 may be affected and collapsed. Accordingly, in order to prevent this, the second gate G52 according to the present invention may include the first main gate pattern 562, the second main gate pattern 564, the first connection pattern 566a, and the second connection pattern 566b. And a third connection pattern 566c.

The first main gate pattern 562 extends in a direction parallel to the first gate T51 and is spaced apart from each other at a first predetermined distance. The first main gate pattern 562 may be formed to have the same line width L52 as the line width L51 of the first gate T51.

The second main gate pattern 564 is arranged to be spaced apart from the first gate T51 by a second predetermined distance that is further than the first predetermined distance. The second main gate pattern 564 may be formed to have a line width larger than the line width L52 of the first main gate pattern 562.

The first connection pattern 566a may connect upper portions of the first and second main gate patterns 562 and 564 facing each other.

The second connection pattern 566b may connect lower portions of the first and second main gate patterns 562 and 564 facing each other.

The third connection pattern 566c is disposed between the first and second main gate patterns 562 and 564 facing each other, and may connect an intermediate region of the first and second main gate patterns 562 and 564.

In this case, the first to third connection patterns 566a, 566b, and 566c extend in a direction orthogonal to the first and second main gate patterns 562 and 564. In addition, the first to third connection patterns 566a, 566b, and 566c may be arranged in a direction parallel to each other, that is, in a 'three' shape, and the line widths L53 may be the same.

As described above, the present invention divides and arranges the second gate G52 into the first main gate pattern 562 and the second main gate pattern 564 so that the first gate G51 is formed by the second gate G52. It can prevent the fall.

In addition, in the semiconductor device 500 including the MOS transistor according to the fourth embodiment of the present invention, in order to prevent the first main part 562 from being collapsed by the second main part 564, the first through the first to the second parts may be used. Three connection patterns 566a, 566b, and 566c may be formed.

7 is a plan view showing a semiconductor device including a MOS transistor according to a fifth embodiment of the present invention.

As shown in FIG. 7, the semiconductor device 600 including the MOS transistor according to the fifth embodiment of the present invention includes the MOS transistor T61. Here, the semiconductor device 600 includes a plurality of transistors which jointly use each other's source and drain regions on one active region 620. The MOS transistor T61 according to the present invention may include a plurality of transistors. It can be said that the transistor of.

The MOS transistor T61 has a first gate G61, a second gate G62, and a first and second gate G61 spaced apart from each other at a predetermined interval on the semiconductor substrate having one active region 620. G62) includes a pair of first to third impurity regions 622, 624, and 626 formed by injecting N-type or P-type conductive impurities into each of the active regions 620 exposed between both sides and between the two regions. The first to third impurity regions 622, 624, and 626 may be electrically connected to data input / output lines (not shown), which are upper layers, by contacts 642, 644, and 646 formed on the first to third impurity regions 622, 624, and 626, respectively. In this case, the data input / output line in the present invention may be, for example, a bit line.

More specifically, a first impurity region 622 is formed at one end of the first gate G61 of the first MOS transistor T61, and a third at the other end of the second gate G62 of the second MOS transistor T61. An impurity region 626 is formed. In addition, a second impurity region 624 is formed between the opposite end of the first gate G61 and one end of the second gate G62, so that the other end of the first gate G61 and one end of the second gate G62 are formed first. The second impurity region 624 may be connected in common.

In this case, the line width L60 of the second gate G62 of the semiconductor device including the MOS transistor according to the fifth embodiment of the present invention is larger than the line width L61 of the first gate G61 as shown in FIG. 7. Can be.

The second gate G62 includes the first main gate pattern 662, the second main gate pattern 664, the third main gate pattern 666, the first auxiliary pattern group 665a, 665b, and 665c, and the second gate pattern 662. Auxiliary pattern groups 667a, 667b, and 667c.

The first main gate pattern 662 extends in a direction parallel to the first gate G61 and is spaced apart from the first predetermined distance. The first main gate pattern 662 may be formed to have the same line width L62 as the line width L61 of the first gate G61.

The second main gate pattern 664 extends in a direction parallel to the first gate G61 and is spaced apart from the first gate G61 at a second predetermined distance farther from the first predetermined distance. In addition, the second main gate pattern 664 may be formed to have a line width L64 greater than the line width L61 of the first gate G61.

The third main gate pattern 666 extends in a direction parallel to the first gate G61, and is spaced apart from the first gate G61 by a third predetermined distance farther from the second predetermined distance. In addition, the line width L66 of the third main gate pattern 666 is formed to be the same as the line width L61 of the first gate G61 and is smaller than the line width L64 of the second main gate pattern 664. It is preferable.

The first auxiliary pattern groups 665a, 665b, and 665c connect the first and second main gate patterns 662 and 664 facing each other. As shown in FIG. 8, the first and second main gate patterns 662 may be used. , 664 a first connection part 665a for connecting the opposite upper parts of the first and second main gate patterns 662, 664, and a second connection part 665b for connecting the opposite lower parts of the first and second parts; And a third connector 665c connecting the intermediate portions of the second main gate patterns 662 and 664 to face each other.

In this case, the first to third connection parts 665a, 665b, and 665c may extend in a direction orthogonal to the first and second main gate patterns 662 and 664. The first auxiliary pattern groups 665a, 665b, and 665c may be arranged in parallel to each other, and the line widths L63 may be the same.

The second auxiliary pattern groups 667a, 667b, and 667c connect the second and third main gate patterns 664 and 666 facing each other. As shown in FIG. 7, the second and third main gate patterns 664, A fourth connection part 667a connecting the opposite upper parts of the 666, a fifth connection part 667b connecting the opposite lower parts of the second and third main gate patterns 664 and 666, and second and third connections; And a sixth connector 667c connecting the intermediate portions of the main gate patterns 664 and 666. In this case, the fourth to sixth connectors 667a, 667b, and 667c may extend in a direction orthogonal to the second and third main gate patterns 664 and 666. The second auxiliary pattern groups 667a, 667b, and 667c are arranged in parallel to each other, and the line widths L65 may be the same.

As described above, when the semiconductor device 600 according to the present invention has a plurality of MOS transistors having different line widths on one active region 620, the smallest line width is changed by modifying the shape of the gate having the largest line width. The branch can compensate for the pattern of the MOS transistor.

More specifically, as shown in FIG. 7, it is possible to prevent the first gate G61 having the first line width L61 from collapsing by the second gate L62 having the larger second line width L60. . To this end, as in the present invention, by sequentially forming the first and second main gate patterns 662 and 664 having a line width as the distance from the neighboring distance to the first gate G61, the conventional dummy pattern The formation of the pattern of the first gate G61 may be helped without forming a plurality of layers, and the total area of the semiconductor device may be reduced because the dummy pattern may not be formed.

In addition, in the semiconductor device 600 according to the fifth embodiment of the present invention, the third main gate pattern 666 may prevent the first main gate pattern 662 from being collapsed by the second main gate pattern 664. ) And the first and second auxiliary pattern groups 665a, 665b, 665c, 667a, 667b, and 667c may further reinforce the pattern of the MOS transistors.

As those skilled in the art can realize the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

10, 20, 100, 200, 300, 400, 500, 600: semiconductor device

Claims (12)

A plurality of MOS transistors formed with first and second gate line widths having different sizes; And
The dummy pattern is disposed between the plurality of MOS transistors to include a dummy pattern.
And a gate of the MOS transistor having the second gate line width among the plurality of MOS transistors includes a MOS transistor having a hole partially exposing an active region. The method according to claim 1,
A gate of the MOS transistor having the second gate line width is
A first main part and a second main part separated by the holes and arranged in parallel with each other;
A first connection part formed between the first and second main parts and connecting upper portions of the first and second main parts; And
And a MOS transistor formed between the first and second main parts, the MOS transistor including a second connection part arranged in parallel with the first connection part and connecting lower portions of the first and second main parts. The method of claim 2,
And a MOS transistor arranged between the first and second connectors and further comprising a third connector connecting intermediate regions of the first and second main parts. The method of claim 3,
The line width of the first main part includes a MOS transistor having a same size as the dummy pattern and the first gate line width. The method of claim 4, wherein
And the hole includes a MOS transistor configured to expose side ends of the exposed active region facing each other. 6. The method of claim 5,
The hole includes a MOS transistor formed to expose the surfaces of the active region. Including a MOS transistor having a first and a second gate formed on a semiconductor substrate having a single active region having a different line width,
The second gate having a line width larger than the first gate includes a MOS transistor in which holes are formed to protect the pattern of the first gate. The method of claim 7, wherein
The second gate is,
A first main gate pattern spaced apart from the first gate at a first predetermined distance and formed to have the same line width as that of the first gate;
A second main gate pattern formed with a line width larger than that of the first main gate pattern;
A first connection pattern connecting upper portions of each of the first and second main gate patterns;
A second connection pattern connecting lower portions of each of the first and second main gate patterns; And
And a MOS transistor disposed between the first and second connection patterns, the MOS transistor including a third connection pattern connecting middle regions of the first and second main gate patterns. The method of claim 8,
The second gate is,
A first main gate pattern spaced apart from the first gate at a first predetermined distance and arranged in a parallel direction, the first main gate pattern having the same line width as the line width of the first gate;
A second main gate pattern spaced apart from the first gate at a second predetermined distance and arranged in a parallel direction, the second main gate pattern having a line width larger than that of the first main gate pattern;
A third main gate pattern spaced apart from the first gate at a third predetermined distance and arranged in parallel with each other, the third main gate pattern having the same line width as the line width of the first gate;
A first auxiliary pattern group connecting the first and second main gate patterns; And
And a MOS transistor including a second auxiliary pattern group connecting the second and third main gate patterns. 10. The method of claim 9,
The first to third main gate patterns may be arranged to sequentially extend in a direction parallel to the gate, and the semiconductor device may include a MOS transistor disposed at a position spaced apart from the gate by a longest distance from the third main gate pattern. . The method of claim 10,
The first auxiliary pattern group,
A first connector connecting the upper portions of the first and second main gate patterns facing each other;
A second connector connecting the lower portions of the first and second main gate patterns facing each other; And
And a MOS transistor including a third connection portion connecting the intermediate portions of the first and second main gate patterns to face each other. The method of claim 11, wherein
The second auxiliary pattern group,
A fourth connector connecting the upper portions of the second and third main gate patterns facing each other;
A fifth connector connecting the lower portions of the second and third main gate patterns facing each other; And
And a MOS transistor including a sixth connection portion connecting the intermediate portions of the second and third main gate patterns facing each other.
KR1020100113291A 2010-11-15 2010-11-15 Semiconductor apparatus including mos transistor KR20120051919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100113291A KR20120051919A (en) 2010-11-15 2010-11-15 Semiconductor apparatus including mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100113291A KR20120051919A (en) 2010-11-15 2010-11-15 Semiconductor apparatus including mos transistor

Publications (1)

Publication Number Publication Date
KR20120051919A true KR20120051919A (en) 2012-05-23

Family

ID=46268785

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100113291A KR20120051919A (en) 2010-11-15 2010-11-15 Semiconductor apparatus including mos transistor

Country Status (1)

Country Link
KR (1) KR20120051919A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379107B2 (en) 2014-04-22 2016-06-28 Samsung Electronics Co., Ltd. FinFET semiconductor devices including dummy structures
US11903187B2 (en) 2021-04-30 2024-02-13 Samsung Electronics Co., Ltd. Semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379107B2 (en) 2014-04-22 2016-06-28 Samsung Electronics Co., Ltd. FinFET semiconductor devices including dummy structures
US9653363B2 (en) 2014-04-22 2017-05-16 Samsung Electronics Co., Ltd. Methods of fabricating FinFET semiconductor devices including dummy structures
US11903187B2 (en) 2021-04-30 2024-02-13 Samsung Electronics Co., Ltd. Semiconductor devices

Similar Documents

Publication Publication Date Title
US10290653B2 (en) Integrated circuit layout structure
US7469389B2 (en) Standard cell library, method of designing semiconductor integrated circuit, semiconductor integrated circuit pattern, and semiconductor integrated circuit
US7919792B2 (en) Standard cell architecture and methods with variable design rules
US20070111405A1 (en) Design method for semiconductor integrated circuit
KR100477042B1 (en) Semiconductor integrated circuit and standard cell layout designing method
US20060113533A1 (en) Semiconductor device and layout design method for the same
US20150303216A1 (en) Semiconductor device
US20080180132A1 (en) Semiconductor device and method of fabricating the same
US20120292666A1 (en) Semiconductor device
US20140217513A1 (en) Semiconductor integrated circuit device
KR102133377B1 (en) Semiconductor device and method for manufacturing the same
US9595523B2 (en) Semiconductor integrated circuit devices
US11557610B2 (en) Semiconductor integrated circuit device
US10748933B2 (en) Semiconductor device
US20180308796A1 (en) Metal Patterning For Internal Cell Routing
US20130234211A1 (en) Semiconductor device
JP2008192841A (en) Semiconductor integrated circuit
KR20160105263A (en) System on chip and method of design layout for the same
CN105609466B (en) Metallic section is as the regional interconnection part in then pad and IC device
KR100366905B1 (en) Semiconductor integrated circuit having thereon on-chip capacitors
KR20120051919A (en) Semiconductor apparatus including mos transistor
KR100808605B1 (en) Semiconductor device of periphery circuit area
JP4761914B2 (en) Standard cell library, semiconductor integrated circuit design method, semiconductor integrated circuit pattern, and semiconductor integrated circuit
CN114927519A (en) Semiconductor structure, integrated circuit and method for forming semiconductor structure
JP7323847B2 (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination