KR20120049031A - Senucibductir memory device and refresh method thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a refresh method thereof are provided to selectively perform a self refresh operation among a plurality of word lines by using refresh information. CONSTITUTION: A memory cell array(110) includes a plurality of word lines. A self refresh controller(150) controls a self refresh operation of the memory cell array. A plurality of word lines include a dummy word line(112). The dummy word line stores refresh information about the word line for a refresh operation.

Description

Semiconductor memory device and its refresh method {SENUCIBDUCTIR MEMORY DEVICE AND REFRESH METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a refresh method thereof, and more particularly, to a semiconductor memory device and a refresh method thereof for reducing self refresh power consumption.

Recently, there is a demand for large-capacity DRAM in mobile electronic products including smart phones. In general, in a semiconductor memory device such as a DRAM, data stored in a memory cell may be changed by a leakage current. Therefore, a refresh operation is required to periodically recharge the data stored in the memory cell.

However, even when demand exists, it is difficult to employ DRAM due to an increase in power consumption due to refresh operation in DRAM in a standby mode.

Therefore, in order to employ DRAM, it is necessary to reduce power consumption due to refresh operation in the DRAM.

Accordingly, a technical problem to be achieved by the present invention is to provide a semiconductor memory device and a refresh method thereof for reducing self refresh power consumption.

A semiconductor memory device according to the present invention comprises a memory cell array comprising a plurality of word lines; And a self refresh controller for controlling a self refresh operation of the memory cell array, wherein the plurality of word lines includes at least one dummy word line, wherein the at least one dummy word line is selected from among the plurality of word lines. Refresh information regarding a word line to be refreshed may be stored, and the self-refresh operation of some of the plurality of word lines may be selectively performed using the refresh information.

The self refresh controller may further include a self refresh address generation block configured to generate a refresh address; And a self refresh period determination block configured to receive the refresh address and determine a self refresh period.

The semiconductor memory device may further include a buffer register configured to receive and store the refresh information.

The refresh information may correspond to bitmapped refresh information.

The self refresh period determination block may determine the self refresh period by using the bitmapped refresh information.

The at least one dummy word line may be positioned at the outermost of the plurality of word lines.

A memory module according to the present invention comprises: the semiconductor memory device; And a memory controller for controlling the semiconductor memory device.

In addition, the electronic system according to the present invention includes the memory module; And a storage device that stores system OS and applications.

In addition, the storage device may include a mass storage device or a nonvolatile memory.

In addition, the mass storage device may include an HDD, SSD, and NAS.

In addition, the nonvolatile memory may include flash memory, PRAM, and MRAM.

According to another aspect of the present invention, there is provided a method of refreshing a semiconductor memory device, the method including: bitmaping refresh information that is information on whether to perform refresh for each word line; Storing the bitmapped refresh information in at least one dummy word line; And performing a self refresh by comparing a row address with the refresh information during the self refresh operation.

In addition, the refresh information may include information about word lines that require refresh and information about word lines that do not require refresh.

The performing of the self refresh may include performing a self refresh of the word line when the row address and the information about the word lines requiring the refresh match as a result of the comparison.

The performing of the self refresh may include skipping the self refresh of the word line when the row address and the information about the word lines that do not need the refresh match as a result of the comparison.

In addition, the performing of the self refresh may include determining a self refresh cycle.

According to the semiconductor memory device and the refresh method according to an embodiment of the present invention it is possible to reduce the self refresh power, there is an effect that the DRAM can be employed in mobile electronic products such as smart phones.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.
1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating in detail the self-refresh controller shown in FIG. 1.
3 is a diagram illustrating an embodiment of a dummy word line that stores bitmapped information of the semiconductor memory device.
4A is a diagram for describing a self refresh cycle according to a comparative example of the present invention.
4B is a diagram for describing a self refresh cycle according to an embodiment of the present invention.
5 is a flowchart illustrating a memory refresh method according to an embodiment of the present invention.
6 is a block diagram illustrating a memory module according to an example embodiment.
7 illustrates an electronic system according to an embodiment of the present invention.

Specific structural or functional descriptions of the embodiments according to the inventive concept disclosed herein are provided for the purpose of describing the embodiments according to the inventive concept only. It may be embodied in various forms and is not limited to the embodiments described herein.

Embodiments according to the inventive concept may be variously modified and have various forms, so embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments in accordance with the concept of the invention to the specific forms disclosed, it includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor memory device 100 may include a memory cell array 110, a row decoder 120, a sense amplifier 130, a column decoder 140, a self refresh controller 150, and a command decoder 160. And a mode register set / extended mode register set (MRS / EMRS) circuit 170, an address buffer 180, a data input / output circuit 190, and a buffer register 195. A schematic operation of the semiconductor memory device 100 is as follows.

The memory cell array 110 is a data storage location where a large number of memory cells are arranged in a row direction and a column direction. The sense amplifier 130 senses and amplifies the data of the memory cell and also stores the data in the memory cell. The memory cell array 110 of FIG. 1 may have four memory banks (eg, first to fourth memory banks), but is not limited thereto.

The semiconductor memory device 100 may bitmap the refresh information, which is information on whether to refresh the word line for each word line, in consideration of the word line to be refreshed and the word line not to be refreshed. . The bitmapped refresh information may be stored in the dummy word line 112. In this case, the dummy word line 112 may be included in the memory cell array 110.

Each of the first to fourth memory banks may perform a refresh operation for each word line based on the bitmapped refresh information. For example, although the refresh operation is not performed on the first and second word lines, the refresh operation may be performed on the third word line.

The data DQ input through the data input / output circuit 190 is written in the memory cell array 110 based on the address signal ADD and read out from the memory cell array 110 based on the address signal ADD. The data DQ is output to the outside through the data input / output circuit 190.

The address signal ADD is input to the address buffer 180 to designate a memory cell in which data is to be written or read. The address buffer 180 temporarily stores an address signal ADD input from the outside.

The buffer register 195 receives and stores the bitmapped refresh information through the data input / output circuit 190. The buffer register 195 may output the bitmapped refresh information to the row decoder 120 or the self refresh controller 150.

The row decoder 120 decodes a row address of the address signal ADD output from the address buffer 180 to designate a word line connected to a memory cell to which data is input or output.

That is, the row decoder 120 decodes the row address output from the address buffer 180 to enable the corresponding word line in the data write or read mode. In addition, in the self refresh mode, the row decoder 120 may refresh the corresponding word line based on the row address generated from the self refresh controller 150 and the bitmapped refresh information.

The column decoder 140 decodes a column address of the address signal ADD output from the address buffer 180 to designate a bit line connected to a memory cell to which data is input or output.

The memory cell array 110 outputs data from or writes data to memory cells specified by row and column addresses.

The command decoder 160 receives a command signal CMD applied from the outside and decodes the signals to internally generate a decoded command signal (eg, a self refresh entering command or a self refresh ending command).

The self refresh controller 150 receives the decoded command signal from the command decoder 160 and controls an operation of self refresh of the memory cell array 110. The self-refresh controller 150 will be described in more detail later with reference to FIG. 2.

The MRS / EMRS circuit 170 sets an internal mode register in response to an MRS / EMRS command and an address signal ADD for specifying an operation mode of the semiconductor memory device 100.

In addition, although not shown in FIG. 1, the semiconductor memory device 100 may include a clock circuit (not shown) for generating a clock signal and a power circuit (not shown) for receiving or supplying a power voltage applied from the outside to generate an internal voltage. ) May be further provided.

The self refresh controller 150 controls the self refresh operation of the semiconductor memory device 100 in response to a command output from the command decoder 160.

FIG. 2 is a diagram illustrating in detail the self-refresh controller shown in FIG. 1. Referring to FIG. 2, the self refresh controller 150 includes a self refresh period determination block 152, a row address counter 154, a self refresh address generation block 156, and a column address counter 158.

When the self refresh address generation block 156 receives the self refresh entry command from the command decoder 160, the self refresh address generation block 156 generates a refresh address and outputs the refresh address to the self refresh period determination block 152.

The self refresh period determination block 152 receives the refresh address and determines a self refresh period.

For example, the refresh period determination block 152 may include row address information incremented by a row address counter 154, and bitmapped refresh information of the buffer register 195 (or the bits stored in the dummy word line 112). The mapped refresh information) may be compared to determine the self refresh period for each word line.

Therefore, when the self refresh period is determined for each word line, a word line to be refreshed among the word lines may be determined.

More specifically, since the bitmapped refresh information includes information about a word line that needs to be refreshed or information about a word line that does not require refresh, refreshing may be performed on only word lines that require refresh according to the comparison.

The row address counter 154 outputs a row address including the word line information to be refreshed to the row decoder 120.

The column address counter 158 may increase the column address and input / output the bitmapped refresh information stored in the dummy word line 112 to the buffer register 195.

3 is a diagram illustrating an embodiment of a dummy word line that stores bitmapped information of the semiconductor memory device. Referring to FIG. 3, the dummy word line 112 illustrated in FIG. 3 may correspond to a conceptual block for explaining an embodiment of the present invention.

The dummy word line 112 may correspond to a kind of word line included in the memory cell array 110 and may be located at the outermost part of the word line array, but is not limited thereto.

The dummy word line 112 corresponds to an area for storing a flag indicating whether there is a need for self refresh for each word line. For example, when the flag corresponds to the first flag FL_1, that is, when the flag corresponds to 1, it may mean a word line to perform self refresh, and when the flag corresponds to the second flag FL_2, that is, the flag. If 0 corresponds to a word line, the self-refresh should not be performed.

However, the scope of the present invention is not limited thereto. For example, two or more flags (eg, 10 or 100) may correspond to a criterion for determining whether to perform self refresh of one page (eg, one or more word lines).

4A is a diagram illustrating a self refresh cycle according to a comparative example of the present invention, and FIG. 4B is a diagram illustrating a self refresh cycle according to an embodiment of the present invention.

Referring to FIGS. 1, 4A, and 4B, the buffer register 195 of FIG. 1 includes a plurality of blocks 211 through 21n having the same shape as that of FIGS. 4A and 4B, for example. At 211 to 21n, a flag (eg, 0 or 1) indicating whether there is a need for self refresh may be stored.

A first period T_1, which is a self refresh period according to the comparative example of FIG. 4A, is a period in which all word lines are refreshed regardless of information on word lines that require refresh or information about word lines that do not require refresh. Corresponding.

In this case, the plurality of blocks 211 through 21n may include blocks 213 and 215 including information about a word line requiring refresh, and blocks 211 and 212 including information about a word line not requiring refresh. , 214, and 216 to 21n).

Unlike FIG. 4A, the self refresh period according to the exemplary embodiment of FIG. 4B may correspond to the sum of the second period T_2 and the third period T_3. The second period T_2 and the third period T_3 correspond to the time taken to perform the refresh of each word line corresponding to each of the blocks 213 and 215 including information on the word line to be refreshed. do.

Each word line corresponding to each of the blocks 211, 212, 214, and 216 to 21n including the information about the word line that does not need refreshing may be refreshed if it corresponds to a word line requiring refreshing next time. Can be.

For example, if the word lines corresponding to each of the blocks 211, 212, 214, and 216 to 21n all need to be refreshed next time, the word corresponding to the successive blocks 211 and 212 and 216 to 21n. The lines are refreshed all at once. Therefore, in the case of FIG. 4B, the next self-refresh cycle according to an embodiment of the present invention may correspond to the sum of the fourth period T_4, the fifth period T_5, and the sixth period T_6. have.

5 is a flowchart illustrating a memory refresh method according to an embodiment of the present invention. The memory refresh method may be performed by the semiconductor memory device 100 shown in FIG. 1.

Referring to FIG. 5, the semiconductor memory device 100 bitmaps the refresh information, which is information on whether to perform a refresh for each word line (S110). The refresh information includes information about word lines that require refresh and information about word lines that do not require refresh.

The semiconductor memory device 100 stores the bitmapped refresh information in a dummy word line included in the memory cell array 110 of the semiconductor memory device 100 (S120).

The semiconductor memory device 100 compares the row address and the refresh information with each other in the self refresh operation (S130). When the comparison result is the first result, that is, the row address and the refresh information, for example, a word requiring refresh. When the information on the lines match, refresh is performed (S140).

When the comparison result is the second result, that is, when the refresh information, for example, information about word lines that do not need refresh is matched with the corresponding row address, the refresh skip S150 is performed.

Thus, according to the memory refresh method according to the embodiment of the present invention, since only the word lines requiring refresh can be performed, there is an advantage in that the refresh power can be reduced. In addition, according to the memory refresh method according to an embodiment of the present invention, the memory refresh period can be extended for each word line according to the characteristics of the word line, thereby reducing the refresh power.

6 is a block diagram illustrating a memory module 500 according to an embodiment of the present invention. The memory module 500 includes a semiconductor memory device 100 and a memory controller 510 for controlling the semiconductor memory device 100 according to an embodiment of the present invention.

Since the configuration and operation of the semiconductor memory device 100 are the same as or similar to those of the semiconductor memory device 100 described with reference to FIGS. 1 to 5, a detailed description thereof will be omitted.

The memory device 100 and / or the memory controller 510 according to an embodiment of the present invention may be mounted using various types of packages. For example, a memory device and / or a memory controller according to an embodiment of the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) , Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) ), Such as Wafer-Level Processed Stack Package (WSP).

The memory device 100 and the memory controller 510 may constitute a memory card. In this case, the memory controller 510 may include a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect-express (PCI-E), a serial ATA (SATA), a parallel ATA (PATA), and a small SCSI (SCATA). It may be configured to communicate with an external (eg, host) through one of a variety of interface protocols such as a computer system interface (ESI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), and the like.

7 illustrates an electronic system according to an embodiment of the present invention. Referring to FIG. 7, the electronic system 700 includes a memory module 500, a nonvolatile memory (NVM, 710), a mass storage device 720, a CPU 730, and an I / O interface 740. These may be connected to each other via a bus 800.

The nonvolatile memory 710 may include a flash memory, a PRAM, and an MRAM, and the mass storage device 720 may include an SSD, an HDD, a NAS, and the like. The nonvolatile memory 710 or the mass storage device 720 may store files of a system OS and other applications.

The I / O interface 740 may be directly connected to a network port or network for connecting to the network.

During operation of the electronic system 700, the CPU 730 may control the memory module 500, thereby allowing the semiconductor memory device 100 to refresh only word lines that require refresh.

Here, certain components in the electronic system 700 may be changed. For example, the CPU 730 may be any one of various types of CPU, and the semiconductor memory device 100 may be any memory of various types of memory including DRAM or other types of memory requiring refresh. Can be. Further, embodiments of the electronic system 700 are also not limited to the devices shown in FIG. 7 and may include additional devices.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. (E.g., transmission over the Internet).

The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. And functional programs, codes and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention belongs.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Semiconductor memory device 100
Memory cell array 110
Dummy Word Line (112)
Row decoder 120
Sense Amplifier (130)
Column decoder 140
Self Refresh Controller (150)
Self Refresh Cycle Decision Block (152)
Row address counter 154
Self Refresh Address Generation Block (156)
Column address counter 158
Command decoder 160
MRS / EMRS Circuit (170)
Address buffer (180)
Data input / output circuitry 190
Buffer registers (195)

Claims (10)

A memory cell array including a plurality of word lines; And
A self refresh controller for controlling a self refresh operation of the memory cell array;
The plurality of word lines includes at least one dummy word line,
The at least one dummy word line stores refresh information regarding a word line to be refreshed among the plurality of word lines,
And performing the self refresh operation on at least one word line of the plurality of word lines using the refresh information. The method of claim 1, wherein the self-refresh controller
A self refresh address generation block for generating a refresh address; And
And a self refresh period determination block configured to receive the refresh address and determine a self refresh period. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises:
And a buffer register configured to receive and store the refresh information. The method of claim 1,
And the refresh information corresponds to information on whether or not to perform refresh for each word line. The method of claim 4, wherein the self refresh period determination block is
And a self refresh cycle is determined using the bitmapped refresh information. The method of claim 1,
And the at least one dummy word line is located at the outermost of the plurality of word lines. The semiconductor memory device according to any one of claims 1 to 6; And
And a memory controller for controlling the semiconductor memory device. A memory module of claim 7; And
An electronic system comprising a storage device for storing a system OS and an application. The method of claim 8,
The storage device comprises a mass storage device or a nonvolatile memory. 10. The method of claim 9,
The mass storage device comprises an HDD, SSD and NAS.

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