KR20120047359A

KR20120047359A - Circuit for transferring data

Info

Publication number: KR20120047359A
Application number: KR1020100108309A
Authority: KR
Inventors: 박상수
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2010-11-02
Filing date: 2010-11-02
Publication date: 2012-05-14

Abstract

PURPOSE: A data transmitting circuit is provided to transmit data at high speed by using a DDR(Double Data Rate) mode. CONSTITUTION: A reference clock generating unit has data output timing in rise transition timing and fall transition timing and generates a plurality of reference clocks with phase difference. A frequency divider(123) generates a transmission clock with a frequency corresponding to a phase difference between the plurality of reference clocks. A data output unit outputs data in a transition timing of a transmission clock.

Description

Data transmission circuit {CIRCUIT FOR TRANSFERRING DATA}

The present invention relates to a data transmission circuit, and more particularly, to a data transmission circuit capable of transmitting data at high speed using a double data rate (DDR) method.

Nowadays, the role of high speed serial communication has become very important in solving the problems such as the improvement of data transmission speed between electronic devices or electromagnetic interference (EMI). Applications of high speed serial communication are increasing in computers, display devices, mobile devices, or image sensors. Accordingly, new standards and standards have emerged and are being used in various ways.

Methods for transmitting / receiving data between devices can be broadly divided into wired communication and wireless communication, and wired communication can be classified into various types according to their media. Data can be divided into parallel and serial formats, depending on whether you send multiple bits at once using multiple lines or one bit at a time using one line.

In the past, the required data rate was not high and the operating margin of the electronic equipment was also large. Therefore, many parallel methods were used. However, as the required data transfer rate increases, power consumption, EMI problems, Due to the miniaturization of devices, serial transmission methods are widely used.

There is also a single data rate (SDR) and double data rate (DDR) in the serial method. In the case of DDR, data is caught on both the rising edge and the falling edge of the clock signal. In both methods, the accuracy of the reference clock is very important. In particular, it is important to keep the reference clock duty constant.

However, when data is transmitted using the DDR method, the duty ratio may be modified while the clock signal used in the system passes through various logic blocks and signal lines. When the duty ratio of the reference clock is modified, it becomes difficult to reliably transmit data at high speed using the DDR method.

The present invention provides a data transmission circuit that transmits data at high speed by using a DDR method and has excellent reliability for data transmission.

The present invention includes a reference clock generator for generating a plurality of reference clocks having a data output timing at each rising transition timing or falling transition timing and having a phase difference from each other; A frequency multiplier for generating a transmission clock having a frequency corresponding to a phase difference between the plurality of reference clocks; And a data output unit configured to output data at the transition timing of the transmission clock.

According to the present invention, in a circuit for continuously outputting data on the basis of transition points of a plurality of reference clocks, it is possible to transmit data in a state where the duty of the clock signal for determining the output timing of the data is more stabilized.

1 is a block diagram showing a data transmission circuit for explaining the present invention.
2 is a block diagram showing a data transmission circuit according to an embodiment of the present invention.
3 is a block diagram showing a transmission clock generating unit of the data transmission circuit shown in FIG.
FIG. 4A is a circuit diagram showing a first synchronization unit shown in FIG.
4B is a circuit diagram showing a second synchronization unit shown in FIG.
5 and 6 are circuit diagrams showing the frequency multiplier shown in FIG.
FIG. 7 is a waveform diagram showing the operation of the transmission clock generator shown in FIG. 4; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

1 is a block diagram showing a data transmission circuit for explaining the present invention. In particular, it is a data transmission circuit for DDR data transmission.

Referring to FIG. 1, the data transmission circuit includes a data transmitter 10 and a data receiver 20. The data transmitter 10 includes a first clock generator 11, a second clock generator 12, and a data output unit 13.

The data output from the data output unit 13 is aligned with the edge of the clock signal CLK1 output from the first clock generator 11 and the edge of the clock signal CLK2 output from the second clock generator 12. It is transmitted to the data receiving unit 20. In this case, it is assumed that the two clock signals CLK1 and CLK2 have a constant phase difference, but have a 90 degree phase difference. When data is transmitted and received in a DDR manner using two clock signals having a phase difference of 90 degrees, an error may occur while data is transferred from the data transmitter 10 to the data receiver 20. This is because the duty ratio of each clock output from the first clock generator 11 and the second clock generator 12 may be changed, or the timing may not match between the two clocks.

In order to solve this problem, in the present invention, in order to increase the duty ratio accuracy of the clock in the DDR method, a clock signal having a frequency twice as high as the reference frequency is generated, and the clock transmission is performed after correcting the duty ratio of the generated clock signal. A data transmission circuit for use in the present invention is proposed.

2 is a block diagram showing a data transmission circuit according to an embodiment of the present invention.

Referring to FIG. 2, the data transmission circuit according to the present embodiment includes a data transmitter 100 and a data receiver 200. The data transmitter 100 outputs data along with a clock, and the data receiver 300 receives data provided from the data transmitter 100 together with a clock.

The data transmitter 100 includes a reference clock generator 110, a transmission clock generator 120, and a data outputter 130. The reference clock generator 110 generates four reference clocks CLK0, CLK90, CLK180, and CLK270 that are shifted by 90 degrees from each other. The transmission clock generator 120 generates a first transmission clock and a second transmission clock having twice the frequency of the reference clock by using the four reference clocks generated by the reference clock generator 110. The first transmission clock and the second transmission clock are clocks having a phase opposite to each other by 180 degrees. Data output from the data output unit 130 is output in synchronization with the rising edge of the first transmission clock and the rising edge of the second transmission clock.

FIG. 3 is a block diagram illustrating a transmission clock generator of the data transmitter of FIG. 2.

Referring to FIG. 3, the transmission clock generator 120 includes a first synchronizer 121, a second synchronizer 122, a frequency multiplier 123, and a third synchronizer 124. .

The first synchronizer unit 121 corrects and outputs the duty ratios of the first reference clock CLK0 and the third reference clock CLK180 that are input. The second synchronizing unit 122 corrects and outputs the duty ratios of the second reference clock CLK90 and the fourth reference clock CLK270.

The frequency multiplier 123 receives the first to fourth reference clocks CLK0, CLK90, CLK180, and CLK270 to generate a first transmission clock CLK2X and a second transmission clock CLK2X_180 having a clock frequency of two multiples. . The first transmission clock CLK2X and the second transmission clock CLK2X_180 are clocks whose phases are opposite to each other by 180 degrees. The third synchronizing unit 124 receives the first transmission clock CLK2X and the second transmission clock CLK2X_180, corrects the duty ratio, and outputs the corrected duty ratio.

FIG. 4A is a circuit diagram illustrating a first synchronization unit shown in FIG. 3. FIG. 4B is a circuit diagram illustrating a second synchronization unit shown in FIG. 3.

Referring to FIG. 4A, the first synchronizer 121 includes six inverters I1 to I6. The two inverters I5 and I6 have a latch structure in which each input terminal is connected to each other's output terminal, and the two inverters I1 and I2 receive and transfer the first reference clock CLK0 and the two inverters I3 and I4 receive and transmit a third reference clock CLK180.

While the inverters I1, I2, I3, I4 transfer the first and third reference clocks CLK0, CLK180, respectively, the two reference clocks CLK0, The duty ratio of CLK180 is corrected.

As shown in FIG. 4B, the second synchronization unit 122 also has the same configuration as the first synchronization unit 121 and includes six inverters I7 to I10.

5 and 6 are circuit diagrams showing the frequency multiplier shown in FIG.

The frequency multiplier 123 shown in FIG. 5 is a circuit that receives the first through fourth reference clocks CLK0, CLK90, CLK180, and CLK270 to generate the first transmission clock CLK2X. 6 is a circuit for receiving the first to fourth reference clocks CLK0, CLK90, CLK180, and CLK270 to generate a second transmission clock CLK2X_180.

The frequency multiplier 123 includes eight MOS transistors T1 to T8 and MOS transistors T9 to T16, respectively, and as illustrated, the first to fourth reference clocks CLK0, CLK90, CLK180, and CLK270, respectively. ), And generates a first transmission clock CLK2X and a second transmission clock CLK2X_180.

FIG. 7 is a waveform diagram illustrating an operation of the transmission clock generator shown in FIG. 3.

As shown in FIG. 7, first, the reference clock generator 110 generates four reference clocks CLK0, CLK90, CLK180, and CLK270 and provides them to the transmission clock generator 120.

The first synchronization unit 121 of the transmission clock generator 120 corrects and outputs the duty ratios of the first and third reference clocks CLK0 and CLK180, and the second synchronization unit 122 outputs the second and second synchronization units. The duty of the fourth reference clocks CLK90 and CLK270 is corrected and output.

Subsequently, the frequency multiplier 123 receives the first to fourth reference clocks CLK0, CLK90, CLK180, and CLK270, and has a first transmission clock CLK2X and a second transmission clock having a frequency twice that of the reference clock. CLK2X_180). The third synchronizing unit 124 corrects and outputs the duty ratios of the first transmission clock CLK2X and the second transmission clock CLK2X_180. The data output unit 130 of the data transmission unit 100 outputs data to the rising edges of the first transmission clock CLK2X and the second transmission clock CLK2X_180.

As described so far, the data transmission circuits according to the present embodiment are 180 degrees out of phase with two times the frequency of the reference clock in order to increase the duty ratio accuracy of the reference clock when transmitting data serially in the DDR system. A method of generating first and second transmission clocks with and outputting data to the rising edge of the first transmission clock and the rising edge of the second transmission clock is used. In addition, a third sinking unit that provides duty between the first and second transmission clocks is provided so that the duty of the first and second transmission clocks as the reference of the data output can be maintained in a desired state.

Here, although the first and second transmission clocks are generated to output data for each rising edge, one transmission clock may be generated and the data may be output to the rising and falling edges of the generated transmission clock.

In the conventional method, the data output unit outputs data using two clock signals having a 90 degree phase difference provided by the clock provider. Therefore, when the phase of the clock signal is changed, the output timing or transfer timing of the data is changed, and an error may occur.

However, the present invention generates a transmission clock having twice the frequency of the reference clock signal without using two clock signals having a phase difference of 90 degrees, and the rising / falling edge or phase of the generated transmission clock is 180 degrees. The difference is that data is transmitted to the rising edge of the two transmission clocks, which increases the accuracy of the data transmission timing.

In addition, through the present invention, skew between the clock signal and the data can be reduced. This is because the duty ratio of the transmission clock can be kept constant, and the output timing of data is determined at the time of transition of one transmission clock. Skew means that the transmission time is different because the transmission path of the clock signal and the transmission path of the data signal do not coincide.

When data is serially transmitted using the data transmission circuit according to the present embodiment, since the transmission clock which is a reference for the output timing of the data is stabilized and provided, data can be provided more reliably at high speed. . In particular, it is possible to apply the data transmission circuit according to the present embodiment to an integrated circuit using the MIPI protocol. The Mobile Industry Processor Interface Alliance (MIPI) is a coalition of companies aiming to standardize portable device interfaces, covering many topics including cameras, displays, audio, and signal buses.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims

A reference clock generator having a data output timing at each rising transition timing or a falling transition timing, and generating a plurality of reference clocks having a phase difference from each other;
A frequency multiplier for generating a transmission clock having a frequency corresponding to a phase difference between the plurality of reference clocks; And
Data output unit for outputting data at the transition timing of the transmission clock
Data transmission circuit comprising a.

The method of claim 1,
And the plurality of reference clocks are first to fourth reference clocks each having a phase of 0, 90, 180, and 270 degrees.

The method of claim 2,
And said transmission clock has a frequency twice that of said reference clock.

The method of claim 3, wherein
The frequency multiplier
A first frequency multiplier circuit for receiving the first reference clock of 0 degree phase and the third reference clock of 180 degree phase to generate a first transmission clock; And
A second frequency multiplier circuit configured to receive the first reference clock in the 90 degree phase and the fourth reference clock in the 270 degree phase to generate a second transmission clock;
And the data output unit outputs data at the time of transition of the first transmission clock and the second transmission clock.

The method of claim 4, wherein
And a first synchronizing unit for correcting the duty ratio of the first reference clock in the zero degree phase and the third reference clock in the 180 degree phase to transmit the corrected ratio to the frequency multiplier,
The first synchronization unit
First and second inverters connected in series to receive and transmit the first reference clock;
Third and fourth inverters connected in series to receive and transmit the third reference clock;
A fifth inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an output terminal of the third inverter; And
And a sixth inverter having an input terminal connected to an output terminal of the third inverter and an output terminal connected to an output terminal of the first inverter.

The method of claim 5, wherein
A second synchronization unit for correcting the duty ratio of the second reference clock of 90 degrees phase and the fourth reference clock of 270 degrees phase is further provided.
The second synchronization unit
Seventh and eighth inverters connected in series to receive and transmit the second reference clock;
Ninth and tenth inverters connected in series to receive and transmit the fourth reference clock;
An eleventh inverter having an input terminal connected to an output terminal of the seventh inverter and an output terminal connected to an output terminal of the ninth inverter; And
And a twelfth inverter having an input terminal connected to an output terminal of the ninth inverter and an output terminal coupled to an output terminal of the seventh inverter.

The method of claim 2,
The frequency multiplier
A first PMOS transistor configured to receive the fourth reference clock as a gate;
A second PMOS transistor which receives the first reference clock as a gate and is connected in series with the first PMOS transistor;
A third PMOS transistor configured to receive the second reference clock as a gate;
A fourth PMOS transistor which receives the third reference clock as a gate and is connected in series with the third PMOS transistor;
A first NMOS transistor receiving the fourth reference clock as a gate;
A second NMOS transistor receiving the first reference clock as a gate and connected in series with the fourth NMOS transistor;
A third NMOS transistor configured to receive the second reference clock as a gate; And
A fourth NMOS transistor which receives the third reference clock as a gate and is connected in series with the third NMOS transistor,
The first and third PMOS transistors receive a power supply voltage to one side, and the second and fourth NMOS transistors receive a ground voltage to one side, and the second and fourth PMOS transistors and the first and third PMOS transistors. And providing the transmission clock through a common node of a third NMOS transistor.

The method of claim 4, wherein
And a synchronizing unit for correcting the duty ratio of the first transmission clock and the third transmission clock.
The synchronization unit
First and second inverters connected in series to receive and transmit the first transmission clock;
Third and fourth inverters connected in series to receive and transmit the second transmission clock;
A fifth inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an output terminal of the third inverter; And
And a sixth inverter having an input terminal connected to an output terminal of the third inverter and an output terminal connected to an output terminal of the first inverter.