KR20120045397A - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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KR20120045397A
KR20120045397A KR1020100106911A KR20100106911A KR20120045397A KR 20120045397 A KR20120045397 A KR 20120045397A KR 1020100106911 A KR1020100106911 A KR 1020100106911A KR 20100106911 A KR20100106911 A KR 20100106911A KR 20120045397 A KR20120045397 A KR 20120045397A
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gate electrode
type
active region
isolation layer
gate
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KR1020100106911A
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Korean (ko)
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김호웅
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에스케이하이닉스 주식회사
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Publication of KR20120045397A publication Critical patent/KR20120045397A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent the HEIP phenomenon without using a gate tab, the present invention is a substrate for which the active region is defined by an isolation layer; And a gate electrode formed on the substrate and crossing the device isolation layer and the active region at the same time, wherein the gate electrode alternates between the first gate electrode and the second gate electrode having complementary conductivity types in the channel width direction. The second gate electrode has a structure disposed in the semiconductor device, and the second gate electrode is disposed at a boundary region where the device isolation layer and the active region are in contact. By disposing the second gate electrode having a conductivity type complementary to the one gate electrode, there is an effect that the HEIP phenomenon can be prevented without using the gate tab.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a semiconductor device capable of preventing a hot electron induced punchthrough (HEIP) phenomenon and a manufacturing method thereof.

Recently, as the degree of integration of semiconductor devices increases, a problem arises in that the operation characteristics of the transistors are rapidly deteriorated due to a hot electron induced punchthrough (HEIP) phenomenon. The HEIP phenomenon is a phenomenon in which the effective channel length decreases because channels are formed at both ends in the channel width direction in the transistor off state, which increases the leakage current of the transistor and decreases the breakdown voltage (BV). Cause. In order to solve the problems caused by the above-described HEIP phenomenon, a method of compensating the effective channel length reduced by the HEIP phenomenon by introducing a gate tap has been introduced.

1A to 1C show a semiconductor device according to the prior art, FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along the line II ′ shown in FIG. 1A, and FIG. 1C is shown in FIG. 1A. A cross-sectional view taken along the line II-II '.

1A to 1C, the active region 13 is defined by the device isolation layer 12 formed on the substrate 11, and the active region 13 is doped with impurities for a well. A gate 17 having a structure in which the device isolation layer 12 and the active region 13 are simultaneously crossed on the substrate 11, and the gate insulating layer 14, the gate electrode 15, and the gate hard mask layer 16 are sequentially stacked. ) Is formed, and the gate tab A is disposed at a boundary region where the device isolation layer 12 and the active region 13 contact each other. The junction region 18 is formed in the active region 13 at both sides of the gate 17.

In the semiconductor device of the related art having the above-described structure, the gate W having the width W2 of the gate 17 located at the edge of the active region 13 in contact with the device isolation film 12 is located at the center of the active region 13. (17) The gate taps A are formed in such a manner that they are larger than the width W1. As a result, the length L2 of the channel formed at the edge of the active region 13 in contact with the device isolation film 12 where the HEIP phenomenon occurs is longer than the length L1 of the channel formed at the center, thereby alleviating the HEIP phenomenon. You can.

However, since the length of the channel decreases as the degree of integration of the semiconductor device increases, the length of the gate tap A must also be increased to compensate for the decrease in the channel length. In this case, since the size (or area) of the active region 13 must be increased to maintain a constant distance between the gates 17 in a region in which transistors requiring the gate taps A are dense, the net die ( net die) increases in size. As a result, it is difficult to improve the integration degree of the semiconductor device, and as the integration degree increases, it is difficult to secure the characteristics of the transistor.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can prevent the HEIP phenomenon without using a gate tab.

According to an aspect of the present invention, there is provided a substrate including an active region defined by an isolation layer; And a gate electrode formed on the substrate and crossing the device isolation layer and the active region at the same time, wherein the gate electrode alternates between the first gate electrode and the second gate electrode having complementary conductivity types in the channel width direction. The semiconductor device may have a structure in which the second gate electrode is disposed at a boundary region where the device isolation layer and the active region are in contact with each other.

In addition, the semiconductor device of the present invention may further include a junction region formed in the active region on both sides of the gate electrode, and the junction region may have the same conductivity type as the first gate electrode.

In addition, the semiconductor device of the present invention may further include a well formed in the substrate including the active region, and the well may have the same conductivity type as the second gate electrode.

According to another aspect of the present invention, there is provided a device isolation layer that defines an active region on a substrate; And forming a gate electrode crossing the device isolation layer and the active region at the same time on the substrate, wherein the gate electrode includes a first gate electrode and a second gate electrode having complementary conductivity types. The second gate electrode is formed in an alternately arranged structure, and the second gate electrode is formed at a boundary region where the device isolation layer and the active region are in contact with each other.

The semiconductor device manufacturing method may further include forming a junction region at both sides of the gate electrode in the active region, and the junction region may be formed to have the same conductivity type as the first gate electrode.

In addition, the method of manufacturing a semiconductor device of the present invention further includes forming a well by implanting impurities into the substrate before forming the device isolation layer, wherein the well has the same conductivity type as the second gate electrode. Can be formed.

The forming of the gate electrode may include forming a gate conductive film doped with an impurity of a first conductivity type on the substrate; Forming a photoresist pattern on the gate conductive layer, the photoresist pattern having an opening for opening a boundary region between the device isolation layer and the active region; Performing counter doping by ion implanting impurities of the second conductive type in the gate conductive layer using the photoresist pattern as an injection barrier; Removing the photoresist pattern; And selectively etching the gate conductive layer.

In accordance with the above-described problem solving means, the present invention provides a HEIP without using a gate tab by arranging a second gate electrode having a conductivity type complementary to the first gate electrode at a boundary region where the device isolation layer and the active region are in contact with each other. There is an effect that can prevent the phenomenon.

1A to 1C show a semiconductor device according to the prior art.
2A to 2D illustrate a semiconductor device according to an embodiment of the present invention.
3A to 3C illustrate band diagrams between a gate electrode, a gate insulating film, and a substrate in a semiconductor device according to an embodiment of the present invention.
4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention to be described later provides a semiconductor device and a method of manufacturing the same that can prevent a hot electron induced punchthrough (HEIP) phenomenon without using a gate tap. In the HEIP phenomenon, charge is trapped on the surface of the device isolation layer (or inside) of the device isolation layer at the boundary between the active region and the device isolation layer, and the charge trapped on the device isolation layer even when no bias is applied to the gate (that is, off state). This means that the effective channel length decreases as the channel is formed. In other words, the HEIP phenomenon is a phenomenon in which the threshold voltage in the active region overlapping the gate and the boundary region of the device isolation layer is lower than the predetermined threshold voltage by the charge trapped in the device isolation layer.

The gate tap according to the related art is a method of compensating for the effective channel length reduced by the HEIP phenomenon by increasing the channel length of the region where the HEIP phenomenon occurs (that is, the boundary region where the device isolation layer overlaps the gate and the active region). HEIP was alleviated. That is, the HEIP phenomenon is alleviated by increasing the channel length of the region where the HEIP phenomenon occurs and increasing the threshold voltage of the region above the preset threshold voltage. On the contrary, the present invention described below adjusts the conductivity type of the gate electrode so that the boundary region between the device isolation layer and the active region has a threshold voltage larger than the preset threshold voltage in order to prevent the HEIP phenomenon without using the gate tab. It is thought.

2A to 2D are diagrams illustrating a semiconductor device according to an embodiment of the present invention. FIG. 2A is a plan view, FIG. 2B is a cross-sectional view taken along the line II ′ shown in FIG. 2A, and FIG. 2C is a view. FIG. 2D is a cross-sectional view taken along the line II-II 'of FIG. 2A, and FIG. 2D is a cross-sectional view taken along the line III-III' of FIG. 2A. Hereinafter, an embodiment of the present invention will be described by illustrating a PMOS transistor.

As shown in FIGS. 2A to 2D, a semiconductor chip according to an embodiment of the present invention is formed on the substrate 31 and the substrate 31 on which the active region 33 is defined by the device isolation layer 32. A gate 37 having a structure in which the device isolation layer 32 and the active region 33 are simultaneously crossed and the gate insulating layer 34, the gate electrode 35, and the gate hard mask layer 36 are sequentially stacked. At this time, the gate electrode 35 has a structure in which the first gate electrode 35A and the second gate electrode 35B having complementary conductivity types are alternately arranged in the channel width direction, and the second gate electrode 35B is It is characterized in that it is disposed at the boundary area where the device isolation layer and the active region contact each other. Here, the first gate electrode 35A is of P type and the second gate electrode 35B is of N type.

In addition, the semiconductor device of the present invention further includes a junction region 38 formed in the active region 33 on both sides of the gate electrode 35. At this time, the junction region 38 has the same conductivity type as the first gate electrode 35A. That is, the conductivity type of the junction region 38 is P type.

In addition, the semiconductor device of the present invention further includes a well 39 formed in the substrate 31 including the active region 33. At this time, the well 39 has the same conductivity type as the second gate electrode 35B. That is, the conductivity type of the well 39 is N type.

The gate electrode 35 having the first gate electrode 35A and the second gate electrode 35B having complementary conductivity types in the channel width direction may be a silicon film, for example, a polysilicon film. Accordingly, the first gate electrode 35A may be a P-type polysilicon film, and the second gate electrode 35B may be an N-type polysilicon film. The first gate electrode 35A and the second gate electrode 35B have the same width W1 = W2. Therefore, the length L1 of the channel by the first gate electrode 35A and the length L2 of the channel by the second gate electrode 35B are also the same (L1 = L2).

In the gate electrode 35 in which the first gate electrode 35A and the second gate electrode 35B are alternately disposed, the second gate electrode 35B is positioned at least on the active region 33 in contact with the device isolation layer 32. Form. For example, as shown in the drawing, the second gate electrode 35B extends from the active region 33 to the device isolation layer 32, that is, the second gate electrode 35B has the active region 33 and the element. The separator 32 may be disposed to overlap all of the separators 32.

The first gate electrode 35A serves as a main gate electrode of the transistor, and the second gate electrode 35B serves as a sub gate electrode to prevent a HEIP phenomenon. At this time, even if the length L1 of the channel by the first gate electrode 35A and the channel length L2 by the second gate electrode 35B are the same (L1 = L2), the second gate electrode 35B is By having a conductivity type complementary to the first gate electrode 35A, the threshold voltage of the channel formed by the bias applied to the second gate electrode 35B is controlled by the bias applied to the first gate electrode 35A. It serves to increase the threshold voltage (that is, the predetermined threshold voltage) of the channel to be formed. Through this, the HEIP phenomenon can be prevented without using the gate tab, which will be described in more detail with reference to FIGS. 3A to 3C.

3A to 3C are diagrams illustrating band diagrams between a gate electrode, a gate insulating film, and a substrate in a semiconductor device according to an embodiment of the present invention. Hereinafter, a PMOS transistor will be described by way of example. Accordingly, the first gate electrode is referred to as 'P-type polysilicon', the second gate electrode is referred to as 'N-type polysilicon', and the well formed on the substrate including the active region is referred to as an 'N-type silicon substrate'. In the drawing, 'qΦ 1 ' is the work function of the P-type polysilicon, 'qΦ 2 ' is the work function of the N-type polysilicon, 'qΦs' is the work function of the N-type substrate,' Vc 'is the vacuum level,' Ec 'Is the conduction band,' Ev 'is the valence band,' Ei 'is the true Fermi level,' Ef 1 'is the Fermi level of P-type polysilicon,' Ef 2 'is the Fermi level of N-type polysilicon, and'Efs' is N It means the pep level of silicon substrate.

As shown in FIG. 3A, which shows a band diagram of the region A shown in FIG. 2B, the work function of the P-type polysilicon in the state where the P-type polysilicon and the N-type silicon substrate are not bonded is the work function of the N-type silicon substrate. It can be seen that the larger (qΦ 1 > qΦs).

In the thermal equilibrium state where the P-type polysilicon film and the N-type silicon substrate are bonded to each other and no bias is applied from the outside, the work function of the P-type polysilicon is larger than that of the N-type silicon substrate. It can be seen that the conductivity type of the substrate surface is converted into a neutral state or weakly P-type.

As shown in FIG. 3B, which shows a band diagram of the region B shown in FIG. 2C, the work function of the N-type polysilicon and the work function of the N-type silicon substrate in the state where the N-type polysilicon and the N-type silicon substrate are not bonded to each other. It can be seen that is almost similar (qΦ 2 s qΦs).

In the thermal equilibrium state where the N-type polysilicon film and the N-type silicon substrate are bonded to each other and the external bias is not applied, band banding does not occur because the work function of the N-type polysilicon and the N-type silicon substrate are similar. It can be seen that the band diagram of the N-type silicon substrate is flat.

Referring to FIG. 3C, in which the same bias (V <0, qV) is applied to the P-type polysilicon and the N-type polysilicon based on FIGS. 3A and 3B, the P-type polysilicon and the N-type silicon substrate are applied by the applied bias. It can be seen that the band banding is deepened between the conductive type on the surface of the N-type silicon substrate to convert to the P-type (ie, inversion) to form a channel.

On the contrary, since no band banding occurred in the thermal equilibrium state between the N-type polysilicon and the N-type silicon substrate, the surface of the N-type silicon substrate was applied even if the same bias applied to the P-type polysilicon was applied to the N-type polysilicon. The conductive type of is converted to P type and no channel is formed. In other words, the N-type polysilicon must be applied with a larger bias than that applied to the P-type polysilicon so that the surface of the N-type silicon substrate under the N-type polysilicon is converted to P-type (ie, inverted) to form a channel. You can see that.

Referring to FIGS. 3A to 3C, the HEIP phenomenon occurs because a channel is first formed by charge trapped in the device isolation layer at a boundary between the device isolation layer and the active region under the gate. Here, according to an embodiment of the present invention, the channel is formed only when a threshold voltage larger than a predetermined threshold voltage is applied by the second gate electrode (ie, N-type polysilicon) disposed in the region where the HEIP phenomenon occurs. Therefore, even if charge is trapped in the device isolation layer, it is possible to prevent the channel from being first formed at the boundary area between the device isolation layer and the active region under the gate. That is, the HEIP phenomenon can be prevented from occurring.

As described above, the present invention can prevent the HEIP phenomenon without using the gate tap. As a result, as the degree of integration of the semiconductor device increases, the characteristics of the semiconductor device may be prevented from being deteriorated, and the net die size may be reduced to improve the productivity of the semiconductor device.

4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Here, description will be made based on a process cross-sectional view taken along the line III-III 'shown in FIG. 2A, and a PMOS transistor will be described as an example.

As shown in FIG. 4A, impurities are implanted into the substrate 51 to form the wells 52. In this case, the well 52 may be formed by ion implanting N-type impurities into the substrate 51, and phosphorus (P), arsenic (As), antimony (Sb), or the like may be used as the N-type impurities.

Next, an isolation region 53 is formed on the substrate 51 to define the active region 54. The isolation layer 53 may be formed using a shallow trench isolation (STI) process, and the depth of the isolation layer 53 may be deeper or shallower than the depth of the well 52.

Next, a gate insulating film 55 is formed over the entire surface of the substrate 51. The gate insulating film 55 may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are stacked.

Next, a gate conductive film 56 doped with P-type impurities is formed on the gate insulating film 55. The gate conductive film 56 may be formed of a silicon film, for example, a polysilicon film. The gate conductive layer 56 doped with the P-type impurity forms the gate conductive layer 56 and simultaneously injects the P-type impurity or forms the P-type impurity after the gate conductive layer 56 is formed. It can be formed by ion implantation. In this case, boron (B) may be used as the P-type impurity.

As shown in FIG. 4B, a photosensitive film pattern 57 having an opening 57A that opens a boundary area where the device isolation layer 53 and the active region 54 contact each other is formed on the gate conductive film 56. In this case, the opening 57A of the photoresist pattern 57 is formed to expose at least the active region 54 in contact with the device isolation layer 53. For example, the device isolation layer 53 and the active region 54 in the boundary region where the device isolation layer 53 and the active region 54 contact each other may be formed.

Next, a counter-doping for ion implanting N-type impurities into the gate conductive film 56 is performed using the photosensitive film pattern 57 as an injection barrier to form an N-type impurity region in the gate conductive film 56. When the counter doping is completed, the gate conductive film 56 is composed of a P-type impurity region 56A doped with P-type impurities and an N-type impurity region 56B doped with N-type impurities.

As shown in FIG. 4C, after the photoresist layer pattern 57 is removed, the gate hard mask layer 58 is formed on the gate conductive layer 56. The gate hard mask film 58 may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are stacked.

Next, the gate hard mask layer 58, the gate conductive layer 56, and the gate insulating layer 55 are sequentially etched to include the gate electrode 59 simultaneously crossing the active region 54 and the device isolation layer 53. The gate 60 is formed. At this time, in the gate electrode 59, the first gate electrode 59A having a conductivity type of P type and the second gate electrode 59B having a conductivity type of N type are alternately arranged in the channel width direction, and the second gate electrode 59B is disposed. The device isolation layer 53 has a structure disposed at a boundary region where the device isolation layer 53 and the active region 54 contact each other.

Next, P-type impurities are implanted into the active regions 54 at both sides of the gate 60 to form a junction region (not shown).

The semiconductor device of the present invention formed through the above-described manufacturing method can prevent the HEIP phenomenon without using the gate tab. As a result, as the degree of integration of the semiconductor device increases, the characteristics of the semiconductor device may be prevented from being deteriorated, and the net die size may be reduced to improve the productivity of the semiconductor device.

In the above description, the PMOS transistor is illustrated as an example, and the conductivity of the first gate electrode and the junction region is P-type, and the conductivity of the second gate electrode and well is N-type. The technical idea of the present invention described above is equally applicable to NMOS transistors, where the conductivity type of the first gate electrode and the junction region is N type, and the conductivity type of the second gate electrode and well is P type.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

31 substrate 32 device isolation film
33: active region 34: gate insulating film
35 gate electrode 36 gate hard mask film
37 gate 38 junction area
39: Well

Claims (17)

A substrate in which an active region is defined by an isolation layer; And
A gate electrode formed on the substrate and crossing the device isolation layer and the active region at the same time;
The gate electrode has a structure in which a first gate electrode and a second gate electrode having complementary conductivity types are alternately arranged in a channel width direction, and the second gate electrode is disposed at a boundary region where the device isolation layer and the active region are in contact with each other. Arranged semiconductor device.
The method of claim 1,
A junction region formed at both sides of the gate electrode in the active region;
And the junction region has the same conductivity type as the first gate electrode.
The method of claim 1,
Further comprising a well formed in the substrate including the active region,
And the well has the same conductivity type as the second gate electrode.
The method of claim 1,
And the second gate electrode on at least the active region in contact with the device isolation layer.
The method of claim 4, wherein
And the second gate electrode extends to the device isolation layer in contact with the active region.
The method of claim 1,
And a threshold voltage of a channel by the second gate electrode is greater than a threshold voltage of the channel by the first gate electrode.
The method of claim 1,
The gate electrode is a line pattern, the semiconductor device having the same width as the first gate electrode and the second gate electrode.
The method of claim 1,
The conductive type of the first gate electrode is P type, and the conductive type of the second gate electrode is N type.
The method of claim 1,
The conductive type of the first gate electrode is N type, and the conductive type of the second gate electrode is P type.
Forming an isolation layer defining an active region on the substrate; And
Forming a gate electrode on the substrate to cross the device isolation layer and the active region at the same time;
The gate electrode may have a structure in which a first gate electrode and a second gate electrode having complementary conductivity types are alternately arranged in a channel width direction, and the second gate electrode is a boundary region where the device isolation layer and the active region are in contact with each other. Forming a semiconductor device.
The method of claim 10,
And forming a junction region at both sides of the gate electrode in the active region, wherein the junction region is formed to have the same conductivity type as the first gate electrode.
The method of claim 10,
Before forming the device isolation film
And forming a well by implanting impurities into the substrate, wherein the well is formed to have the same conductivity type as that of the second gate electrode.
The method of claim 10,
Forming the gate electrode,
Forming a gate conductive layer doped with an impurity of a first conductivity type on the substrate;
Forming a photoresist pattern on the gate conductive layer, the photoresist pattern having an opening for opening a boundary region between the device isolation layer and the active region;
Performing counter doping by ion implanting impurities of the second conductive type in the gate conductive layer using the photoresist pattern as an injection barrier;
Removing the photoresist pattern; And
Selectively etching the gate conductive layer
&Lt; / RTI &gt;
The method of claim 13,
And the opening opens the active region in contact with at least the device isolation layer.
The method of claim 14,
And the opening opens the device isolation layer and the active region at the same time.
The method of claim 13,
And the first conductive type is P type and the second conductive type is N type.
The method of claim 13,
And the first conductive type is N type, and the second conductive type is P type.
KR1020100106911A 2010-10-29 2010-10-29 Semiconductor device and method for fabricating the same KR20120045397A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10141400B2 (en) 2016-01-05 2018-11-27 Samsung Electronics Co., Ltd. Semiconductor devices including field effect transistors with dummy gates on isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10141400B2 (en) 2016-01-05 2018-11-27 Samsung Electronics Co., Ltd. Semiconductor devices including field effect transistors with dummy gates on isolation

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