KR20120030872A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to secure the same channel or source/drain distance between cells by forming a junction with the diffusion of dopant included in a PSG layer. CONSTITUTION: A device isolation area defining an active area is formed on a semiconductor substrate. A recess(180) is formed by etching the semiconductor substrate. A gate electrode pattern(190) is formed in he recess. A PSG(Phosphosilicate Glass) layer(200). An impurity included in the PSG layer is diffused to the active area by thermally processing the PSG layer.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the characteristics of a buried gate.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. The transistor is composed of three regions: a gate, a source, and a drain. The transistor transfers charge between the source and the drain according to a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has been gradually reduced, resulting in short channel effects and drain induced barrier lower (DIBL). The reliability of the operation was lowered. Phenomena that occur as the channel length decreases can be overcome by maintaining the threshold voltage so that the cell transistor can perform normal operation. Typically, the shorter the channel of the transistor, the higher the doping concentration of impurities in the region where the channel is formed.

However, as the design rule decreases to less than 100 nm, the increase in doping concentration in the channel region further increases the electric field at the storage node (SN) junction, thereby degrading the refresh characteristics of the semiconductor memory device. Cause. To overcome this problem, a cell transistor having a three-dimensional channel structure having a long channel length in the vertical direction is used to maintain the channel length of the cell transistor even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating.

In addition, as the degree of integration of the semiconductor device increases, the distance between the word line and the bit line connected to the cell transistor is closer. As the parasitic capacitance increases, the operating margin of the sense amplifier, which amplifies the data transmitted through the bit line, is deteriorated, which adversely affects the operation reliability of the semiconductor device. In order to overcome this problem, a buried word line structure has been proposed in which word lines are formed only in recesses, not on top of a semiconductor substrate, in order to reduce parasitic capacitance between bit lines and word lines. The buried word line structure is formed with a bit line formed on a semiconductor substrate on which a source / drain is formed by forming a conductive material in a recess formed in the semiconductor substrate and covering the top of the conductive material with an insulating film so that the word line is buried in the semiconductor substrate. Electrical isolation can be clarified.

As described above, in the buried word line structure, a region where the source / drain junction and the word line overlap each other, and a GIDL (Gate Induced Drain Leakage) occurs in the overlapped region. If the GIDL is large, the stored charge is discharged, thereby degrading memory retention characteristics.

In order to solve the above-described conventional problems, the present invention deposits a gate electrode material in a recess region formed by etching a semiconductor substrate, and then etches back to form a buried gate, When filling an insulating film for insulation between buried gates, a PSG (phosphosilicate glass) film is buried, and a dopant included in the PSG film is diffused by a heat treatment process to form a junction to form a junction or a depth of a gate electrode. The present invention provides a method of manufacturing a semiconductor device capable of securing the same channel or the same source / drain distance between cells even if the amount of the material is etched is different.

The present invention provides a method of forming a semiconductor device, the method comprising: forming a device isolation region defining an active region in a semiconductor substrate, forming a recess by etching the semiconductor substrate, forming a gate electrode pattern in the recess, Forming a PSG (Phosphosilicate glass) film and performing a heat treatment process on the PSG film to provide a method for manufacturing a semiconductor device comprising the step of diffusing impurities contained in the PSG film to the active region.

Preferably, forming a device isolation region defining an active region in the semiconductor substrate comprises depositing a pad insulating film on the semiconductor substrate, forming a trench by etching the pad insulating film and the semiconductor substrate, and forming the trench. And depositing an insulating material on the insulating material and planarizing etching the insulating material until the pad insulating film is exposed.

The method may further include forming a polysilicon layer on the removed region after removing the pad insulating layer after forming the device isolation region.

Preferably, the method further comprises performing an oxidation process in the recess between forming the recess and forming a gate electrode pattern in the recess.

The forming of the gate electrode pattern in the recess may include depositing a conductive material in the recess, and performing an etchback process to remove the conductive material on the recess. After the step and the etch back process, characterized in that it comprises the step of cleaning the top of the recess.

Preferably, the recess is formed by anisotropically etching the semiconductor substrate.

Preferably, after the forming of the PSG (Phosphosilicate glass) film, characterized in that it further comprises the step of performing an ion implantation process.

According to the present invention, a gate electrode material is deposited in a recess region formed by etching a semiconductor substrate and then etched back to form a buried gate, and then an insulating film is buried for insulation between neighboring buried gates. In this case, a PSG (phosphosilicate glass) film is embedded, and a dopant included in the PSG film is diffused to form a junction by a heat treatment process, so that even if the depth of the recess region or the amount of gate electrode material is etched is different, the cell ( The same channel or source / drain distance between cells can be secured.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a pad insulating film (not shown) is formed on a semiconductor substrate 100. In this case, the pad insulating film is preferably composed of a pad oxide film and a pad nitride film. Subsequently, after the photoresist is coated on the pad insulating film, a photoresist pattern (not shown) is formed by an exposure and development process using a mask defining an element isolation region. The trench 110 is formed by etching the pad insulating layer and the semiconductor substrate 100 using the photoresist pattern as an etching mask. Thereafter, sidewall oxidation is performed to form sidewall oxide layers (not shown) on the bottom and sidewalls of the trench 110.

Next, the liner nitride film 120 and the liner oxide film 130 are sequentially formed on the entire surface including the trench 110 in which the sidewall oxide film is formed. At this time, the liner nitride layer 120 is to improve the refresh characteristics by alleviating the stress applied to the semiconductor substrate 100, and the liner oxide layer 130 is a liner nitride layer (HDP layer or SOD layer) during deposition. 120 to prevent the oxidation and etching.

Then, a silicon on dielectric (SOD) material is embedded in the trench 110 and planarized etching is performed until the pad insulating layer is exposed to form the device isolation region 150.

Next, after forming the device isolation region 150, the exposed pad insulating film is removed. The polysilicon layer 160 is formed on the exposed active region 140.

Next, an interlayer insulating film 170 and a photosensitive film (not shown) are formed on the entire surface including the polysilicon layer 160, and then a photosensitive film pattern (not shown) is formed by an exposure and development process using a recess forming mask. . In this case, the interlayer insulating film 170 preferably includes an oxide film. The recess 180 is formed by etching the interlayer insulating layer 170, the polysilicon layer 160, and the semiconductor substrate 100 using the photoresist pattern as an etching mask.

Referring to FIG. 1B, a gate insulating film (not shown) and a gate electrode material (not shown) are sequentially formed in the recess 180, and then the gate electrode material is etched back into the recess region 180. The gate electrode pattern 190 is formed. In this case, the gate electrode material is preferably formed of a titanium nitride film (TiN) or a titanium nitride film (TiN) and a tungsten (W) laminated structure. Here, the gate insulating film is formed in the recess 180 by performing an oxidation process, and the oxidation process is preferably performed by a thermal treatment method or a plasma treatment method.

Referring to FIG. 1C, a capping layer 200 is buried in an upper portion of the gate electrode pattern 190 in the recess 180. At this time, the capping film 200 is preferably formed of a PSG (phosphosilicate glass) film. Here, in an enlarged view of region A of FIG. 1C, a dopant included in the capping layer 200 may be diffused into the active region 140 by performing heat treatment on the capping layer 200 to form a junction 210. Is formed.

As described above, the present invention deposits a gate electrode material in a recessed region formed by etching a semiconductor substrate, and then etches back to form a buried gate, and then insulation between neighboring buried gates is removed. In order to bury the insulating film to fill the PSG (phosphosilicate glass), and the heat treatment process the dopant (dopant) included in the PSG film is diffused to form a junction (etching) the amount of the depth of the recess region or the gate electrode material is etched Although different, the same channel or the same source / drain distance between cells can be secured.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (7)

Forming an isolation region defining an active region in the semiconductor substrate;
Etching the semiconductor substrate to form a recess;
Forming a gate electrode pattern in the recess;
Forming a PSG (Phosphosilicate glass) film on the gate electrode pattern; And
Performing a heat treatment process on the PSG film to diffuse impurities contained in the PSG film into the active region;
And forming a second insulating film on the semiconductor substrate. The method of claim 1,
Forming an isolation region defining an active region in the semiconductor substrate is
Depositing a pad insulating film on the semiconductor substrate;
Etching the pad insulating layer and the semiconductor substrate to form a trench; And
Depositing an insulating material in the trench and planarizing etching of the insulating material until the pad insulating film is exposed. The method of claim 2,
And forming a polysilicon layer on the removed region after the pad insulating layer is formed after the device isolation region is formed. The method of claim 1,
And performing an oxidation process in said recess between forming said recess and forming a gate electrode pattern in said recess. The method of claim 1,
Forming a gate electrode pattern in the recess
Depositing a conductive material in the recess;
Performing an etchback process to remove the conductive material on top of the recess; And
After the etch back process, cleaning the upper portion of the recess. The method of claim 1,
The recess is formed by anisotropically etching the semiconductor substrate. The method of claim 1,
And forming an ion implantation process after the forming of the PSG (Phosphosilicate glass) film.

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