KR20120020308A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory apparatus is provided to transfer a delayed column address and a bank address to a core region while delaying a command signal, thereby securing a margin between the column address, the bank address, and a column selection signal. CONSTITUTION: A core region(109) comprises a plurality of banks. A command timing control part outputs a delayed command signal by delaying a reading or writing signal while activating a delay control signal. A bank address timing control part outputs a delayed bank address by delaying the bank address while activating the delay control signal. A bank selector(103) generates a bank selection signal by decoding the delayed bank address. A column selection signal transfer part(107) transfers the delayed command signal to a column selection signal of a bank selected by the bank selection signal.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor memory device.

As is well known, a memory device includes a core region including a plurality of banks and peripheral circuits for controlling input and output of data stored in the core region. A bank is a collection of memory cells that store data, and memory cells are arranged in a matrix form between a plurality of rows and columns. Each row and column has a predetermined address.

The operation of the core region in the memory device includes first selecting a row address to amplify data of a corresponding word line and transferring the amplified data to a data line by selecting a column address. At this time, in order to transfer the correct data, the column should be selected while the data of the word line is sufficiently amplified. To this end, in the memory development phase, a test is performed to delay the column select signal with different delay amounts in test mode.

1 is a configuration diagram of a memory device according to the prior art.

Referring to FIG. 1, a memory device according to the related art may include a command timing controller 101, a bank selector 103, a column select signal transfer unit 105, a column address transfer unit 107, and a core region 109. Include.

The command timing controller 101 outputs the delayed command signal CAS_D by delaying the read signal CASRD or the write signal CASWT when the delay control signal YSTM is activated.

The delay control signal YSTM is a delay test mode for securing an operation margin of the column selection signals YS <0: 7> and the column address ADDYS (2: 9>) in the core region 109. Is the signal to be activated.

The read signal CASRD is a signal that is activated in the memory device when the column address strobe signal CAS applied from the outside of the memory device is activated and the write enable signal WE is deactivated. The CASWT is a signal that is activated in the memory device when the column address strobe signal CAS and the write enable signal WE are activated.

The bank selector 103 decodes the bank address BKADD <0: 2> to activate one of the bank select signals BK <0: 7>. Since it is assumed that the core region 109 includes eight banks, the number of bank selection signals BK <0: 7> is eight.

The column select signal transfer unit 105 transfers the delayed command signal CAS_D to the column select signals YS <0: 7> of the bank selected by the bank select signals BK <0: 7>. For example, when the bank select signal BK <2> is activated, the delayed command signal CAS_D is transferred to the column select signal YS <2>.

The column address transfer unit 107 strobes the input addresses ADDRD <2: 9> with the read signal CASRD in the read period, and uses the column address ADDYS <2: 9> to strobe the core region 109. In the write period, the input address ADDWT <2: 9> is strobe with the write signal CASWT and transmitted to the core region 109 as the column address ADDYS <2: 9>.

In the core area 100, a specific column is selected by the input column selection signals YS <0: 7> and column addresses ADDYS <2: 9>, and data of the corresponding memory cell is input / output.

However, the conventional memory device includes only the command timing controller 101 for delaying the command signal such as the read signal CASRD or the write signal CASWT, and thus the command signal CAS_D delayed by the column select signal transfer unit 105. ) Is different from the timing at which the timing of activating) and the timing of activating the non-delayed bank selection signals BK <0: 7> are different. In addition, in the core region 109, there is a problem that the activation timing between the column selection signals YS <0: 7> and the non-delayed column addresses ADDYS <2: 9> is different.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a memory device capable of securing a margin between a bank address and a column address in a delay test mode of a column select signal.

In the memory device according to the present invention for achieving the above object, the memory device, the core timing including a plurality of banks, the command timing for delaying the read signal or the write signal when the delay control signal is activated to output a delayed command signal A control unit, a bank address timing control unit for outputting a delayed bank address by delaying a bank address when the delay control signal is activated, and generating a bank select signal for selecting one bank among the plurality of banks by decoding the delayed bank address And a bank selector for transmitting the delayed command signal to a column select signal of a bank selected by the bank select signal.

The column address timing control unit may output a delayed read signal or a delayed write signal by delaying the read signal or the write signal when the delay control signal is activated, and a column address in response to the delayed read signal or the delayed write signal. The apparatus may further include a column address transfer unit for transferring the plurality of banks.

The delay amount of the command timing controller, the bank address timing controller, and the column address timing controller may be designed to be adjustable.

The column address may be strobe by the delayed read signal in a read period and transferred to the plurality of banks, or may be strobe by the delayed write signal in a write period and transmitted to the plurality of banks.

According to the present invention, a delay between a command signal and a bank address and a column address are also delayed and transferred to the core area, thereby ensuring a margin between the column select signal, the bank address, and the column address.

In addition, by performing the test while adjusting the delay amount of the column selection signal and the column address during the margin test of the core region, there is an advantage that the memory development period can be shortened.

1 is a block diagram of a memory device according to the prior art.
2 is a configuration diagram of an embodiment of a memory device according to the present invention;
3 is a diagram illustrating an internal configuration of the core region 109 of FIG. 2.
4 is a circuit diagram of an embodiment of the command timing controller 101 of FIG.
5 is a circuit diagram of an embodiment of the bank address timing controller 201 of FIG.
FIG. 6 is a circuit diagram of an embodiment of the column select signal transmitter 105 of FIG.
FIG. 7 is a circuit diagram of an embodiment of the column address timing controller 203 of FIG.
8 is a circuit diagram of an embodiment of the column address transfer unit 107 of FIG.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a configuration diagram of an embodiment of a memory device according to the present invention.

Referring to FIG. 2, the memory device according to an embodiment of the present invention may delay the read signal CASRD or the write signal CASWT when the core region 109 including a plurality of banks and the delay control signal YSTM are activated. The command timing controller 101 which outputs the delayed command signal CAS_D, delays the bank address ADDBK <0: 2> when the delay control signal YSTM is activated, and delays the bank address ADDBK_D <0: 2>. The bank address timing control unit 201 outputs a delayed bank address ADDBK_D <0: 2> to generate a bank select signal BK <0: 7> for selecting one of the plurality of banks. The bank selector 103, a column select signal transfer unit 107 for transferring the delayed command signal to the column select signal YS <0: 7> of the bank selected by the bank select signal BK <0: 7>; When the delay control signal YSTM is activated, the read signal CASRD or the write signal CASWT is delayed. The column address timing controller 203 outputting the delayed read signal CASRD_D or the delayed write signal CASWT_D and the column address ADDYS <2: 9 in response to the delayed read signal CASRD_D or the delayed write signal ADDWT_2: 9. Column address transfer unit 107 for transferring &quot;) to a plurality of banks.

In this embodiment, it is assumed that the core region 109 is composed of eight banks.

The read signal CASRD and the write signal CASWT are command signals activated inside the memory device by the column address strobe signal CAS. Specifically, when the column address strobe signal CAS is activated as' high 'and the write enable signal WE is deactivated as' low' in the command decoder, the read signal CASRD is' When the 'high' is activated and both the column address strobe signal CAS and the write enable signal WE are activated 'high', the write signal CASWT is activated as 'high'.

The delay control signal YSTM is a signal that is activated in a test mode for securing an operating margin of the column selection signals YS <0: 7> in the core region 109. When the delay control signal YSTM is activated as 'high', the command timing controller 101, the bank address timing controller 201, and the column address timing controller 203 delay and output the input signal or address. At this time, each control unit may be designed to be able to adjust the delay amount.

The command timing controller 101 outputs the delayed command signal CAS_D by delaying the read signal CASRD or the write signal CASWT which is a command signal when the delay control signal YSTM is activated. The delayed command signal CAS_D determines the timing at which the column selection signals YS <0: 7> are activated in the core region 109. That is, by adjusting the delay amount that delays the command signal in the test mode, the column select signals YS <0: 7> are activated with the most appropriate margin during the time that the word line is selected in the bank and the data is amplified. To determine the timing.

The bank address timing controller 201 delays the bank address ADDBK <0: 2> input when the delay control signal YSTM is activated, and outputs the delayed bank address ADDBK_D <0: 2>. Since the conventional memory device has only a configuration of delaying only the command signal in the test mode, it is difficult to match the timing between the delayed command signal CAS_D and the non-delayed bank address ADDBK <0: 2>. In order to solve the problem, a configuration in which the bank address ADDBK <0: 2> is also delayed as in the command signal is added. Here, it is preferable that the delay amounts of the command timing control unit 101 and the bank address timing control unit 201 are the same.

The bank selector 103 decodes the delayed bank address ADDBK_D <0: 2> to receive a bank select signal BK <0: 7> for selecting one bank among a plurality of banks in the core region 109. Output

Table 1 summarizes the relationship between the delayed bank address (ADDBK_D <0: 2>) and the bank selection signals BK <0> to BK <7>.

BKADD_D <0: 2> Bank select signal BKADD_D <0: 2> Bank select signal 000 BK <0> 100 BK <4> 001 BK <1> 101 BK <5> 010 BK <2> 110 BK <6> 011 BK <3> 111 BK <7>

The column select signal transfer unit 105 receives the delayed command signal CAS_D and the bank select signals BK <0: 7> and transmits the delayed command signal CAS_D to the bank select signals BK <0: 7>. The signal is transferred to the column select signals YS <0: 7> of the selected bank. This will be described in detail with reference to FIG. 3.

When the delay control signal YSTM is activated, the column address timing controller 203 delays the read signal CASRD in the read period and outputs the delayed read signal CASRD_D in the read period, and delays the write signal CASWT in the write period. The delayed write signal CASWT_D is output. In the conventional memory device, only the command signal is delayed in the test mode, so that a margin between the column select signal YS <0: 7> and the column address ADDYS <2: 9> is secured in the core region 109. Since there is a problem of difficulty, the delayed read signal CASRD_D or the delayed write signal CASWT_D is used to match the timing with the column select signals YS <0: 7>. It is preferable that the delay amounts of the command timing controller 101 and the column address timing controller 203 are the same.

In addition, the reason for distinguishing the delayed read signal CASRD_D and the delayed write signal CASWT_D may be different from the CAS latency CL and the write latency WL, thereby ensuring an optimum margin in the core region 109. This is because the delay amount of the read signal CASRD and the delay amount of the write signal CASWT may be different.

The column address transfer unit 107 transfers the column address ADDYS <2: 9> that is strobe by the delayed read signal CASRD_D or the delayed write signal CASWT_D to the core region 109. Specifically, in the read period, the input read address ADDRD <2: 9> is strobe with the delayed read signal CASRD_D and transmitted to the column address ADDYS <2: 9>, and in the write period, the write address ( The ADDWT <2: 9> is strobe with the delayed write signal CASWT_D and transferred to the column address ADDYS <2: 9>.

3 is a diagram illustrating an example embodiment of the core region 109 of FIG. 2. In the present embodiment, the case of including eight banks BANK0 to BANK7 is illustrated, but the concept of the present invention can be applied to the case of 4 banks, 16 banks, or the like.

The bank selector 103 decodes the delayed bank address ADDBK_D <0: 2> to activate one of the eight bank select signals BK <0> to BK <7>, and activates the activated bank select signal BK. Column selection signals YS <0> to YS <7> corresponding to the banks BANK0 to BANK7 selected by <0> to BK <7> are applied.

The column addresses ADDYS <2: 9> transmitted from the column address transfer unit 107 are input to all banks BANK0 to BANK7 in the core region 109 so that data input and output are performed.

FIG. 4 is a circuit diagram of an embodiment of the command timing controller 101 of FIG. 2.

As shown in FIG. 4, the command timing controller 101 may include a NAND gate 401, a delay unit 403, and two pass gates 405 and 407.

When the delay control signal YSTM is activated, the pass gate 405 is turned off and the pass gate 407 is turned on so that the read signal CASRD or the write signal CASWT is the NAND gate 401 and the delay unit 403. The signal is transferred to the delayed command signal CAS_D through the pass gate 407. When the delay control signal YSTM is inactivated, the pass gate 405 is turned on and the pass gate 407 is turned off to transmit the read signal CASRD or the write signal CASWT without passing through the delay unit 403. do.

In this case, the NAND gate 401 is provided to prevent the command signals CASRD and CASWT from being transmitted to the delay unit 403 when the delay control signal YSTM is inactivated, thereby preventing unnecessary current consumption due to the delay unit 403. You can get the effect. In addition, since the delay amount of the delay unit 403 can be designed to be adjustable, it is easy to find the optimal timing for securing the margin of the column selection signals YS <0: 7> using the test mode. .

FIG. 5 is a circuit diagram of an embodiment of the bank address timing controller 201 of FIG. 2.

As shown in FIG. 5, the bank address timing controller 201 includes three delay circuits 501 to 503, and the delay circuit 501 includes a NAND gate 511, a delay unit 513, and two paths. Gates 515 and 517 may be included.

The operation of the bank address timing control unit 201 will be described through the delay circuit unit 501. The operation methods of the remaining delay circuit units 502 and 503 are the same.

When the delay control signal YSTM is activated, the pass gate 515 is turned off and the pass gate 517 is turned on so that the bank address ADDBK <0> is set to the NAND gate 511, the delay unit 513, and the pass. Passed through the gate 517 is passed to the delayed bank address (ADDBK <0>). When the delay control signal YSTM is inactivated, the pass gate 515 is turned on and the pass gate 517 is turned off so that the bank address ADDBK <0> is transferred without passing through the delay unit 513.

Here, the delay unit 513 is delayed by the same delay amount as the delay unit 403 of the command control unit 101, so that the delayed command signals CAS_D and the bank select signals BK <0> to BK <7> are columns. The timing input to the selection signal transfer unit 105 may be adjusted. Similar to the command timing controller 101, the delay amount of the delay unit 513 in the test mode can be adjusted.

FIG. 6 is a circuit diagram of an embodiment of the column select signal transmitter 105 of FIG. 2.

As shown in FIG. 6, the column select signal transmission unit 105 includes eight circuit units 601 to 608 for generating eight column select signals YS <0> to YS <7>. 601 may include two PMOS transistors PM61 and PM62, two NMOS transistors NM61 and NM62, and three inverters IV61, IV62, and IV63.

Referring to the operation of the column select signal transfer unit 105 through the circuit unit 601, the NMOS transistors NM61 and NM62 when the delayed command signal CAS_D and the bank select signal BK <0> are activated 'high'. Is turned on, and the column select signal YS <0> is activated 'high' through the inverters IV61, IV62, and IV63. When the delayed command signal CAS_D is 'low', the column select signal YS <0> also becomes 'low' and is held by the row latches PM62 and IV61. The column select signals YS <0> are transmitted to the corresponding bank BANK0. In the same manner, the remaining column select signals YS <1> to YS <7> are also activated to correspond to the corresponding banks BANK1 to BANK7. Is passed to.

FIG. 7 is a circuit diagram of an embodiment of the column address timing controller 203 of FIG. 2.

As shown in FIG. 7, the column address timing control unit 203 includes a read signal delay circuit unit 701 and a write signal delay circuit unit 702, and the read signal delay circuit unit 701 includes a NAND gate 711 and a delay. A portion 713 and two pass gates 715 and 717 may be included.

The operation of the column address timing controller 201 through the read signal delay circuit unit 701 will be described. The operation method of the write signal delay circuit unit 702 is the same.

When the delay control signal YSTM is activated, the pass gate 715 is turned off and the pass gate 717 is turned on so that the read signal CASRD is the NAND gate 711, the delay unit 713, and the pass gate 717. Is transmitted to the delayed read signal CASRD. When the delay control signal YSTM is inactivated, the pass gate 715 is turned on and the pass gate 717 is turned off so that the read signal CASRD is transmitted without passing through the delay unit 713. The delay amount of the delay unit 713 can be adjusted.

The delay amount of the delay unit 713 delaying the read signal CASRD and the delay amount of the delay unit 723 delaying the write signal CASWT may be different from each other. This is because when the cascade latency CL in the read operation and the write latency WL in the write operation are different, the timing for strobe the address may vary in each operation.

8 is a circuit diagram of an example of the column address transfer unit 107 of FIG. 2.

As illustrated in FIG. 8, the column address transfer unit 107 may include an address ADDRD <2> to ADDRD <9> input in a read period or an address ADDWT <2> to ADDWT <9> input in a write period. ) Includes eight transfer circuits 801 to 808 for transferring to the column addresses ADDYS <2> to ADDYS <9>, and the transfer circuit 801 includes four PMOS transistors PM81 to PM84, four NMOS transistors NM81 to NM84 and latch units IV81 and IV82 may be included.

The operation of the column address transfer unit 107 through the transfer circuit unit 801 will be described.

When the address ADDRD <2> is input in the read period, when the delayed read signal CASRD_D is activated 'high', the delayed read signal CASRD_D is strobe and transferred to the column address ADDYS <2>. The transferred column address ADDYS <2> is held until the next address is input by the latch units IV81 and IV82. Similarly, when the address ADDWT <2> is input in the write section, it is transferred to the column address ADDYS <2> when the delayed write signal CASWT_D is activated.

In this manner, the column addresses ADDYS <2: 9> are transferred through the eight transfer circuit units 801 to 808 and input to all banks BANK0 to BANK7 of the core region 109.

As described above, in the present invention, in the margin test of the core region, the command signal is delayed to activate the column selection signal and at the same time, the bank address and the column address are also delayed and transferred to the core region. A memory device capable of securing margins and shortening the memory development period by testing while adjusting the delay amount of the column selection signal and the column address has been proposed.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

Claims (8)

A core region comprising a plurality of banks;
A command timing control unit which outputs a delayed command signal by delaying the read signal or the write signal when the delay control signal is activated;
A bank address timing controller for outputting a delayed bank address by delaying a bank address when the delay control signal is activated;
A bank selector configured to decode the delayed bank address to generate a bank select signal for selecting one of the plurality of banks; And
A column select signal transfer unit configured to transfer the delayed command signal to a column select signal of a bank selected by the bank select signal;
Memory device comprising a.
The method of claim 1,
The delay amount of the command timing controller and the bank address timing controller is adjustable.
Memory device.
The method of claim 1,
The lead signal is
Is activated when the column address strobe signal is activated and the write enable signal is deactivated
Memory device.
The method of claim 1,
The light signal is
Is activated when the column address strobe signal and the write enable signal are activated
Memory device.
The method of claim 1,
A column address timing controller configured to delay the read signal or the write signal and output a delayed read signal or a delayed write signal when the delay control signal is activated; And
A column address transfer unit configured to transfer a column address to the plurality of banks in response to the delayed read signal or the delayed write signal
The memory device further comprising.
6. The method of claim 5,
The delay amount of the column address timing controller is adjustable
Memory device.
6. The method of claim 5,
The column address is
Strobe by the delayed read signal in the read period is delivered to the plurality of banks
Memory device.
6. The method of claim 5,
The column address is
Strobe by the delayed write signal in the write period is delivered to the plurality of banks
Memory device.

Images