KR20120003617A - Periphery circuit structure of semiconductor device - Google Patents

Periphery circuit structure of semiconductor device Download PDF

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Publication number
KR20120003617A
KR20120003617A KR1020100064318A KR20100064318A KR20120003617A KR 20120003617 A KR20120003617 A KR 20120003617A KR 1020100064318 A KR1020100064318 A KR 1020100064318A KR 20100064318 A KR20100064318 A KR 20100064318A KR 20120003617 A KR20120003617 A KR 20120003617A
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KR
South Korea
Prior art keywords
region
fuse
line
semiconductor device
pads
Prior art date
Application number
KR1020100064318A
Other languages
Korean (ko)
Inventor
조희정
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100064318A priority Critical patent/KR20120003617A/en
Publication of KR20120003617A publication Critical patent/KR20120003617A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention relates to a peripheral circuit structure of a semiconductor device, comprising: a plurality of pads; A fuse line region disposed between the pads; And a global line region spaced apart from one side of the region where the plurality of pads and the fuse line region is disposed and extending in the long axis direction.

Description

Peripheral circuit structure of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits and, more particularly, to peripheral circuit structures of semiconductor devices.

The semiconductor device is divided into a memory cell region and a peripheral circuit region, and in particular, a plurality of pads, global lines, and fuse line regions for input / output are disposed in the peripheral circuit region.

However, a problem arises in that the layout area of the semiconductor device as a whole increases due to the increase in the number of data lines and the layout area thereof as the semiconductor device increases in capacity and speed.

That is, the global line and the fuse line region disposed in the peripheral circuit region occupy about 80% of the peripheral circuit region. At this time, the global line and the fuse line region are adjacent to each other and are routed in the same direction. This arrangement has to increase the number of global lines and the memory cell area together as the semiconductor device becomes higher in capacity and speed, but there is a limit to increasing the global line since the fuse line area is routed in the same area with the global line. .

The present invention has been made to solve the above-described problem, it is possible to increase the global line number of the semiconductor circuit.

A peripheral circuit structure of a semiconductor device according to an embodiment of the present disclosure may include a plurality of pads; A fuse line region disposed between the pads; And a global line region spaced apart from one side of the region where the plurality of pads and the fuse line region is disposed and extending in the long axis direction.

The peripheral circuit structure of the semiconductor device according to the present invention has the effect of increasing the global line number of the semiconductor device by disposing the fuse line region in the excess area between the pads.

1 is a plan view showing a peripheral circuit structure of a semiconductor device according to an embodiment of the present invention;
2A and 2B are plan views illustrating fuse line regions of a peripheral circuit structure of the semiconductor device of FIG. 1.

1 is a plan view illustrating a peripheral circuit structure of a semiconductor device according to an embodiment of the present disclosure.

As shown in FIG. 1, the peripheral circuit structure 100 of the semiconductor device according to the exemplary embodiment includes first to third regions 102, 104, and 106.

The first region 102 is disposed to be spaced a predetermined distance from one side 130a of the global line region 130 of the third region 106, and the first pad 112, the second pad 114, and the first pad 102 are spaced apart from each other. Fuse line region 122.

The first and second pads 112 and 114 are input / output pads for inputting / outputting data in a memory cell area, and a power supply including a power supply pad for supplying power to a semiconductor device and a pair of ground power pads. At least one of the supply pads.

The first fuse line region 122 is disposed between the first and second pads 112 and 114. The first fuse line region 122 will be described in more detail later with reference to FIGS. 2A and 2B.

The second region 104 is disposed spaced apart from the other side 130b of the global line region 130 of the third region 106 by the third pad 116, the fourth pad 118, and the second fuse. Line region 124. Each of the third pad 116, the fourth pad 118, and the second fuse line region 124 of the second region 104 may have a first pad 112 and a second pad 114 of the first region 102. ) And the first fuse line region 122, the description of the configuration will be omitted.

In the present invention, although two pads 112, 114, 116, 118 and one fuse line region 122, 124 are disposed in each of the first region 102 and the second region 104, the convenience of explanation. For the sake of simplicity, the present invention is not limited to the embodiment of the present invention and may be changed according to the chip size of the semiconductor device.

The third region 106 is disposed between the first and second regions 102 and 104. The third region 106 includes a plurality of global lines GIO <0: N> for transferring data for inputting or outputting data to the memory cell region.

As such, in the present invention, the fuse line regions 122 and 124 routed together with the global line (GIO <0: N>) in the existing third region 106 may be divided into a plurality of pads 112, 114, 116, By disposing in the remaining spaces of the first region 102 and the second region 104 in which the 118s are formed, it is possible to reduce the overall area size of the semiconductor by increasing the utilization of the remaining space and increase the number of global lines of the semiconductor device. Can be.

2A and 2B are plan views illustrating fuse line regions of a peripheral circuit structure of the semiconductor device of FIG. 1.

As shown in FIG. 2A, the first fuse line region 122 of the peripheral circuit structure according to the present invention includes a fuseset group 140. Here, the second fuse line region 124 has the same structure as the first fuse line region 122, and therefore, only the first fuse line region 122 will be referred to in the present invention.

The fuse set group 140 includes a guard ring line 142 and a fuse set 144.

The guard ring line 142 is a power supply line for supplying power to the fuse set 144, and is disposed in a lower layer of the fuse set 144. The guard ring line 142 is electrically connected to the fuse set 144 by a contact.

The guard ring line 142 is formed in a closed curve shape to define a predetermined region.

The fuse set 144 includes a plurality of fuses that store address information of a defective cell. Each of the fuses is formed at a P interval, which is a distance satisfying the neighboring fuses 152 and 154 and the laser array error tolerance.

The fuse set 144 is disposed in a space surrounded by the guard ring line 142 line. At this time, the planar distance between the ends of the fuses and the guard ring line 142 is L1. However, even though the ends of the fuses and the guard ring line 142 abut, since the insulation is interposed between the upper and lower layers, the size of the fuse set 144 and the size of the guard ring line 142 are the same. It can be formed in size.

The fuse set group 140 may be formed of one fuse set 140 as illustrated in FIG. 2A, or may be formed of a plurality of fuse sets 140a and 140b as illustrated in FIG. 2B.

When at least one fuseset group 140a, 140b is formed as shown in FIG. 2B, each fuseset group 140a, 140b is allowed to prevent signal distortion between adjacently arranged guard ring lines 142a, 142b. It may be formed spaced apart by the distance L2 satisfying the range.

As such, the peripheral circuit structure of the semiconductor device according to the present invention can reduce the total area of the semiconductor device by arranging the fuse lines between the pads, and extending the global lines in a straight line without bypassing the conventional lines.

As those skilled in the art can realize the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: peripheral circuit structure 112, 114, 116, 118: pad
122: first fuse line region 124: second fuse line region
130: global line area

Claims (9)

A pad area including a plurality of pads; And
A global line region including a plurality of global lines arranged to face the pad region,
And a fuse line region disposed between the plurality of pads. The method according to claim 1,
And the fuse line region includes at least one fuseset group. The method of claim 2,
Each of the at least one fuseset group,
A fuse set including a plurality of fuses storing address information of a defective cell; And
And a guard ring line electrically connected to the fuse set. The method of claim 3,
Each of the at least one fuseset group,
A peripheral circuit structure of a semiconductor device that is formed spaced apart from each other by a predetermined interval. A first region comprising a plurality of pads and a first fuse line region;
A second region disposed to face the first region, the second region including a plurality of pads and a second fuse line region; And
And a third region extending and disposed between the first region and the second region. The method of claim 5,
In the third area,
A peripheral circuit structure of a semiconductor device in which a plurality of global lines are formed. The method of claim 6,
And each of the first and second fuse line regions includes at least one fuseset group. The method of claim 7, wherein
Each of the at least one fuseset group,
A fuse set composed of a plurality of fuses storing address information of a defective cell; And
And a guard ring line electrically connected to the fuse set. The method of claim 8,
Each of the at least one fuseset group,
A peripheral circuit structure of a semiconductor device spaced apart from each other by a predetermined distance.
KR1020100064318A 2010-07-05 2010-07-05 Periphery circuit structure of semiconductor device KR20120003617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100064318A KR20120003617A (en) 2010-07-05 2010-07-05 Periphery circuit structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100064318A KR20120003617A (en) 2010-07-05 2010-07-05 Periphery circuit structure of semiconductor device

Publications (1)

Publication Number Publication Date
KR20120003617A true KR20120003617A (en) 2012-01-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100064318A KR20120003617A (en) 2010-07-05 2010-07-05 Periphery circuit structure of semiconductor device

Country Status (1)

Country Link
KR (1) KR20120003617A (en)

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