KR20110134286A - Circuit of controlling a precharge and integrated circuit having the same - Google Patents

Abstract

PURPOSE: A precharge control circuit and an integrated circuit including the same are provided to reduce a peak current in a precharge operation by controlling a control signal to slowly supply a precharge voltage. CONSTITUTION: A precharge voltage provider outputs a precharge voltage according to a voltage level of a precharge control signal. A voltage generator outputs an operation voltage for controlling a voltage level of the precharge control signal in response to a first enable signal and a voltage control signal. A signal generator(263) locks the voltage of the precharge control signal to a preset level in response to a second enable signal. If the second enable signal is disable, the signal generator linearly changes the voltage level of the precharge control signal according to a slope determined by the voltage level of the operation voltage.

Description

Precharge control circuit and integrated circuit having same {circuit of controlling a precharge and integrated circuit having the same}

The present invention relates to a precharge control circuit and an integrated circuit having the same.

Nonvolatile semiconductor memory devices have a characteristic in that stored data is not erased even when power supply is interrupted.

Such nonvolatile memory devices are programmed or erased through F-N tunneling. Electrons are accumulated in the floating gate by the program operation, and electrons accumulated in the floating gate are emitted to the substrate by the erase operation. The threshold voltage of the memory cell varies according to the amount of electrons accumulated in the floating gate, and the data is determined according to the level of the threshold voltage detected by the read operation.

1 is a diagram for describing a structure of a memory cell array of a semiconductor memory device.

Referring to FIG. 1, the memory cell array 100 of the semiconductor memory device includes a plurality of memory blocks BK. The plurality of memory blocks BK are disposed up and down. Each memory block BK includes a plurality of cell strings.

Each cell string is connected to a bit line (BL). The cell strings of the memory blocks BK arranged in the same column are connected to one bit line BL.

Therefore, as the number of memory blocks increases, the length of the bit line increases. In general, when a program or a read operation is performed in a semiconductor memory device, a bit line is precharged or discharged. Therefore, the longer the length of the bit line, the longer the precharge or discharge time of the bit line. In addition, when the power supply voltage is applied at one time to precharge the bit line, the peak current may be increased to affect the operation of other circuits.

The precharge problem is not limited to the bit line, but is a problem that may occur when the loading of the line to be precharged in the integrated circuit is large.

An embodiment of the present disclosure provides a semiconductor memory device capable of reducing peak current generated in a precharge operation by adjusting a control signal to gradually supply a precharge voltage supplied to a precharge circuit.

Precharge control circuit according to an embodiment of the present invention,

A precharge voltage providing unit configured to output a precharge voltage according to a voltage level of the precharge control signal; A voltage generator configured to output an operating voltage for controlling a voltage level of the precharge control signal in response to a first enable signal and a voltage control signal; And in response to the second enable signal, fix the voltage of the precharge control signal to a predetermined level, and when the second enable signal is disabled, set the voltage level of the precharge control signal to the voltage level of the operating voltage. It includes a signal generator for changing the linearly according to the slope determined by the.

Integrated circuit according to an embodiment of the present invention,

An integrated circuit comprising a plurality of circuits, the integrated circuit comprising: a precharge voltage circuit for providing a precharge voltage changed according to a voltage level of a precharge control signal; A precharge control circuit for changing and outputting a voltage level of the precharge control signal to linearly change a voltage level of the precharge voltage in response to a first and second enable signal and a voltage control signal; And a control logic for outputting the first and second enable signals for precharge operation, and for outputting the voltage control signal according to a change in ambient temperature and a change in power supply voltage level.

The precharge control circuit and the integrated circuit having the same according to an exemplary embodiment of the present invention adjust the precharge control signal to gradually input the precharge voltage when the precharged circuit load is large according to the precharge control signal. Peak current generated in the charge operation can be reduced.

1 is a diagram for describing a structure of a memory cell array of a semiconductor memory device.
2 is a diagram for describing a semiconductor memory device.
FIG. 3 is a diagram for describing the page buffer of FIG. 2.
4 is a diagram for describing a precharge control circuit for precharging a bit line in stages.
FIG. 5A illustrates a precharge control signal that is instantaneously changed by the precharge control circuit of FIG. 4.
FIG. 5B illustrates a precharge control signal changed in stages by the precharge control circuit of FIG. 4.
FIG. 5C illustrates the degree to which the internal voltage falls according to the precharge control signal shown in FIG. 5A.
FIG. 5D illustrates the degree to which the internal voltage falls according to the precharge control signal shown in FIG. 5B.
6 is a detailed circuit diagram of a precharge control circuit according to an embodiment of the present invention.
FIG. 7A illustrates precharge control signals changed according to transistors turned on in the precharge control circuit.
FIG. 7B illustrates the degree of internal voltage drop as precharge control signals are input as shown in FIG. 7A.
8 is a timing diagram of control signals for explaining an operation of FIG. 6.
9 shows a precharge control circuit according to a second embodiment of the present invention.
10 is a block diagram schematically illustrating a voltage control signal output portion of the control logic.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2 is a diagram for describing a semiconductor memory device.

Referring to FIG. 2, the semiconductor memory device 200 may include a memory cell array 210, a page buffer group 220, an X decoder 230, a voltage supply circuit 240, a control logic 250, and a precharge control circuit. 260.

The memory cell array 210 includes a plurality of memory blocks BK. The memory blocks BK are disposed up and down, for example. Each memory block includes a plurality of cell strings.

Each cell string includes a drain select transistor (DST) and a source select transistor (SST), and includes zero through zeros between the drain select transistor (DST) and the source select transistor (SST). 31 Memory cells C0 to C31 are connected in series.

A drain select line DSL is connected to a gate of the drain select transistor DST, and a drain of the drain select transistor DST is connected to a bit line. The bit lines of FIG. 2 are divided into an even bit line (BLe) and an odd bit line (BLo).

A source select line SS is connected to the gate of the source select transistor SST, and a source of the source select transistor SST is connected to a common source line.

The 0th to 31st word lines WL0 to WL31 are connected to gates of the 0th to 31st memory cells C0 to C31, respectively.

The cell strings of the memory blocks BK arranged in the same column are connected to one bit line BL.

The page buffer group 220 includes a plurality of page buffers (PBs) 221. Each page buffer 221 is connected to one or more bit lines. The page buffer 221 of the semiconductor memory device 200 illustrated in FIG. 2 is connected to a pair of even bit lines BLe and an odd bit line BLO.

The page buffer 221 temporarily stores data for programming in the selected memory cell or reads and stores data stored in the selected memory cell.

The X decoder 230 includes a plurality of block selection circuits 231. Each block selection circuit 231 is connected to one memory block BK, respectively.

In response to the control signal from the control logic 250, the block select circuit 231 may drain the drain select line DSL, the source select line SSL, and the 0 th to 31 th word lines WL0 to WL31 of the memory block BK. ) And the global drain select line GDSL, the global source select line GSSL, and the global word lines GWL0 to GWL31 of the voltage supply circuit 240.

The voltage supply circuit 240 generates an operating voltage, for example, a read voltage Vread, a program voltage Vpgm, a pass voltage Vpass, and the like in response to a control signal from the control logic 250. It is provided to the global drain select line GDSL, the global source select line GSSL, and the global word lines GWL0 to GWL31.

The control logic 250 outputs a control signal for controlling the operation of the semiconductor memory device 200 such as a program, a read, an erase, and the like.

The precharge control circuit 260 outputs a precharge control signal PRECH input to the page buffer group 220.

By the operation of the page buffers 221 of the page buffer group 220, the even bit line BLe or the odd bit line BLO is selectively precharged.

FIG. 3 is a diagram for describing the page buffer of FIG. 2.

Referring to FIG. 3, the page buffer 221 includes a bit line selector 222, a precharge unit 223, a sensing unit 224, and a latch unit 225.

The bit line selector 222 selects one of the even bit line BLe and the odd bit line BLO. The selected bit line BLe or BLo is connected to the first sensing node SO1. The bit line selector 222 includes first and second NMOS transistors N1 and N2. The first NMOS transistor N1 is connected between the even bit line BLe and the first sensing node SO1, and the second NMOS transistor N2 is connected to the odd bit line BLo and the first sensing node SO1. Is connected between.

An even bit line selection signal BSLe is input to a gate of the first NMOS transistor N1, and an odd bit line selection signal BSLo is input to a gate of the second NMOS transistor N2.

The sensing unit 224 changes the voltage of the second sensing node SO2 according to the bit line voltage connected to the first sensing node SO1. The sensing unit 224 includes a third NMOS transistor N3.

The third NMOS transistor N3 is connected between the first and second sensing nodes SO1 and SO2, and the sensing signal PBSENSE is input to the gate of the third NMOS transistor N3.

The precharge unit 223 precharges the second sensing node SO2 or the even bit line BLe or the odd bit line BLo through the first sensing node SO1 connected to the second sensing node SO2. Optionally precharge).

The precharge unit 223 includes a PMOS transistor P. The PMOS transistor P is connected between the power supply voltage input terminal and the second sensing node SO2, and the precharge control signal PRECH is input to the PMOS transistor P.

The degree to which the PMOS transistor P is turned on is controlled according to the precharge control signal PRECH, and thus the operation of precharging the bit line through the second sensing node SO2 is controlled.

The latch unit 225 temporarily stores data to be programmed, or reads and stores data stored in a selected memory cell.

As described above, the memory block BK shares the bit lines BLe or BLo. Therefore, as the number of memory blocks BK increases, the lengths of the even bit line BLe and the odd bit line BLO become longer, and the loading of the bit lines for precharging also increases.

As described above, when precharging a bit line having a large loading, a peak current may increase. This problem is not limited to bit line precharge of semiconductor memory devices. In an integrated circuit such as a semiconductor memory device, a circuit requiring precharge is included, and if the circuit has a large loading, a problem of peak current increase due to sudden precharge voltage is applied.

In order to solve the peak current problem, a method of applying the precharge voltage itself in stages or using the following circuit for precharge control may be used.

Typically, the following method may be used to solve the peak current problem during the precharge operation of the bit line.

4 is a diagram for describing a precharge control circuit for precharging a bit line in stages.

Referring to FIG. 4, the bit line precharge circuit 260 for precharging the bit lines step by step includes first to third switches SW1, SW2, and SW3 and a level generator 261.

The first switch SW1 is connected to the power input terminal and the node K1 in response to the first control signal, and the second switch SW2 connects the output node of the level generator 261 in response to the second control signal. K1).

The third switch SW3 connects the ground node to the node K1 in response to the third control signal.

The first to third control signals are input from the control logic 250.

The level generator 261 generates and outputs a voltage lower than the power supply voltage and higher than the ground voltage. The voltage output by the level generator 261 is controlled by the control logic 250.

FIG. 5A illustrates a precharge control signal that is instantaneously changed by the precharge control circuit of FIG. 4, and FIG. 5B illustrates a precharge control signal that is gradually changed by the precharge control circuit of FIG. 4.

5C shows the degree of falling of the internal voltage according to the precharge control signal as shown in FIG.

5A to 5D, reference is made to FIGS. 2 to 4.

In the case of FIG. 5A, a first control signal is initially input from the control logic 250 of FIG. 2 to turn on the first switch SW1. The third switch SW3 is turned on in response to the third control signal output from the control logic 250. Accordingly, the precharge control signal PRECH is changed from the high level to the low level.

When the precharge control signal PRECH is changed from the high level to the low level as shown in FIG. 5A, the internal voltage drops about 1.5V as in 5c. This means that the peak current of the current flowing to precharge the bit line increases.

To compensate for this, a precharge control signal PRECH having an intermediate step is provided as shown in FIG. 5B.

Initially, the high level precharge control signal PRECH is maintained by the first control signal from the control logic 250. When the second control signal is input from the control logic 250, the output aV of the level generator 261 becomes the precharge control signal PRECH.

Finally, when the third control signal is input from the control logic 250, the node K1 is connected to the ground node, and the precharge control signal PRECH becomes the ground voltage level.

Accordingly, the precharge control signal PRECH is changed from a high level to an intermediate voltage level and a low level. Therefore, as shown in FIG. 5D, the degree of the internal voltage drop is smaller than that of the precharge control signal PRECH of FIG. 5A. However, voltage drop still occurs, and adjusting the voltage output by the level generator 261 is a difficult problem because it must consider factors such as fluctuations in ambient temperature and power supply voltage level.

Alternatively, additional circuitry for precharging the bit lines may be made, but adding circuitry has the problem of increasing the size of the semiconductor memory device.

Accordingly, in the present invention, a circuit is used in which the precharge control signal PRECH is gradually changed linearly from a high level to a low level. Accordingly, the PMOS transistor P of the page buffer 221 of FIG. 3 is also gradually turned on linearly to gradually input the precharge voltage to the bit line. This can prevent the peak current from increasing.

6 is a detailed circuit diagram of a precharge control circuit according to a first embodiment of the present invention.

Referring to FIG. 6, the precharge control circuit 260 that generates the precharge control signal PRECH includes a current control circuit 262 and a signal generator 263.

The current control circuit 262 includes a first PMOS transistor PM1, a resistor R, first to fourth NMOS transistors NM1 to NM4, and a level generator 262a.

The signal generator 263 includes a second PMOS transistor PM2 and a fifth NMOS transistor NM5.

The first PMOS transistor PM1 and the resistor R are connected in series between the power supply voltage input terminal and the node K2, and the first enable signal EN1 is input to the gate of the first PMOS transistor PM1. .

The first to fourth NMOS transistors NM1 to NM4 are connected in parallel between the node K2 and the ground node.

The level generator 262a outputs a voltage set in response to the voltage control signal from the control logic 250. At this time, the level generator 262a outputs the first to fourth control voltages a1 to a4. The first to fourth control voltages a1 to a4 are input to the gates of the first to fourth NMOS transistors NM1 to NM4, respectively.

The level generator 262a outputs a voltage to some or all of the first to fourth control voltages a1 to a4 according to the control signal of the control logic 250. If the level generator 262a outputs only the first control voltage a1, only the first NMOS transistor NM1 is turned on, and if the level generator 262a outputs the first and second control voltages a1 and a2, The first and second NMOS transistors NM1 and NM2 are turned on.

If the level generator 262a outputs the first to fourth control voltages a1 to a4, all of the first to fourth NMOS transistors NM1 to NM4 are turned on.

On the other hand, as another embodiment (not shown), the level generator 262a has one voltage output terminal and adjusts the number of the first to fourth NMOS transistors NM1 to NM4 turned on by adjusting the output voltage level. There is also. In this case, all threshold voltages at which the first to fourth NMOS transistors NM1 to NM4 are turned on must be set differently. The number of transistors turned on according to the voltage level output by the level generator 262a may be adjusted.

Node K2 is connected to the gate of fifth NMOS transistor NM5.

The second PMOS transistor PM2 and the fifth NMOS transistor NM5 are connected in series between a power supply voltage input terminal and a ground node. The second enable signal EN2 is input to the gate of the second PMOS transistor PM2.

The precharge control signal PRECH is output from the node K3, which is a connection point between the second PMOS transistor PM2 and the fifth NMOS transistor NM5.

The degree of turning on the fifth NMOS transistor NM5 of the signal generator 263 is adjusted according to the voltage output from the current control circuit 262 of the precharge controller 260 according to the embodiment of the present invention.

While not precharging, the second enable signal EN2 from the control logic 250 is input at a low level. Accordingly, the second PMOS transistor PM2 is turned on and a power supply voltage is input to the node K3. The precharge control signal PRECH is maintained at a high level.

Referring to FIG. 3, when the precharge control signal PRECH is at a high level, the PMOS transistor P of the precharge unit 223 of the page buffer 221 is kept turned off.

The control logic 250 outputs the low level first enable signal EN1 and the high level second enable signal EN2 for precharging the bit lines. The first PMOS transistor PM1 is turned on by the low level first enable signal EN1. At least one of the first to fourth NMOS transistors NM1 to NM4 is turned on according to the number of the first to fourth control voltages a1 to a4 output by the level generator 262a. Accordingly, the node K2 receives the resistance of the turned-on transistors among the first to fourth NMOS transistors NM1 to NM4 and the voltage distributed by the resistor R. The fifth NMOS transistor NM5 is turned on by the voltage of the node K2. The extent to which the fifth NMOS transistor NM5 is turned on depends on the voltage of the node K2.

In this case, the second PMOS transistor PM2 is turned off by the second enable signal EN2 having a high level.

When the second PMOS transistor PM2 is turned off, the voltage of the node K3 is discharged to the ground node through the fifth NMOS transistor N5.

The control logic 250 outputs some or all of the first to fourth control voltages a1 to a4 by the level generator 262a. The number of first to fourth control voltages a1 to a4 output by the level generator 262a is controlled by the control logic 250.

In addition, since the resistance value is changed according to the number of the first to fourth NMOS transistors NM1 to NM4 turned on, the voltage of the node K2 is changed. The degree to which the fifth NMOS transistor NM5 is turned on is adjusted according to the voltage of the node K2.

That is, the first to fourth NMOS transistors NM1 to NM4, together with the resistor R, serve as resistance components. Therefore, the voltage of the node K2 is changed according to the number of turned on among the first to fourth NMOS transistors NM1 to NM4.

As the number of turned-on transistors among the first to fourth NMOS transistors NM1 to NM4 increases, the resistance value between the node K2 and the ground node decreases. When the resistance value between the node K2 and the ground node decreases, the voltage of the node K2 also decreases. That is, the voltage of the node K2 is smaller as the number of transistors turned on among the first to fourth NMOS transistors NM1 to NM4 increases.

The smaller the voltage of the node K2 is, the smaller the degree that the fifth NMOS transistor NM5 is turned on. As a result, the speed at which the voltage is discharged to the node K3 becomes relatively slow.

The speed at which the precharge signal PRECH changes to a low level is also adjusted according to the speed at which the voltage of the node K3 is discharged. In this case, the precharge signal PRECH drops to a low level by being linearly changed by the voltage of the node K3 being linearly discharged by the fifth NMOS transistor NM5. Since the fifth NMOS transistor NM5 is to be turned on by the node K2 and the power supply voltage of the node K3 should not be discharged instantaneously, the fifth NMOS transistor NM5 has a relatively large size compared to other transistors. small.

When the precharge signal PRECH, which gradually decreases, the PMOS transistor P of the precharge unit 223 of the page buffer 221 of FIG. 3 is linearly turned on. As the PMOS transistor P is slowly turned on linearly, the voltage input to the bit line also gradually increases.

As the precharge voltage is gradually input to the bit line, the peak current generated at the bit line precharge becomes smaller.

FIG. 7A illustrates precharge control signals changed according to transistors turned on in the precharge control circuit, and FIG. 7B illustrates a degree of internal voltage drop as precharge control signals are input as shown in FIG. 7A.

7A and 7B, the change of the precharge control signal PRECH and the voltage drop are separately shown according to the number of transistors turned on among the first to fourth NMOS transistors NM1 to NM4 of FIG. 6.

If the control logic 250 controls the level generator 262a to output only the first control signal a1, only the first NMOS transistor NM1 is turned on. When only the first NMOS transistor NM1 is turned on, the voltage of the node K2 of the precharge control circuit 260 becomes relatively higher than when the two transistors are turned on.

Accordingly, the degree to which the fifth NMOS transistor NM5 is turned on is increased, and the speed at which the precharge control signal PRECH falls to a low level is increased.

When the precharge control signal PRECH drops to a low level quickly, the voltage drop increases.

On the contrary, if the control logic 250 controls the level generator 262a to output all of the first to fourth control voltages a1 to a4 so that all of the first to fourth NMOS transistors NM1 to NM4 are turned on, the node ( The voltage of K2) is relatively low, and the degree to which the fifth NMOS transistor NM5 is turned on is also small.

Accordingly, the precharge control signal PRECH is gradually changed to the low level. The slower the rate at which the precharge control signal PRECH changes to the low level, the smaller the degree of the voltage drop.

According to the above description with reference to FIGS. 7A and 7B, as the number of transistors turned on among the first to fourth NMOS transistors NM1 to NM4 increases, the rate at which the precharge control signal PRECH changes to a low level is increased. Slows down, and the degree to which the internal voltage drops momentarily decreases.

In FIG. 6, only the first to fourth NMOS transistors NM1 to NM4 are illustrated. However, in order to further slow down the rate at which the precharge control signal PRECH is lowered to a low level, the NMOS transistor is interposed between the node K2 and the ground node. Increasing the number of them is possible.

When the precharge control signal PRECH is controlled to be gradually lowered by the above operation, the voltage drop when the voltage is applied for the bit line precharge can be reduced, and the peak current can be reduced.

The operation of controlling the voltage level of the precharge control signal PRECH will now be described in detail.

8 is a timing diagram of control signals for explaining an operation of FIG. 6.

Referring to FIG. 8, the control logic 250 outputs a first enable signal EN1 at a high level and a second enable signal EN2 at a low level while the pre-charge operation is not performed.

Accordingly, the second PMOS transistor PM2 of FIG. 6 is kept turned on. Therefore, the precharge control signal PRECH is fixed at a high level.

In order to output the precharge control signal PRECH, the voltage control signal is first input to the level generator 262a to control the operations of the first to fourth NMOS transistors NM1 to NM4.

Before starting the precharge operation, the control logic 250 turns on all of the first to fourth NMOS transistors NM1 to NM4. Although the first to fourth NMOS transistors NM1 to NM4 are not necessarily turned on initially, the first to fourth NMOS transistors NM1 to NM4 may be used to prevent the voltage level of the precharge control signal PRECH from dropping rapidly. You need to do this to turn it on.

For the precharge, the control logic 250 first changes the second enable signal EN2 to a high level. Accordingly, since the power supply voltage applied to the node K3 is cut off, the precharge control signal PRECH is no longer maintained at the high level and may be gradually discharged (or discharged).

Next, the control logic 250 changes the first enable signal EN1 to a low level. Accordingly, the power supply voltage is input to the node K2. At the same time, the control logic 250 inputs a voltage control signal for controlling the voltage of the node K2 to the level generator 262a.

8 shows a timing diagram when only the first NMOS transistor NM1 is turned on. The control logic 250 inputs the voltage control signal to the level generator 262a so that only the first control signal a1 can be output at a high level.

Accordingly, the level generator 262a changes the first control signal a1 to the high level.

When the first enable signal EN1 is changed to the low level and the first control signal a1 is input to the high level, the first PMOS transistor PM1 and the first NMOS transistor NM1 are turned on. Accordingly, the voltage of the node K2 is determined.

The degree in which the fifth NMOS transistor NM5 is turned on is adjusted according to the voltage of the node K2, and accordingly, the voltage of the node K3 is discharged.

That is, as shown in FIG. 8, the precharge control signal PRECH is slowly lowered (SLOW PRECH1).

FIG. 8 also shows that the precharge control signal PRECH is discharged at a different slope when the precharge operation is performed once again after the precharge (SLOW PRECHE 2).

The control logic 250 outputs a voltage control signal such that the first and second NMOS transistors NM1 and NM2 are turned on, thereby increasing the voltage level of the second node K2, thereby increasing the precharge control signal PRECH. You can see that the control is quickly discharged.

On the other hand, in order to be able to adjust the voltage level of the second node (K2) more finely, instead of the resistor (R) of FIG. 6, a variable resistor is used, and the control logic 250 can control the resistance value. The precharge control circuit 260 can also be configured.

9 shows a precharge control circuit according to a second embodiment of the present invention.

In FIG. 9, the same reference numerals are used to designate a circuit having the same operation as that of FIG. 6.

Referring to FIG. 9, in the precharge control circuit 260 according to the second embodiment, the resistance R is changed to a variable resistor Ra as compared to FIG. 6, and the variable resistor Ra is a resistance control signal b. <0: 2>) changes the resistance value.

The resistance control signals b <0: 2> are output from the level generator 262a.

The level generator 262a receiving the voltage control signal from the control logic 250 may control the first to fourth control signals a1 to a4 and the resistance control signal b <0: to adjust the voltage of the second node K2. 2>).

In addition, since the resistance value of the variable resistor Ra is changed by the resistance control signal b <0: 2>, the voltage of the second node K2 is changed.

Therefore, the voltage level of the second node K2 may be more precisely controlled using only the first to fourth NMOS transistors NM1 to NM4.

On the other hand, the control logic 250 outputs the voltage control signal in accordance with the power supply voltage change and the temperature change.

10 is a block diagram schematically illustrating a voltage control signal output portion of the control logic.

Referring to FIG. 10, the control logic 250 may include a voltage detector 251, a temperature detector 252, an add / subtract circuit 253, a register 254, and a controller 255.

The voltage detector 251 detects whether a power supply voltage applied in an integrated circuit such as a semiconductor memory device is dropped and outputs a detection signal. The voltage interceptor 251 may use a circuit for detecting a change in the reference voltage and the power supply voltage using a comparator.

The temperature detector 252 outputs a detection signal according to a change in ambient temperature.

The detection signals output from the voltage detector 251 and the temperature detector 252 are input to the add / subtract circuit 253. The acceleration / subtraction circuit 253 determines how quickly the precharge control signal PRECH is to be discharged using the detection signals according to the voltage and temperature detection, and outputs the voltage detection signal according to the stored signal to the register 254. do.

The addition / subtraction circuit 253 outputs a voltage control signal according to the voltage and temperature change according to the characteristics of the transistor constituting the precharge unit 223.

Referring to FIG. 3, in the semiconductor memory device, the precharge unit 223 of the page buffer includes a PMOS transistor P connected between a power supply voltage and a second sensing node SO2. The degree to which P) is turned on in accordance with the power supply voltage change and the temperature change may vary. Therefore, the magnitude of the precharge voltage flowing into the second sensing node SO2 may vary.

Therefore, the addition / subtraction circuit 253 determines how quickly the precharge control signal PRECH is discharged according to the voltage drop and the temperature change in consideration of the characteristics of the PMOS transistor P, and accordingly the voltage control signal. Outputs

The voltage control signal temporarily stored in the register 254 is output to the level generator 262a in response to the control signal of the controller 255.

In addition, the control unit 255 outputs a control signal for controlling the operations of the addition / subtraction circuit 253 and the register 254, while the first and second enable signals EN1 and EN2 are performed when the precharge operation is performed. )

According to the voltage control signal, the speed at which the precharge control signal PRECH is discharged is adjusted to enable the precharge voltage to be flexibly supplied to the ambient temperature and the voltage change.

As described above, the precharge control circuit according to the embodiment of the present invention shown in FIG. 6 or 9 is not only used for bit line precharge control of a semiconductor memory device, but is applied to a circuit requiring precharge in an integrated circuit. The higher the loading of the line or node to be precharged, the greater the effect. In addition, by controlling the precharge speed according to the ambient temperature and voltage changes, it is possible to reduce the loading and enable an effective precharge.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

260: precharge control circuit 262: current control circuit
263: signal generator

Claims (16)

A precharge voltage providing unit configured to output a precharge voltage according to a voltage level of the precharge control signal;
A voltage generator configured to output an operating voltage for controlling a voltage level of the precharge control signal in response to a first enable signal and a voltage control signal; And
In response to the second enable signal, the voltage of the precharge control signal is fixed to a predetermined level, and when the second enable signal is disabled, the voltage level of the precharge control signal is set to the voltage level of the operating voltage. A precharge control circuit comprising a signal generator for linearly changing according to the slope determined by the. The method of claim 1,
And the signal generation unit linearly lowers and outputs the voltage level of the precharge control signal according to a slope determined by the voltage level of the operating voltage. The method of claim 1,
The voltage generator,
A level generator for outputting one or more control signals set according to the voltage control signal;
A first switching element coupled between a power input terminal and a first node, the first switching element operative in response to the first enable signal; And
And a plurality of second switching elements connected in parallel between the first node and the ground node, each of which is turned on by one or more control signals. The method of claim 3, wherein
The voltage generator,
And a variable resistor connected between the first switching element and the first node, wherein the variable resistor is changed in response to a resistance control signal output by the level generator. . The method of claim 4, wherein
The signal generator,
A third switching element connected between a power supply voltage and a second node and operative in response to the second enable signal;
A fourth switching element connected between the second node and a ground node, the fourth switching element being turned on in accordance with a voltage level of the first node;
The precharge control signal is outputted from the second node, and a speed at which the voltage level of the precharge control signal drops is changed according to the voltage level of the first node. 6. The method of claim 5,
The higher the voltage level of the first node, the faster the voltage level of the precharge control signal is lowered. An integrated circuit comprising a plurality of circuits,
A precharge voltage circuit for providing a precharge voltage changed according to a voltage level of the precharge control signal;
A precharge control circuit for changing and outputting a voltage level of the precharge control signal to linearly change a voltage level of the precharge voltage in response to a first and second enable signal and a voltage control signal; And
And a control logic that outputs the first and second enable signals for precharge operation and outputs the voltage control signal in response to changes in ambient temperature and power voltage levels. The method of claim 7, wherein
And the voltage level of the precharge control signal of the precharge control circuit drops linearly. The method of claim 7, wherein
The precharge control circuit,
A voltage generator configured to output an operating voltage for controlling the voltage level of the precharge control signal in response to the first enable signal and the voltage control signal; And
In response to the second enable signal, the voltage of the precharge control signal is fixed to a predetermined level, and when the second enable signal is disabled, the voltage level of the precharge control signal is set to the voltage level of the operating voltage. And a signal generator for linearly changing the inclination determined by the slope. The method of claim 7, wherein
The voltage generator,
A level generator for outputting one or more control signals set according to the voltage control signal;
A first switching device connected between a power supply voltage input terminal and a first node and turned on in response to the first enable signal; And
And a plurality of second switching elements connected in parallel between the first node and the ground node, each of which is turned on by one or more control signals output by the level generator. The method of claim 10,
And a variable resistor connected between the first switching element and the first node, wherein the variable resistor changes a resistance value in response to a resistance control signal output by the level generator. 12. The method of claim 11,
The signal generator,
A third switching element connected between the power supply voltage input terminal and the second node and operating in response to the second enable signal;
A fourth switching element connected between the second node and the ground node, the fourth switching element being turned on in accordance with the voltage of the first node;
And a rate at which the voltage of the precharge control signal drops according to the voltage of the first node and the precharge control signal is output from the second node. The method of claim 10,
The first switching element is a PMOS transistor, and the second switching elements are NMOS transistors. The method of claim 10,
And the higher the voltage of the first node is, the faster the voltage of the precharge control signal drops. The method of claim 7, wherein
The voltage generator,
A level generator for outputting a voltage set according to the voltage control signal;
A first switching device connected between the power supply voltage input terminal and the first node and turned on in response to the first enable signal; And
A plurality of fifth switching elements connected in parallel between the first node and the ground node and turned on according to a voltage level at the output of the level generator, wherein each of the fifth switching elements has a threshold voltage; Integrated circuits characterized in that different. The method of claim 7, wherein
The control logic is,
A voltage detector for detecting a change in the power supply voltage and outputting a first detection signal according to a detection result;
A temperature sensor for detecting a change in the ambient temperature and outputting a second detection signal according to a detection result;
An addition and subtraction circuit unit generating the voltage control signal according to the first and second detection signals; And
And a controller configured to output the first and second enable signals and to control an output of the voltage control signal generated by the add / subtract circuit.

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