KR20110122939A - Non-polar semiconductor device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A non-polar semiconductor device and a manufacturing method thereof are provided to prevent production costs or a produce time excessively from being increased by not forming a insulation pattern during epi-layer growth. CONSTITUTION: A sapphire substrate(21) includes a mesa(23) with C-side sidewall(23a) in an upper side. A buffer layer(27) with a void(27a) is formed on the sapphire substrate. A first semiconductor layer(31) is formed on the buffer layer. A second semiconductor layer(35) is formed on the first semiconductor layer. A multi-quantum well structure(33) is placed between the first semiconductor layer and the second semiconductor layer.

Description

Non-polar semiconductor device and method for manufacturing same {NON-POLAR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a non-polar semiconductor device and a method of manufacturing the same.

Gallium nitride compounds are recognized as essential materials for high power and high performance optical and electronic devices. Currently, commercially available GaN-based semiconductor devices are generally manufactured by growing a c-plane GaN-based epi layer on a c-plane sapphire substrate using a technique such as MBE, MOVPE or HVPE. However, the c-plane GaN has a problem in that the luminescence recombination rate is reduced by the internal electric field formed by the spontaneous polarization and the piezoelectric polarization, thereby lowering the internal quantum efficiency.

Therefore, in order to solve the decrease in internal quantum efficiency due to polarization, various techniques for growing an a-plane or m-plane GaN epitaxial layer have been studied. For example, much research is being conducted on techniques for growing nonpolar or semipolar GaN using substrates such as r-plane sapphire, m-plane sapphire, a-plane SiC, m-plane SiC, or LiAl ₂ O ₃ . However, non-polar or semi-polar GaN grown on dissimilar substrates have a problem of low internal quantum efficiency due to very high density of threading dislocations and stacking faults.

On the other hand, there is an attempt to grow high quality nonpolar or semipolar GaN using a nonpolar or semipolar GaN substrate, but it is difficult to secure a commercially available sized GaN substrate, resulting in excessive increase in the cost of semiconductor device production. For this reason, it is difficult to commercialize a semiconductor device using a nonpolar or semipolar GaN substrate in reality. In addition, a technique has been attempted to grow non-polar GaN on a heterogeneous substrate, form an insulating pattern thereon, and grow a non-polar or semi-polar GaN epitaxial layer using a side growth (LEO) technique. However, since the insulating pattern cannot be formed in-situ, the substrate must be taken out of the reactor to form the insulating pattern during epilayer growth. In addition, since after forming the insulating pattern, the substrate is loaded in the reactor again and the epitaxial growth conditions must be set again, so that the process time is excessively increased, making it difficult to commercialize.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonpolar semiconductor device having improved internal quantum efficiency by a high quality nonpolar GaN-based epi layer and a method of manufacturing the same.

Another object of the present invention is to provide a nonpolar semiconductor device and a method of manufacturing the same that can prevent excessive increase in production cost or production time.

Another object of the present invention is to provide a non-polar semiconductor device using a sapphire substrate can be easily secured and a method of manufacturing the same.

According to one aspect of the present invention, a nonpolar semiconductor element is provided. The nonpolar semiconductor device includes a sapphire substrate, the sapphire substrate includes mesas each having a c-plane sidewall on an upper surface thereof. Meanwhile, a buffer layer may be located on the sapphire substrate. The buffer layer may include a void therein. A first semiconductor layer may be positioned on the buffer layer, and a second semiconductor layer may be positioned on the first semiconductor layer. In addition, a multi-quantum well structure may be interposed between the first semiconductor layer and the second semiconductor layer.

The upper surface of the sapphire substrate is not particularly limited as long as it is a surface perpendicular to the c-plane, and may be, for example, a-plane or m-plane. In particular, the top surface of the sapphire substrate may be an a-plane, and in this case, the buffer layer (and the first and second semiconductor layers and the multi-quantum well structure) on the sapphire substrate may be an m-plane gallium nitride-based epi layer.

Meanwhile, c-plane sidewalls of adjacent mesas may be parallel to each other. The mesas may be arranged in a specific pattern. For example, the mesas may be arranged in a stripe pattern by trenches that expose c-plane sidewalls. Here, the void may be located in the trench. The voids may be elongated along the sidewalls of the mesas. Alternatively, the mesas may be arranged in an island pattern by trenches. Here, the voids may be located between the c-plane sidewalls of the mesas adjacent to each other, and may be spaced apart from each other.

Meanwhile, the buffer layer may be GaN. In addition, the buffer layer may include an interface where the N-plane and Ga-plane of GaN meet. In addition, the interface may be perpendicular to the top surface of the buffer layer.

The buffer layer may have an a-plane or an m-plane on its top surface. In particular, an upper surface of the sapphire substrate may be an a-plane, and an upper surface of the buffer layer may be an m-plane.

In some embodiments, the first semiconductor layer may include a superlattice layer in which InGaN and GaN are alternately stacked. The superlattice layer further improves the crystal quality of the multi-quantum well structure and assists current dispersion in the first semiconductor layer.

According to another aspect of the present invention, a method of manufacturing a nonpolar semiconductor device is provided. The method includes preparing a sapphire substrate including mesas, each having c-plane sidewalls on its top surface. A buffer layer is grown on the sapphire substrate. The buffer layer may include a void therein. Meanwhile, a first semiconductor layer, a multi-quantum well structure, and a second semiconductor layer may be grown on the buffer layer.

According to the present invention, since the buffer layer is predominantly grown on the c-plane sidewalls of the mesas of the sapphire substrate, and the sidewalls of the buffer layer are grown on the sapphire substrate, a high-quality nonpolar GaN epitaxial layer having a low defect density can be grown. Can be. Accordingly, it is possible to provide a nonpolar semiconductor device having improved internal quantum efficiency. Furthermore, since a sapphire substrate which can be easily secured is used and there is no need to form an insulating pattern during epitaxial growth, a nonpolar semiconductor element capable of preventing excessive increase in production cost or production time can be provided.

1 to 4 are cross-sectional views illustrating a method of manufacturing a non-polar semiconductor device according to an embodiment of the present invention.
5 is a plan view of a sapphire substrate for explaining a non-polar semiconductor device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention to those skilled in the art will fully convey. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 to 4 are cross-sectional views illustrating a method of manufacturing a non-polar semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a sapphire substrate 21 is provided. The substrate 21 has a plurality of mesas 23 on the upper surface, each of which has a c-plane (0001) sidewall 23a. The upper surface 23b of the sapphire substrate 21 is not particularly limited as long as it is a surface perpendicular to the c-plane, and may be, for example, a-plane (11-20) or m-plane (1-100). In particular, the top surface 23b of the sapphire substrate 21 may be a-plane, as shown.

The sapphire substrate 21 having mesas 23 may be formed, for example, by forming an e-planar substrate having a flat top surface, for example, by forming an elongated trench 21a in the [1-100] direction. The c-plane sidewalls 23a of the mesas are exposed by the trench 21a. In this case, the mesas 23 are arranged in a stripe pattern, and the c-plane sidewalls of the adjacent mesas 23 are formed parallel to each other.

Referring to FIG. 2, a buffer layer 25 is grown on the sapphire substrate 21. The buffer layer 25 may be GaN, for example. The buffer layer 25 first grows predominantly on the c-plane sidewall 23a of the mesa 23. In particular, in the GaN buffer layer 25, the Ga-plane 25a is predominantly grown on the c-plane sidewall 23a, and the growth of the N-plane is suppressed. Therefore, as shown, growth is predominantly on one side of both c-planes of the mesa 23a, and growth on the other side is suppressed.

Meanwhile, side growth of the buffer layer 25 may be performed on the upper surface 23b of the mesa 23. In the lateral growth, the Ga-plane 25a and the N-plane 25b may be simultaneously processed, but the growth of the Ga-plane may be superior to the N-plane growth depending on the growth conditions. In particular, stacking defects in the buffer layer 25 can be reduced by predominantly controlling the growth of the Ga-plane.

On the sapphire substrate 21 whose upper surface is the a-side, the buffer layer 25 is grown on the upper surface 25c to the m-side 1-100. Meanwhile, a nuclear layer (not shown) may be formed before the buffer layer 25 is grown.

Referring to FIG. 3, as the growth of the buffer layer 25 proceeds, the Ga-plane and the N-plane meet each other to form a continuous buffer layer 27. Thus, the buffer layer 27 may include an interface 27b between the Ga-plane and the N-plane. In addition, since the buffer layer 25 is predominantly grown on the sidewalls 23a of the mesa 23, voids 27a may be formed in the trench 21a. The voids 27a may be elongated along the sidewalls of the mesa 23 having a stripe shape.

Referring to FIG. 4, a first semiconductor layer 31, a multi-quantum well structure 33, and a second semiconductor layer 35 are formed on the buffer layer 27. The first semiconductor layer, the multi-quantum well structure, and the second semiconductor layer may be formed of a gallium nitride-based semiconductor layer, and may be formed using a technique such as metal organic chemical vapor deposition.

The first semiconductor layer 31 and the second semiconductor layer 35 may be a single layer or multiple layers. In particular, the first semiconductor layer 31 may include a superlattice layer in which GaN / InGaN are alternately stacked. .

The first semiconductor layer 31 and the second semiconductor layer 35 may be n-type and p-type or p-type and n-type. Preferably, the first semiconductor layer 31 is n-type and the second semiconductor layer 35 is p-type.

Thereafter, the semiconductor layers 31, 33, 35 and the substrate 21 are divided into individual chips to complete a semiconductor device. The n- and p-electrodes may be formed before dividing into individual chips, and the mesas may be formed by etching the semiconductor layers 31, 33, and 35.

According to the present embodiment, since the buffer layer 25 grows predominantly on the c-plane sidewall of the mesa 23 of the sapphire substrate 21 and laterally grows on the upper surface 23b of the mesa 23, It is possible to reduce the actual potential, thus providing a high quality semiconductor device. Further, the stacking defect density can be reduced by predominantly controlling the growth of the Ga-plane during lateral growth. In addition, in this embodiment, by using the sapphire substrate 21 which can be easily secured, it is possible to prevent the production cost and production time of the nonpolar semiconductor element from being excessively increased.

Hereinafter, a nonpolar semiconductor device according to an embodiment of the present invention will be described in detail.

Referring back to FIG. 4, the nonpolar semiconductor device according to the present embodiment includes a sapphire substrate 21 and a buffer layer 27. In addition, the first semiconductor layer 31, the multi-quantum well structure 33, and the second semiconductor layer 35 may be disposed on the buffer layer 27.

The sapphire substrate 21 includes mesas 23 having a c-plane sidewall 23a, as described with reference to FIG. 1. The mesas 23 may be arranged in a stripe pattern in which a c-plane sidewall is exposed by the trench 21a. The c-plane sidewalls 23a of the mesas 23 are arranged parallel to each other.

The buffer layer 27 may be formed of GaN and may include a void 27a therein. The void 27a may be located in the trench between the mesas 23 and may have an elongated shape along the c-plane sidewall of the mesa 23. The voids 27a may also be formed at regular intervals from each other to scatter light directed toward the sapphire substrate 21 side. The buffer layer 27 may also include an interface 27b between the Ga-plane and the N-plane. The interface 27b may be perpendicular to the top surface of the buffer layer 27 or the top surface of the substrate 21.

The first semiconductor layer 31 is positioned on the buffer layer 27. Meanwhile, a second semiconductor layer 35 may be positioned on the first semiconductor layer 31, and a multi-quantum well structure may be interposed between the first semiconductor layer 31 and the second semiconductor layer 35. have. The first semiconductor layer 31 and the second semiconductor layer 35 may be formed of a gallium nitride-based compound semiconductor layer. In addition, the first semiconductor layer 31 may include a superlattice layer in which GaN / InGaN are alternately stacked. The multiangja well structure 33 is formed in a structure in which a barrier layer and a well layer are alternately stacked. For light emitting diodes that emit light of a particular wavelength, the material of the well layer is chosen to emit light. For example, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN.

5 is a plan view illustrating a non-polar semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 5, the arrangement of the mesas 53 on the sapphire substrate 51 is different from that of the non-polar semiconductor device according to the present embodiment as compared to the non-polar semiconductor device described with reference to FIGS. 1 to 4.

That is, in the foregoing non-polar semiconductor device, the mesas 23 on the upper surface of the substrate 21 are described as being arranged in a stripe pattern. In the present embodiment, the mesas 53 are the upper surface of the sapphire substrate 51. It is arranged in a land pattern.

Mesas 53 have c-plane (0001) sidewalls 53a exposed by trench 53. In addition, the c-plane sidewalls 53a of adjacent mesas 53 may be located parallel to each other. In addition, as shown, the mesas 53 may have a m-side (1-100) side wall, the upper surface may be a-plane. In the present embodiment, the mesas 53 may have a square pillar shape, but are not limited thereto. For example, the mesas 53 may have a square pyramid shape.

The mesas 53 may be arranged, for example, in an island pattern in which mesas in the first column A and mesas in the second column B are alternately repeated. That is, the second column B is disposed between the first column A and the third column A. FIG. Here, the mesas of the first row are spaced apart from the mesas of the third row by a predetermined distance in the [0001] direction, and the c-plane, that is, the (0001) planes are parallel to each other. Meanwhile, the mesas in the second row may be located at the center of the area surrounded by the mesas in the two first rows and the mesas in the two third rows, respectively. By this structure, the mesas can be arranged in a honeycomb-like structure, for example.

On the other hand, the space between the mesas in the first row and the mesas in the second row adjacent thereto may only have trenches without other mesas. In addition, as shown by a dotted line, a line connecting the side of the mesas of the first row and the side of the mesas of the second row may be a straight line.

The final buffer layer formed thereon by this mesa arrangement will have a flat top surface of the m-plane, and may include voids regularly arranged on the sidewalls of each mesa in the trench 55.

Claims (15)

A sapphire substrate including mesas each having a c-plane sidewall on an upper surface thereof;
A buffer layer disposed on the sapphire substrate and including a void therein;
A first semiconductor layer on the buffer layer;
A second semiconductor layer on the first semiconductor layer; And
A non-polar semiconductor device comprising a multi-quantum well structure interposed between the first semiconductor layer and the second semiconductor layer. The nonpolar semiconductor device of claim 1, wherein an upper surface of the sapphire substrate is an a-plane. The nonpolar semiconductor device of claim 1, wherein c-plane sidewalls of adjacent mesas are parallel to each other. 4. The nonpolar semiconductor device of claim 3, wherein the mesas are arranged in a stripe pattern by trenches that expose c-plane sidewalls. The nonpolar semiconductor device of claim 4, wherein the void is located in the trench. The nonpolar semiconductor device of claim 3, wherein the mesas are arranged in an island pattern by a trench. The nonpolar semiconductor device of claim 6, wherein the void is located between c-plane sidewalls of mesas adjacent to each other. The nonpolar semiconductor device of claim 1, wherein the buffer layer is GaN. The nonpolar semiconductor device of claim 8, wherein the buffer layer comprises an interface where an N-plane and a Ga-plane of GaN meet. The nonpolar semiconductor device of claim 9, wherein the interface is perpendicular to an upper surface of the buffer layer. The nonpolar semiconductor device of claim 1, wherein the buffer layer has an m-plane on an upper surface thereof. The nonpolar semiconductor device of claim 1, wherein the first semiconductor layer includes a superlattice layer in which InGaN and GaN are alternately stacked. Preparing a sapphire substrate including mesas each having a c-plane sidewall on an upper surface thereof;
Growing a buffer layer on the sapphire substrate, the buffer layer including voids therein;
Growing a first semiconductor layer on the buffer layer;
Growing a multi-quantum well structure on the first semiconductor layer;
A method of manufacturing a non-polar semiconductor device comprising growing a second semiconductor layer on the multi-quantum well structure. The method of claim 13, wherein an upper surface of the sapphire substrate is an a-plane. The method of claim 13, wherein the mesas are arranged in a stripe pattern or an island pattern.

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