KR20110121161A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20110121161A
KR20110121161A KR1020100040626A KR20100040626A KR20110121161A KR 20110121161 A KR20110121161 A KR 20110121161A KR 1020100040626 A KR1020100040626 A KR 1020100040626A KR 20100040626 A KR20100040626 A KR 20100040626A KR 20110121161 A KR20110121161 A KR 20110121161A
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KR
South Korea
Prior art keywords
pull
driver
pad
wiring
power line
Prior art date
Application number
KR1020100040626A
Other languages
Korean (ko)
Inventor
안정윤
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100040626A priority Critical patent/KR20110121161A/en
Publication of KR20110121161A publication Critical patent/KR20110121161A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention provides a semiconductor device having a driving circuit in which wiring is most effectively laid out. To this end, the present invention is a pad; A pull-up driver region allocated to one side of the pad to provide a pull-up signal to the pad; A pull-down driver assigned to the other side of the pad for providing a pull-down signal to the pad; A first power line disposed at one side of the pad, the pull-up driver region and the pull-down driver region; A pull-up power line formed of the same wiring layer as the power line and connecting the power line and the pull-up driver area to provide power to the pull-up driver area; A pull-down power line formed of the same wiring layer as the power line and connecting the power line and the pull-down driver area to provide power to the pull-down driver area; And a wiring line different from the power line and having a test wire for providing a test signal to the pull-up driver region.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a wiring layout of a driver circuit of a semiconductor device.

The semiconductor device is completed by forming a circuit designed on a silicon wafer, then separating the wafer by net die and carrying out a package. The layout of a well-designed circuit on a wafer is called a layout. In general, a MOS transistor is disposed on a silicon wafer, and a wiring connecting each node of the MOS transistor is disposed thereon.

Initially, when manufacturing a semiconductor device, a single wiring layer was used to connect nodes with predetermined nodes of each MOS transistor and other devices. However, as the circuit becomes complicated, at least two or more layers of wiring are required. In recent years, semiconductor devices are manufactured using wirings of three or more layers.

On the other hand, a driving circuit for driving an output terminal having a high load for a signal input from various circuits constituting a semiconductor device is widely used. The driving circuit has a high load on the output stage, which pulls up or pulls down the output stage while consuming a lot of current. Since the driving circuit consumes more current than other circuits of the semiconductor device, the layout of the wiring for supplying power to the driving circuit is very important.

The present invention provides a semiconductor device having a driving circuit in which wiring is most effectively laid out.

The present invention pad; A pull-up driver region allocated to one side of the pad to provide a pull-up signal to the pad; A pull-down driver assigned to the other side of the pad for providing a pull-down signal to the pad; A first power line disposed at one side of the pad, the pull-up driver region and the pull-down driver region; A pull-up power line formed of the same wiring layer as the power line and connecting the power line and the pull-up driver area to provide power to the pull-up driver area; A pull-down power line formed of the same wiring layer as the power line and connecting the power line and the pull-down driver area to provide power to the pull-down driver area; And a wiring line different from the power line and having a test wire for providing a test signal to the pull-up driver region.

The power line may be arranged on the other side of the pad, the pull-up driver region, and the pull-down driver region.

In addition, the pull-down power wiring and the pull-up power wiring is characterized in that the symmetry around the pad.

The pull-up driver region may include a pull-up driver for generating the pull-up signal and a pull-up pre-driver for receiving a data signal provided from a core region and providing a pull-up pre-driver signal to the pull-up driver. .

According to the present invention, it is possible to more stably supply power to a pull-up driver region and a pull-down driver region for providing a signal to a pad of a semiconductor device value.

1 is a wiring layout diagram of a driver circuit of a semiconductor device for explaining the present invention.
2 is a wiring layout diagram of a driver circuit of a semiconductor device according to an embodiment of the present invention.
3 is a circuit diagram of an output region of the semiconductor device shown in FIG.
4 is a block diagram of an output region of the semiconductor device shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

The present invention solves a problem in that power supply to an output driver is not smooth when a data signal is input from a semiconductor device, particularly a memory device, and a pull up or pull down signal is output through an output pad. The present invention is applicable to all semiconductor devices, but particularly to semiconductor memory devices.

The semiconductor device includes a plurality of output drivers for outputting a plurality of data signals. Each output driver receives a power supply voltage VDDQ and a ground voltage VSSQ to pull up or pull down the output stage. However, in general, since the power supply voltage VDDQ and the ground voltage VSSQ are not smoothly supplied to the output driver, the amount of power supplied to the output driver is different, resulting in an RTT mismatch.

Recently, in order to reduce costs by reducing process steps, a trend is to manufacture a double layer metal (DLM) structure made of triple layer metal (TLM), which uses three layers of wires when manufacturing a semiconductor device. As a result, there is no power supply using the existing fourth wiring M3 and layout of the wiring M2 for providing the power supply voltage VDDQ and the ground voltage VSS is difficult due to the space constraint between the pad and the pad. . Therefore, when the power supply voltage VDDQ and the ground voltage VSS are provided to the output driver by using the wiring M2, the possibility of RTT mismatch is released.

In order to eliminate the RTT mismatch, in the present invention, the wiring for the test mode used for the output driver is changed from the third wiring M2 to the first wiring M1. Here, it is assumed that the semiconductor device uses three wirings M0, M1, and M2.

1 is a wiring layout diagram for a driver circuit of a semiconductor device for explaining the present invention.

1, a pull-up driver region 11 and a pull-down driver region 12 are allocated to adjacent regions of the pad 10, and the pull-up driver region 11 and the pull-down driver region are shown. The wirings 14a and 14b for the power supply voltage and the wirings 13a and 13b for the ground voltage are arranged in the adjacent regions of the 12 and the pad 10. In addition, a wiring 14c for providing a power supply voltage and a wiring 14d for providing a ground voltage are arranged in the pull-up driver region 11, and a wiring 14d for providing a power supply voltage in the pull-down driver region 12. ), A wiring 13d for providing a ground voltage is arranged. In addition, the wirings 15a and 15b for the test are arranged in the pull-up driver region 11 and the pull-down driver region 12, respectively. Here, the wirings 13a, 13b, 13c, and 13d for supplying the ground voltage and the wirings 14a, 14b, 14d, and 14d for supplying the power voltage are all implemented using the third wiring layer M2. 15a and 15b are implemented using the third wiring layer M2.

In the case of the pull-up driver 11, although the wirings 13a and 13b for the power supply voltage are disposed close to the pad 10, the wiring 13c for providing the ground voltage of the pull-up driver 11 itself is thin. In the center region of the pull-up driver 11, the resistance value of the wiring 13c is increased. In the case of the pull-down driver 12, since there is no wiring for providing a power supply voltage on the upper side, the wiring 14d for providing the power supply voltage greatly increases in resistance upward. Therefore, there is an RTT mismatch depending on the arrangement of the wirings providing the power supply voltage and the ground voltage.

2 is a wiring layout diagram of a driver circuit of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2, the wiring layout diagram of the driver circuit of the semiconductor device according to the embodiment of the present invention is similar to that shown in FIG. Here again, the pull-up driver area 210 and the pull-down driver area 220 are allocated to the adjacent areas of the pad 20, and the pull-up driver area 210, the pull-down driver area 220, and the adjacent areas of the pad 20 are also provided. The wirings 24a and 24b for the power supply voltage and the wirings 23a and 23b for the ground voltage are arranged in this. In addition, a wiring 24c for providing a power supply voltage and a wiring 24d for providing a ground voltage are disposed in the pull-up driver region 210, and a wiring 24d for providing a power supply voltage in the pull-down driver region 220. ), A wiring 23d for providing a ground voltage is arranged. In addition, the wirings 25a and 25b for the test are disposed in the pull-up driver region 210 and the pull-down driver region 220, respectively.

However, in the semiconductor device shown in FIG. 2, the wirings 23a, 23b, 23c, and 23d for supplying the ground voltage and the wirings 24a, 24b, 24d, and 24d for supplying the power supply voltage all connect the third wiring layer M2. The wirings 25a and 25b for the test were implemented using the first wiring layer M0.

In the semiconductor device according to the present exemplary embodiment, the wirings 25a and 25b (wiring provided with a DC signal irrespective of timing) for the test mode using the conventional third wiring M2 are changed to the first wiring M0. Instead, power through the third wiring M2 can be further supplied to the pull-up driver region 210 and the pull-down driver region 220. That is, as shown in FIG. 2, the width of the wirings providing the power supply voltage VDDQ and the ground voltage VSS in the vertical direction is increased. Therefore, more stable power can be supplied to the pull-up driver region 210 and the pull-down driver region 22, thereby reducing the Rtt mismatch.

Even when the wiring resistance is relatively large as the first wiring M0 as a wiring for transmitting a DC signal irrespective of the operation timing when the semiconductor device is operated, there is no problem in the operation of the semiconductor device. Through this, the space for arranging the second wiring M2 is secured to thicken the wiring providing the power supply voltage and the ground voltages VDDQ and VSS, thereby providing more stable power to the driver circuit. The resistance of can reduce the RTT mismatch.

FIG. 3 is a circuit diagram of an output region of the semiconductor device shown in FIG.

Referring to FIG. 3, a pull-up driver 21 for transmitting a pull-up signal to the pad 20, a pull-down driver 22 for transmitting a pull-down signal to the pad 20, and a semiconductor are provided in an output area of the semiconductor device. A pull-up predriver 31 for receiving a data signal from the core region of the memory device and providing a pull-up pre-driver signal to the pull-up driver 21, and a pull-down driver receiving a data signal from the core region of the semiconductor memory device ( 22, a pulldown predriver 32 is provided for providing a pulldown predriver signal.

Here, the pull-up driver 21 and the pull-up predriver 31 are disposed in the pull-up driver region 210, and the pull-down driver 22 and the pull-down predriver 32 are disposed in the pull-down driver region 220. In addition, a ZQ adjusting unit 30 for performing a ZQ calibration operation is disposed in the output region of the semiconductor device.

4 is a block diagram of an output region of the semiconductor device shown in FIG.

Referring to FIG. 4, a pull-up driver 21 is disposed on one side of the pad 20 and a pull-down driver 22 is disposed on the other side of the pad 20 in the output area of the semiconductor device. A pull-up predriver 31 is disposed at one side of the pull-up driver 21, and a pull-down predriver 32 is disposed at one side of the pull-down driver 22.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. Will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims (4)

pad;
A pull-up driver region allocated to one side of the pad to provide a pull-up signal to the pad;
A pull-down driver assigned to the other side of the pad for providing a pull-down signal to the pad;
A first power line disposed at one side of the pad, the pull-up driver region and the pull-down driver region;
A pull-up power line formed of the same wiring layer as the power line and connecting the power line and the pull-up driver area to provide power to the pull-up driver area;
A pull-down power line formed of the same wiring layer as the power line and connecting the power line and the pull-down driver area to provide power to the pull-down driver area; And
And a test wiring for providing a test signal to the pull-up driver region.
The method of claim 1,
And the power line is disposed on the other side of the pad, the pull-up driver region, and the pull-down driver region.
The method of claim 1,
And the pull-down power wiring and the pull-up power wiring are symmetric about the pad.
The method of claim 1
The pull up driver area
And a pull-up pre-driver for generating the pull-up signal and a pull-up pre-driver for receiving a data signal provided from a core region and providing a pull-up pre-driver signal to the pull-up driver.
KR1020100040626A 2010-04-30 2010-04-30 Semiconductor device KR20110121161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100040626A KR20110121161A (en) 2010-04-30 2010-04-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100040626A KR20110121161A (en) 2010-04-30 2010-04-30 Semiconductor device

Publications (1)

Publication Number Publication Date
KR20110121161A true KR20110121161A (en) 2011-11-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100040626A KR20110121161A (en) 2010-04-30 2010-04-30 Semiconductor device

Country Status (1)

Country Link
KR (1) KR20110121161A (en)

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