KR20110120469A - Method of operating a semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A method of operating a semiconductor memory apparatus is provided to minimize the interference such as the threshold voltage rising of memory cells in a target page by the programming of a next page adjacent to a target page. CONSTITUTION: In a method of operating a semiconductor memory apparatus, an LSB program operation is performed(S301). An MSB program operation of a word line corresponding to a previous page is performed. The LSB program operation of a second word line corresponding to a next page is performed(S303). It is confirmed whether the LSB data of memory cells connected to the first word line is changed(S305). An MSB program operation is performed(S307). The threshold voltage of a part of memory cells is increased to a second threshold voltage level. The threshold voltage of rest memory cells is raised to the third threshold voltage level. A memory cell in which MSB data is changed is detected(S309). The MSB program operation is performed(S315).

Description

Method of operating a semiconductor memory apparatus

The present invention relates to a method of operating a semiconductor memory device, and more particularly, to a method of operating a semiconductor memory device for improving reliability of an operation for storing data.

A write operation (or a program operation) is performed to store data in the semiconductor memory device, a read operation is performed to output data, and an erase operation is performed to delete data.

In the case of a flash memory device, a threshold voltage of a memory cell is changed according to data stored therein, and the threshold voltage is changed to one of several levels according to the number of bits of data stored in one memory cell.

1A and 1B are graphs for explaining levels of threshold voltages depending on data stored in a memory cell.

Referring to FIG. 1A, in order to store data in a memory cell, the memory cell is initialized to an erase state in which '11' data is stored. In order to store 2-bit data 11, 01, 10, or 00 including LSB data and MSB data in one memory cell, an LSB program operation and an MSB program operation should be performed, respectively.

First, in order to store '10' or '00' data in a memory cell, LSB data should be changed from '1' to '0'. To this end, the LSB program operation is performed, and the threshold voltages of the memory cells in which '10' or '00' data are stored are higher than 0V by the LSB program operation.

Referring to FIG. 1B, in order to store '01' or '00' data in a memory cell, an MSB program operation should be performed to change the MSB data from '1' to '0'. By the MSB program operation, the threshold voltage of the memory cell in which the '11' data is stored increases to the first threshold voltage level PV1 higher than the first verification voltage Vpv1 and the MSB data stored in the memory cell is changed from '1' to ' The value '01' is stored in the memory cell. In addition, the threshold voltage of the memory cell storing the '10' data rises to the third threshold voltage level PV3 higher than the third verification voltage Vpv3 and the MSB data stored in the memory cell is changed from '1' to '0'. '00' data is stored in the memory cell. In the case of the memory cell in which '10' data is stored, the threshold voltage rises to the second program level PV2 higher than the second verification voltage Vpv2 without changing the data.

In the process of performing the MSB program operation, a threshold voltage of a memory cell (hereinafter, referred to as a first memory cell) in which '01' data is stored is first raised to a first threshold voltage level PV1 and '00' data is stored. The threshold voltage of the memory cell (hereinafter, referred to as a third memory cell) is raised to the third threshold voltage level PV3 at the latest. For this reason, even if the threshold voltage of the first memory cell is increased to the first threshold voltage level PV1, the MSB program operation continues to raise the threshold voltage of the third memory cell to the third threshold voltage level PV3. . As a result, an interference limit is generated in the first memory cells so that the first width W1 in which the threshold voltages of the first memory cells are distributed is widened. The second width W2 in which the threshold voltages of the memory cells (hereinafter, referred to as the second memory cell) in which the '10' data is stored is smaller than the first width W1 and the threshold voltages of the third memory cells are distributed. 3 width W2 is narrower than 2nd width W2.

Such interference occurs in memory cells included in the same page. However, even when performing the MSB program operation of the memory cells included in the next page, interference occurs in the memory cells of the page where the MSB program operation is already completed, and thus the widths of the threshold voltages become wider.

Since the interference has the greatest influence on the threshold voltages of the first memory cells, the first width W1 in which the threshold voltages of the first memory cells are distributed is greatly widened. As a result, an error may be generated in which the data stored in the first memory cell is recognized as '10' which is not '01'.

The present invention provides a method of operating a semiconductor memory device that can prevent an error from occurring due to an interference phenomenon during a program operation for data storage.

A method of operating a semiconductor memory device according to an embodiment of the present invention may include performing an LSB program operation on a target page, and performing a second or third threshold on which MSB data of memory cells included in a next page is higher than a first threshold voltage level. Performing the MSB program operation of the next page to change the MSB data corresponding to the voltage level, and changing the MSB data of the selected memory cells among the memory cells included in the target page to MSB data corresponding to the first threshold voltage level. Performing the MSB program operation of the target page.

Before performing the MSB program operation of the next page, the method may further include performing the LSB program operation of the next page.

The MSB program operation of the next page is performed when there is a memory cell in which the LSB data is not changed after performing the LSB program operation of the target page. When all LSB data of the memory cells included in the target page is changed after the LSB program operation of the target page is changed, the second or third threshold voltage level higher than the first threshold voltage level of the MSB data of the memory cells included in the target page is changed. And performing an MSB program operation of the target page to change to MSB data corresponding to the.

The operation method of the semiconductor memory device may minimize the interference phenomenon in which the threshold voltages of the memory cells increase in the target page by the program operation of the next page adjacent to the target page. As a result, errors that may occur during data storage may be prevented and reliability may be improved.

1A and 1B are graphs for explaining levels of threshold voltages depending on data stored in a memory cell.
2 is a circuit diagram of a memory block for explaining a method of operating a semiconductor memory device of the present invention.
3 is a flowchart illustrating a method of operating a semiconductor memory device of the present invention.

2 is a circuit diagram of a memory block for explaining a method of operating a semiconductor memory device of the present invention.

Referring to FIG. 2, in a NAND flash memory device, a memory array includes a plurality of memory blocks. One memory block includes a plurality of strings ST. The strings are connected to the bit lines BL0 to BLk, respectively, and are commonly connected to the common source CS. Each string ST includes a drain select transistor connected to the bit line BL1, a source select transistor connected to the common source CS, and memory cells connected in series between the drain select transistor and the source select transistor. Here, the memory cells connected in series become a memory cell string, and the drain select transistor becomes a string connection element connecting the memory cell string to a bit line. Gates of the drain select transistors are connected to the drain select line DSL, and gates of the source select transistors are connected to the source select line SSL. In addition, the gates of the memory cells are connected to the word lines WL0 to WLn, respectively. Meanwhile, memory cells connected to one word line WL0 become a page PB. One page PG may be divided into an even page including memory cells connected to even-numbered bit lines and an odd page including memory cells connected to odd-numbered bit lines. A program voltage and a program pass voltage for a program operation are applied to the word lines WL0 to WLn, and a program permission voltage or a program inhibit voltage is selectively applied to the bit lines BL0 to BLk according to data stored in memory cells. Is approved.

 3 is a flowchart illustrating a method of operating a semiconductor memory device of the present invention.

Referring to FIG. 3, in operation S301, an LSB program operation is performed to store LSB data in selected memory cells among memory cells included in a target page. Specifically, the case where the first word line WL1 is set as the target page and the second word line WL2 is set as the next page adjacent to the target page will be described as an example. For the LSB program operation, a program permission voltage (eg, a ground voltage) is applied to bit lines connected to memory cells of which LSB data is changed among memory cells connected to the first word line WL1, and the LSB data is not changed. A program inhibit voltage (eg, a power supply voltage) is applied to bit lines connected to the memory cells. The program voltage is applied to the first word line WL1 and the program pass voltage is applied to the remaining word lines WL0 and WL2 to WLn. Due to the program voltage and the program permission voltage, threshold voltages of selected memory cells among the memory cells connected to the first word line WL1 are higher than 0V, and the LSB data is changed from '1' to '0'. LSB data is stored as '0' in the memory cells selected by the above operation.

In step S303, when data is stored in memory cells included in a memory block according to a known Re-program method, after performing an MSB program operation on a word line WL0 corresponding to a previous page, the second page corresponding to the next page may be used. The LSB program operation of the two word lines WL2 may be performed.

In operation S305, it is checked whether the LSB data of the memory cells connected to the first word line WL1 is changed. In detail, all of the memory cells connected to the first word line WL1 are selected to check whether the threshold voltages of all the memory cells are higher than 0V by the LSB program operation.

When the threshold voltages of all the memory cells connected to the first word line WL1 are higher than 0 V by the LSB program operation, the threshold voltages of the memory cells connected to the first word line WL1 may be equal to or lower than the second threshold voltage level PV2. It must rise to the third threshold voltage level PV3.

Therefore, in operation S307, the threshold voltages of some of the memory cells connected to the first word line WL1 are raised to the second threshold voltage level PV2 according to the stored data, and the thresholds of the remaining memory cells are increased. The MSB program operation is performed to raise the voltages to the third threshold voltage level PV3. In this case, since the MSB program operation for raising the threshold voltage of the memory cell to the first threshold voltage level PV1 is unnecessary, the program operation of the first word line WL1 which is the target page is terminated.

If only the threshold voltages of some of the memory cells connected to the first word line WL1 are higher than 0 V by the LSB program operation, some of the memory cells connected to the first word line WL1 may be stored according to the stored data. These threshold voltages must rise to the first threshold voltage level PV1.

In operation S309, it is detected whether there is a memory cell whose MSB data is changed among memory cells connected to the first word line WL1 according to the stored data. This is to detect whether there is a memory cell whose threshold voltage must rise to the first threshold voltage level PV1 according to the MSB data. If there is no memory cell whose threshold voltage must rise to the first threshold voltage level PV1, the program operation may be terminated.

If there is a memory cell in which the threshold voltage must rise to the first threshold voltage level PV1, the threshold voltage is increased according to the MSB data stored in the memory cells connected to the second word line WL2 in step S311. Alternatively, it is detected whether there is a memory cell that needs to rise to the third threshold voltage levels PV2 and PV3.

If there are memory cells whose threshold voltages must rise to the second or third threshold voltage levels PV2 and PV3, the threshold voltages of the selected memory cells among the memory cells connected to the first word line WL1 may be set to the first threshold voltage level. Before the program operation for raising to PV1, in operation S313, the threshold voltages of some of the memory cells connected to the second word line WL2 are set to a second threshold voltage level higher than the first threshold voltage level PV1. The MSB program operation for raising to the PV2 or the third threshold voltage level PV3 is first performed. Accordingly, the MSB data of some of the memory cells connected to the second word line WL2 is changed to MSB data corresponding to the second or third threshold voltage level higher than the first threshold voltage level.

In operation S315, an MSB program operation is performed to increase threshold voltages of selected memory cells among the memory cells connected to the first word line WL1 to the first threshold voltage level PV1. Accordingly, MSB data of the selected memory cells are changed to MSB data corresponding to the first threshold voltage level PV1.

In operation S311, when it is detected that there is no memory cell to which the threshold voltage of the memory cells connected to the second word line WL2 should rise to the second or third threshold voltage levels PV2 and PV3, Performing an MSB program operation to raise the threshold voltages of the selected memory cells of the first word line WL1 to the first threshold voltage level PV1 without performing the MSB program operation of the second word line WL2 ( S315) is performed.

In this manner, the threshold voltage of the memory cell included in the next page WL2 adjacent to the target page WL1 is previously raised to a high level by a program operation, and then the threshold voltage of the memory cell included in the target page WL1 is programmed. By increasing the level to a low level, it is possible to prevent the threshold voltage of the memory cell from changing from the low level to the high level in the target page WL1 due to the interference caused by the program operation of the next page WL2.

PG: Page ST: String
CS: Common Source BL0 ~ BLk: Bitline
WL0 ~ WLn: Word line DSL: Drain select line
SSL: source select line

Claims (4)

Performing an LSB program operation on a target page;
Performing the MSB program operation of the next page to change the MSB data of the memory cells included in the next page to MSB data corresponding to the second or third threshold voltage level higher than the first threshold voltage level; And
Performing an MSB program operation on the target page to change the MSB data of the selected memory cells among the memory cells included in the target page to MSB data corresponding to the first threshold voltage level. Way.
The method of claim 1,
And performing the LSB program operation of the next page before performing the MSB program operation of the next page.
The method of claim 1,
And the MSB program operation of the next page is performed when a memory cell in which LSB data is not changed after the LSB program operation of the target page exists.
The method of claim 3, wherein
When all the LSB data of the memory cells included in the target page is changed after performing the LSB program operation of the target page, the MSB data of the memory cells included in the target page is higher than the first threshold voltage level. And performing an MSB program operation of the target page to change to MSB data corresponding to a second or third threshold voltage level.

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