KR20110114048A - Semiconductor device having metal line and forming method of the same - Google Patents

Semiconductor device having metal line and forming method of the same Download PDF

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Publication number
KR20110114048A
KR20110114048A KR1020100033458A KR20100033458A KR20110114048A KR 20110114048 A KR20110114048 A KR 20110114048A KR 1020100033458 A KR1020100033458 A KR 1020100033458A KR 20100033458 A KR20100033458 A KR 20100033458A KR 20110114048 A KR20110114048 A KR 20110114048A
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KR
South Korea
Prior art keywords
metal
ion implantation
contact
metal line
high conductivity
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KR1020100033458A
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Korean (ko)
Inventor
장치환
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100033458A priority Critical patent/KR20110114048A/en
Publication of KR20110114048A publication Critical patent/KR20110114048A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

The semiconductor device of the present invention reduces the migration that can occur locally between the metal line and the metal contact and improves contact resistance by injecting ions of a metal having a higher conductivity than the metal line into a region in contact with the upper metal contact in the metal line. By reducing the characteristics of the semiconductor device is improved.

Description

Semiconductor device having metal line and method for forming the same {Semiconductor device having metal line and forming method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal line of a semiconductor device, and more particularly, to a semiconductor device having a metal line capable of reducing contact resistance and improving characteristics of the semiconductor device, and a method of forming the same.

Semiconductor devices use multiple metal lines to transfer external power into the chip. In the conventional semiconductor device, aluminum (Al) is mainly used as a material of a metal line to realize a high speed and low power device due to low resistance in forming metal wires. Cu). This is because copper has lower resistivity and stronger migration characteristics than aluminum.

However, even in the formation of metal wires using copper, migration still occurs in the local region between the metal and the metal contact as shown in FIG. 1, causing poor quality.

In addition, when forming a metal line using copper, there is no dry etch source that can etch copper until now, so the damascene process using the CMP process should be used.

However, when the copper metal line is formed by the damascene process, since the electroplating method is used, the deposited copper has a small grain size structure, resulting in a small bond between atoms and fine voids. Void). This means that the resistance of the copper metal line is increased, and there is a possibility that the volume of copper may shrink, causing an open fail due to migration between the metal and the metal contact.

The present invention is to improve the metal line and its manufacturing method to improve the migration and electrical properties by the resistance between the metal line and the metal contact thereon.

The semiconductor device of the present invention includes a metal line, a high conductivity ion implantation layer implanted on a surface of the metal line and having a higher conductivity than the metal line, and a metal contact formed on the high conductivity ion implantation layer. Include.

As such, in the present invention, metal ions having a higher conductivity than metal lines are implanted into the metal lines, and metal contacts are formed on the ion implantation layer to reduce contact resistance, thereby improving characteristics of the semiconductor device.

In this case, the high conductivity ion implantation layer is a layer in which silver (Ag) ions are implanted, and may be formed only in a region in contact with the metal contact in the metal line or may be formed on the entire upper surface of the metal line.

The method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal line on a first metal contact; And a third step of forming a second metal contact on the high conductivity ion implantation layer.

The first step may include forming a first interlayer insulating layer including the first metal contact, and etching the first interlayer insulating layer until the first metal contact is exposed to define an area of the metal line. A conductive layer may be formed on the first barrier metal layer to form a damascene pattern, to form a first barrier metal layer on an inner surface of the damascene pattern, and to fill the damascene pattern. The conductive layer may be formed by electroplating.

 In the second step, the high conductivity ion implantation layer may be formed in a region of the metal line in contact with the second metal contact. In this case, the second step may include sequentially forming a second barrier metal film and a second interlayer insulating film on the metal line, and forming the second barrier metal film and the second interlayer insulating film until the metal line is exposed. Selective etching may include forming a first contact hole defining a region of the second metal contact, and implanting metal ions into the metal line through the first contact hole. In the third step, a contact material may be formed on the high conductivity ion implantation layer to fill the first contact hole.

Alternatively, the second step may form the high conductivity ion implantation layer on the entire surface of the metal line. In this case, the third step may include forming a third interlayer insulating film on the high conductivity ion implantation layer, and selectively etching the third interlayer insulation layer until the high conductivity ion implantation layer is exposed. Forming a second contact hole defining a region and forming a contact material on the high conductivity ion implantation layer to fill the second contact hole.

The second step is to inject silver (Ag) ions into the metal line, the ion implantation method is an ion implantation method using an accelerator, plasma ion implantation method, PECVD (Plasma Enhanced Chemical Vapor Deposition) method, PVD (Physical Vapor) Deposition) method may be any one.

The present invention can improve the characteristics of the semiconductor device by reducing migration and reducing contact resistance by injecting metal ions having higher conductivity than the metal line in a region in contact with the upper metal contact in the metal line.

1 is a cross-sectional view showing migration in a conventional copper metal line.
2A through 2F are cross-sectional views illustrating an exemplary embodiment for forming the metal line structure of FIG. 1.
3A and 3B are cross-sectional views illustrating another embodiment according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The metal line according to an embodiment of the present invention is a metal having a lower resistance (higher conductivity) than the metal line in a region where the metal line is in contact with the metal contact thereof, for example, when the metal line is copper (Cu). High silver (Ag) ions are implanted locally.

2A to 2F are cross-sectional views illustrating a process for forming a metal line according to the present embodiment.

Referring to FIG. 2A, an interlayer insulating layer 102 is formed on a semiconductor substrate (not shown) on which a lower structure (not shown) such as a transistor, a bit line, a capacitor, and a metal1 contact M1C is formed, and the interlayer insulating layer 102 is formed. The photoresist pattern 104 defining the metal line M1 region is formed sequentially.

Next, the interlayer insulating layer 102 is etched until the metal 1 contact is exposed using the photoresist pattern 104 as an etch mask, thereby forming a damascene pattern 106 defining a metal line region.

Next, referring to FIG. 2B, the barrier metal film 108 is formed on the entire structure including the inner surface of the damascene pattern 106 after the photoresist pattern 104 is removed.

In this case, the barrier metal layer 108 may be formed of a single layer or a double layer including at least one of a tantalum nitride layer (TaN) and a tantalum layer (Ta), an atomic layer deposition (ALD) method, or a chemical vapor deposition (CVD). Can be formed in a In addition, the barrier metal film 108 has a thickness (for example, 20 mm to about 20 mm) to secure the aspect ratio of the damascene pattern 106 and to prevent the diffusion of metal ions included in the conductive layer formed in a subsequent step. 50 mV).

The barrier metal film 108 is formed to prevent ions contained in the conductive layer to be formed in a subsequent process from being diffused into the interlayer insulating film 102 to lower electrical characteristics of the semiconductor device.

Next, referring to FIG. 2C, a conductive layer (not shown) is formed on the entire structure so that the damascene pattern 106 is completely embedded, and then the planarization layer is planarized (CMP) until the interlayer insulating layer 102 is exposed. It remains only inside the drinking pattern to form an electrically isolated metal line 110.

The conductive layer may be formed of a metal such as copper (Cu), aluminum (Al), tungsten (W), chromium (Cr), nickel (Ni), or the like, and may be preferably formed of Cu. In this case, the conductive layer may be formed by an electroplating method, and may be formed by an electroless plating method using the barrier metal film 108 as an electrode for generating a reaction during electroplating.

Next, referring to FIG. 2D, the nitride film 112 and the interlayer insulating film 114 are sequentially formed on the interlayer insulating film 102, the barrier metal film 108, and the metal line 110. In this case, a barrier metal film (not shown) may be additionally formed between the metal line 110 and the nitride film 112.

Next, referring to FIG. 2E, a photoresist pattern (not shown) defining a metal 2 contact (M2C) region is formed on the interlayer insulating layer 114, and the interlayer insulating layer 114 is exposed until the metal line 110 is exposed using an etching mask. The insulating film 114 and the nitride film 112 are sequentially etched to form the metal 2 contact hole 118.

Next, after removing the photoresist layer pattern, the metal line 110 exposed to the metal line 110 exposed by the metal 2 contact hole 118 is implanted with ions of a metal having a lower resistance (higher electrical conductivity) than the metal line 110. ), A high conductivity ion implantation layer 116a is formed in a region to be in contact with the metal 2 contact to be formed in a subsequent process. For example, when the metal line 110 is a copper wiring, the high conductivity ion implantation layer 116a may be an Ag layer implanted with silver (Ag) ions or a Cu and Ag alloy layer.

In this case, the metal (Ag) ion implantation method for forming the high conductivity ion implantation layer 116a may include an ion implantation method using an accelerator, a plasma ion implantation method, a plasma enhanced chemical vapor deposition (PECVD) method, and a physical vapor deposition (PVD) method. ) Method and the like can be used. The Ag ion implantation source uses a solid or gas source containing Ag, and may be injected by forming an Ag plasma using an inert gas (He, Ar, Xe, etc.) according to circumstances.

Prior to ion implantation, a barrier metal film (not shown) may be formed on the inner surface of the metal 2 contact hole 118.

Next, referring to FIG. 2F, a contact material is formed on the high conductivity ion implantation layer 116a so that the metal 2 contact hole 118 is filled and then planarized to form the metal 2 contact 120.

In this case, the planarization process is not only performed on the contact material but also on the interlayer insulating layer 114. That is, since the metal ions are implanted into the surface of the interlayer insulating layer 114 in the ion implantation process of FIG. 2E, the planarization of the interlayer insulating layer 114 is performed to remove the metal ions injected into the surface of the interlayer insulating layer 114. . However, in FIG. 2E, metal ions may be implanted without removing the photoresist pattern. In such a case, metal ions are implanted into the photoresist pattern instead of the interlayer insulating layer 114. Therefore, in such a case, when the photoresist pattern is removed, the metal ions injected into the photoresist pattern are also removed, so that the planarization of the interlayer insulating film 114 is not necessary.

 Since the metal line forming process and the subsequent processes connected to the metal 2 contact 120 are the same as in the related art, a description thereof will be omitted below.

3A and 3B are cross-sectional views illustrating a process for describing another embodiment according to the present invention. For convenience of description, the present embodiment uses the same reference numerals used in the above-described embodiment for the same object.

Referring to FIG. 3A, after performing the above-described processes of FIGS. 2A to 2C, metal (Ag) ions are implanted into the entire product of FIG. 2C, and the high conductivity ion implantation layer 116b is formed on the entire upper surface of the metal line 110. To form. Next, a planarization process is performed to remove metal ions implanted into the interlayer insulating film 102.

Next, referring to FIG. 3B, the nitride film 112 and the interlayer insulating film 114 are sequentially formed on the interlayer insulating film 102, the barrier metal film 108, and the metal line 110.

Next, a photoresist pattern (not shown) defining a metal 2 contact (M2C) region is formed on the interlayer insulating layer 114, and the interlayer insulating layer (not shown) is exposed until the high conductivity ion implantation layer 116b is exposed using an etching mask. 114 and the nitride film 112 are sequentially etched to form a metal 2 contact hole (not shown). Subsequently, a contact material is formed on the high conductivity ion implantation layer 116b so that the metal 2 contact hole is filled and then planarized to form the metal 2 contact 120.

102, 114: interlayer insulating film 104: photosensitive film pattern
106: damascene pattern 108: barrier metal film
110: metal line 112: nitride film
116a and 116b: High conductivity ion implantation layer 118: Metal 2 contact hole
120: metal 2 contact

Claims (15)

Metal lines;
A high conductivity ion implantation layer formed on a surface of the metal line and implanted with ions of a metal having a higher conductivity than the metal line; And
A semiconductor device comprising a metal contact formed on the high conductivity ion implantation layer. The method of claim 1, wherein the high conductivity ion implantation layer
And formed only in a region of the metal line in contact with the metal contact. The method of claim 1, wherein the high conductivity ion implantation layer
A semiconductor device, characterized in that formed on the entire upper surface of the metal line. The method of claim 1, wherein the metal line
A semiconductor device comprising any one of copper (Cu), aluminum (Al), tungsten (W), chromium (Cr), and nickel (Ni). The method of claim 1, wherein the high conductivity ion implantation layer
A semiconductor device comprising a layer implanted with silver (Ag) ions. Forming a metal line on the first metal contact;
A second step of forming a high conductivity ion implantation layer by implanting ions of a metal having a higher conductivity than the metal line into the metal line; And
And forming a second metal contact on the high conductivity ion implantation layer. The method of claim 6, wherein the first step
Forming a first interlayer insulating film including the first metal contact;
Etching the first interlayer insulating layer until the first metal contact is exposed to form a damascene pattern defining a region of the metal line;
Forming a first barrier metal film on an inner surface of the damascene pattern; And
And forming a conductive layer on the first barrier metal film so that the damascene pattern is embedded. The method of claim 7, wherein the conductive layer is
A method for manufacturing a semiconductor device, which is formed by electroplating. The method of claim 6, wherein the second step
And forming the high conductivity ion implantation layer in a region of the metal line in contact with the second metal contact. 10. The method of claim 9, wherein the second step is
Sequentially forming a second barrier metal film and a second interlayer insulating film on the metal line;
Selectively etching the second barrier metal layer and the second interlayer insulating layer until the metal line is exposed to form a first contact hole defining a region of the second metal contact; And
And injecting metal ions into the metal line through the first contact hole. The method of claim 10, wherein the third step
And forming a contact material on the high conductivity ion implantation layer to fill the first contact hole. The method of claim 6, wherein the second step
The high conductivity ion implantation layer is formed on the entire surface of the metal line. The method of claim 12, wherein the third step
Forming a third interlayer insulating film on the high conductivity ion implantation layer;
Selectively etching the third interlayer insulating layer until the high conductivity ion implantation layer is exposed to form a second contact hole defining a region of the second metal contact; And
Forming a contact material on the high conductivity ion implantation layer to fill the second contact hole. The method of claim 6, wherein the second step
Injecting silver (Ag) ions into the metal line, characterized in that the semiconductor device manufacturing method. The method of claim 14, wherein the ion implantation method
A method of fabricating a semiconductor device comprising any one of an ion implantation method using an accelerator, a plasma ion implantation method, a plasma enhanced chemical vapor deposition (PECVD) method, and a physical vapor deposition method (PVD).
KR1020100033458A 2010-04-12 2010-04-12 Semiconductor device having metal line and forming method of the same KR20110114048A (en)

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KR1020100033458A KR20110114048A (en) 2010-04-12 2010-04-12 Semiconductor device having metal line and forming method of the same

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KR1020100033458A KR20110114048A (en) 2010-04-12 2010-04-12 Semiconductor device having metal line and forming method of the same

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