KR20110108547A - Method for manufacturing semiconductor device with vertical gate and active pillar - Google Patents

Method for manufacturing semiconductor device with vertical gate and active pillar Download PDF

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Publication number
KR20110108547A
KR20110108547A KR1020100027796A KR20100027796A KR20110108547A KR 20110108547 A KR20110108547 A KR 20110108547A KR 1020100027796 A KR1020100027796 A KR 1020100027796A KR 20100027796 A KR20100027796 A KR 20100027796A KR 20110108547 A KR20110108547 A KR 20110108547A
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KR
South Korea
Prior art keywords
pillar
film
semiconductor device
sacrificial
etching
Prior art date
Application number
KR1020100027796A
Other languages
Korean (ko)
Inventor
표승석
Original Assignee
주식회사 하이닉스반도체
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Publication date
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Priority to KR1020100027796A priority Critical patent/KR20110108547A/en
Publication of KR20110108547A publication Critical patent/KR20110108547A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

The present invention is to provide a method of manufacturing a semiconductor device having a vertical gate that can prevent the active pillar collapse, the method of manufacturing a semiconductor device of the present invention to form a first pillar separated by a trench by etching the substrate Making; Forming a sacrificial layer to gap fill the trench; Forming a conductive film on the sacrificial film and the substrate; Etching the conductive layer to form a second pillar on the first pillar; And removing the sacrificial layer, and the present invention described above has the effect of increasing the structural stability of the active pillar by forming the active pillar through the sacrificial layer and the sacrificial layer removal gap gap filling.

Description

Method of manufacturing semiconductor device with vertical gate and active pillar {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND ACTIVE PILLAR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a vertical gate and an active pillar.

A semiconductor device having a vertical gate includes a pillar-shaped active region (hereinafter referred to as an 'active pillar') by processing a semiconductor substrate and a round type vertical gate that surrounds the active pillar and is vertical. Channels are formed in the vertical direction at the top and bottom of the active pillar around the gate.

1 is a view showing a method of manufacturing a semiconductor device having a vertical gate according to the prior art.

As illustrated in FIG. 1, the substrate 11 is etched using the hard mask layer 15 as an etch barrier to form an active pillar including the first pillar 12A and the second pillar 12B. The first pillar 12A is a body pillar, and the second pillar 12B is a head pillar. The second pillar 12B is larger in width than the first pillar 12A.

Subsequently, after the gate insulating film 13 is formed on the surfaces of the active pillar and the substrate 11, the vertical gate 14 surrounding the sidewall of the first pillar 12A of the active pillar is formed.

The prior art of FIG. 1 repeats a vertical etch and an isotropic etch to form an active pillar. Accordingly, since the first pillar 12A is smaller than the second pillar 12B, pillar collapse occurs during isotropic etching.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems according to the prior art, and provides a method of manufacturing a semiconductor device having a vertical gate which can prevent the active pillar from collapsing.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of: etching a substrate to form a first pillar separated by a trench; Forming a sacrificial layer to gap fill the trench; Forming a conductive film on the sacrificial film and the substrate; Etching the conductive layer to form a second pillar on the first pillar; And removing the sacrificial film. The substrate and the conductive film may include a silicon film, and the sacrificial film may include a silicon germanium film. The removing of the sacrificial layer is performed by wet etching, and the wet etching is performed by using a mixed solution of acetic acid and hydrofluoric acid.

The present invention described above has the effect of increasing the structural stability of the active pillar by forming the active pillar through the sacrificial layer and the sacrificial layer removal gap gap fill.

1 is a view showing a method of manufacturing a semiconductor device having a vertical gate according to the prior art.
2A to 2F are diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2F are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, the trench 23 is formed by etching the silicon substrate 21 using the first photoresist pattern 22 as an etch barrier. A plurality of first pillars 21A are formed by the trench 23. An etching process for forming the first pillar 21A includes anisotropic etching. Accordingly, the sidewall profile of the first pillar 21A can be formed into a vertical profile.

As shown in FIG. 2B, the sacrificial layer 24 is gapfilled into the trench 23. The sacrificial layer 24 includes an epitaxial layer. The sacrificial layer 24 includes a silicon germanium layer (SiGe). The silicon germanium film (SiGe) is grown by using epitaxial growth. The silicon germanium film used as the sacrificial film 24 has a ratio of silicon (Si) and germanium (Ge) to be selectively etched with respect to the silicon substrate in a subsequent process. Preferably, the ratio of silicon (Si) and germanium (Ge) has a composition ratio of 0.8: 0.2.

As shown in FIG. 2C, the conductive film 25 is formed on the substrate 21 including the sacrificial film 24. The conductive film 25 includes an epitaxial film. The conductive film 25 includes a silicon epitaxial layer. The silicon epitaxial film is grown by using epitaxial growth.

As shown in FIG. 2D, after forming the hard mask film 26 on the conductive film 25, the second photoresist film pattern 27 is formed on the hard mask film 26. The hard mask film 26 includes a nitride film. The second photoresist pattern 26 has a larger line width than the first photoresist pattern 22 (in FIG. 2A).

After etching the hard mask layer 26 using the second photoresist layer pattern 27 as an etch barrier, the conductive layer 25 is etched using the hard mask layer 26 as an etch barrier. As a result, a second pillar 25A is formed. An etching process for etching the conductive film 25 includes anisotropic etching. Accordingly, the sidewall profile of the second pillar 25A can be formed into a vertical profile. When the conductive film 25 is etched, Cl 2 or HBr gas is used alone, or a mixed gas of Cl 2 and HBr gas is used for etching. The second pillar 25A is larger in width than the first pillar 21A.

As described above, when the second pillar 25A is formed, the first pillar 21A is protected by the sacrificial film 24 to prevent the first pillar 21A from collapsing. The first pillar 21A and the second pillar 25A are active pillars 201 serving as active regions.

As shown in FIG. 2E, the second photosensitive film pattern 27 is stripped.

Next, the sacrificial film 24 is removed. Wet etching is used to selectively remove the sacrificial layer 24. Since the first pillar 21A and the second pillar 25A are silicon films and the sacrificial film 24 is a silicon germanium film, a selectivity ratio between the silicon film and silicon germanium is used. Accordingly, the sacrificial film 24 may be selectively removed without attacking the first pillar 21A and the second pillar 25A. For example, when selectively removing the sacrificial film 24, a first mixed solution of acetic acid (CH 3 COOH) and hydrofluoric acid is used. In addition, a second mixed solution may be used in which nitric acid (HNO 3 ), hydrofluoric acid (HF), acetic acid (CH 3 COOH), and water (H 2 O) are mixed. When the second mixed solution is used, 70% nitric acid, 49% hydrofluoric acid, and 99.9% acetic acid are used, and a content ratio of 40: 1: 2: 57 and a solution in which H 2 O is appropriately mixed are used. By using such a first mixed solution or a second mixed solution, the silicon germanium layer (SiGe layer) can be selectively removed without damaging the silicon film.

When the sacrificial film 22B is removed as described above, the active pillar 201 including the first pillar 21A and the second pillar 25A is stably formed on the substrate 21.

As shown in FIG. 2F, a gate insulating film 28 is formed on the surfaces of the active pillar 201 and the substrate 21. Next, the vertical gate 29 surrounding the sidewall of the first pillar 21A is formed. The vertical gate 29 is obtained by depositing a conductive film on the entire surface of the substrate 21 and etching back until the gate insulating film 28 on the substrate 21 is exposed. The vertical gate 29 may be a polysilicon film or a metal film.

Subsequently, a buried bitline is formed in the substrate 21 using a method such as ion implantation. Since the width of the trench is adjustable, it is easy to adjust the line width of the buried bit line.

According to the above-described embodiment, the present invention may perform an anisotropic etching process and selective epitaxial growth (SEG) process when the active pillar 201 including the first pillar 21A and the second pillar 25A is formed. In addition, since it is not necessary to perform the isotropic etching process, it is possible to prevent the collapse of the active pillar caused during the isotropic etching process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

21: substrate 21A: first pillar
23: trench 24: sacrificial film
25A: second pillar 201: active pillar

Claims (7)

Etching the substrate to form a first pillar separated by a trench;
Forming a sacrificial layer to gap fill the trench;
Forming a conductive film on the sacrificial film and the substrate;
Etching the conductive layer to form a second pillar on the first pillar; And
Removing the sacrificial layer
≪ / RTI >
The method of claim 1,
The sacrificial film includes a silicon germanium film.
The method of claim 1,
The substrate and the conductive film comprises a silicon film, the sacrificial film comprises a silicon germanium film.
The method of claim 3,
Removing the sacrificial layer,
A method of manufacturing a semiconductor device by wet etching.
The method of claim 4, wherein
The wet etching is performed using a mixed solution of acetic acid and hydrofluoric acid.
The method of claim 1,
And the conductive film is formed using a selective epitaxial growth method.
The method of claim 1,
Forming the first pillar and forming the second pillar,
A method of manufacturing a semiconductor device that proceeds with anisotropic etching.


KR1020100027796A 2010-03-29 2010-03-29 Method for manufacturing semiconductor device with vertical gate and active pillar KR20110108547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100027796A KR20110108547A (en) 2010-03-29 2010-03-29 Method for manufacturing semiconductor device with vertical gate and active pillar

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100027796A KR20110108547A (en) 2010-03-29 2010-03-29 Method for manufacturing semiconductor device with vertical gate and active pillar

Publications (1)

Publication Number Publication Date
KR20110108547A true KR20110108547A (en) 2011-10-06

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Country Status (1)

Country Link
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