KR20110107122A - Semiconductor package and method of fabricating the same - Google Patents
Semiconductor package and method of fabricating the same Download PDFInfo
- Publication number
- KR20110107122A KR20110107122A KR1020100026304A KR20100026304A KR20110107122A KR 20110107122 A KR20110107122 A KR 20110107122A KR 1020100026304 A KR1020100026304 A KR 1020100026304A KR 20100026304 A KR20100026304 A KR 20100026304A KR 20110107122 A KR20110107122 A KR 20110107122A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- bump
- insulating film
- semiconductor chip
- circuit pattern
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 238000005538 encapsulation Methods 0.000 claims abstract description 11
- 238000009413 insulation Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000003475 lamination Methods 0.000 description 5
- 229920006336 epoxy molding compound Polymers 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920000098 polyolefin Polymers 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention discloses a semiconductor package and a method of manufacturing the same. According to an aspect of the present invention, there is provided a semiconductor package including: a semiconductor chip having one surface on which bonding pads are disposed and the other surface opposite to the surface; An insulation layer exposing the bonding pads and formed on the one surface; Bumps formed on the respective bonding pads; A circuit pattern connected to each of the bumps and formed on the insulating layer; An encapsulation member surrounding the other surface and the side of the semiconductor chip; A solder mask formed on the insulating layer and the circuit pattern to expose a portion of the circuit pattern; And an external mounting member formed on the exposed circuit pattern.
Description
The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same that can enhance the bonding strength.
Packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization.
In addition, in order to realize high-speed operation, it is required to directly connect a logic element and a memory element which are non-memory elements. However, if the non-memory element and the memory element have different pad positions, or if the design of these elements is changed, it is impossible to connect directly to each other.
Accordingly, there is a need for a semiconductor package that can be interconnected regardless of the type or design of the semiconductor devices. As a result, the use of embedded technology is increasing.
On the other hand, the following briefly describes the manufacturing method of the embedded package.
A substrate having a surface having one surface and the other surface opposite to the surface and having a hole is provided. The semiconductor chip having bumps is cut, and the semiconductor chip is attached to the hole formed in the substrate. In this case, the semiconductor chip is attached such that the bump is positioned in a direction corresponding to the other surface of the substrate.
Then, after lamination of the other surface of the substrate with a material such as Resin coated copper foil (RCC), the RCC material is etched to expose the bumps and then opened to have vias. The open via is filled with a conductive material using a filling process to electrically contact the copper formed on the surface and the bump during the lamination.
Thereafter, the circuit pattern and the bump may be chemically bonded to each other by the aforementioned method.
However, this method is possible only in the process of opening the bump, for example, a pitch of about 130 μm or more, and at present there is a limit to opening the bump portion for a pitch less than that. In addition, since the bump opening process and the filling process for filling the via are performed, manufacturing time and manufacturing cost increase.
In addition, this method has a problem that the pressing of the bumps is not uniform during the lamination, thereby causing a step difference in surface, thereby weakening the joint coupling force between the bumps and the circuit patterns to be subsequently formed. In addition, there is a risk that cracks are generated in the semiconductor chip due to a lot of pressure applied.
The present invention provides a semiconductor package and a method of manufacturing the same that can enhance the bonding strength.
A semiconductor package according to an embodiment of the present invention includes a semiconductor chip having one surface on which bonding pads are disposed and the other surface opposite to the one surface; An insulation layer exposing the bonding pads and formed on the one surface; Bumps formed on the respective bonding pads; A circuit pattern connected to each of the bumps and formed on the insulating layer; An encapsulation member surrounding the other surface and the side of the semiconductor chip; A solder mask formed on the insulating layer and the circuit pattern to expose a portion of the circuit pattern; And an external mounting member formed on the exposed circuit pattern.
The insulating layer has a cavity through which the bump passes.
In a method of manufacturing a semiconductor package according to an embodiment of the present invention, an insulating film and bonding pads in which a first layer having a cavity and a second layer disposed on the first layer and not having the cavity are stacked are arranged. Providing a semiconductor chip having one surface and the other surface opposite to the one surface; Forming bumps on each bonding pad of the semiconductor chip; Attaching the semiconductor chip onto the insulating film such that the bump penetrates the cavity; Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip; Removing the second layer of the insulating film so that each bump is exposed; Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump; Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And forming external mounting members on the exposed circuit patterns, respectively.
The preparing of the insulating film may further include a metal layer between the first layer having the cavity and the second layer having no cavity.
The step of attaching the semiconductor chip on the insulating film so that the bump penetrates the cavity is performed using heat, pressure, and ultrasonic waves.
Removing the second layer of the insulating film so that each bump is exposed is performed by a grinding process.
Removing the second layer of the insulating film to expose each bump, is removed using UV.
In a method of manufacturing a semiconductor package according to another embodiment of the present invention, an insulating film and bonding pads in which a soft first layer and a second layer having a higher strength than the first layer are stacked are disposed. Providing a semiconductor chip having one surface and the other surface opposite to the one surface; Forming bumps on each bonding pad of the semiconductor chip; Attaching the semiconductor chip onto the insulating film such that the bump penetrates the first layer and is inserted into the second layer; Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip; Removing the second layer of the insulating film so that each bump is exposed; Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump; Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And forming external mounting members on the exposed circuit patterns, respectively.
According to the present invention, after providing an insulating layer having a semiconductor chip in which bumps are formed in advance and a cavity through which the bumps are transmitted, the bumps are transmitted to a portion corresponding to the cavity to expose the surface of the bumps from the surface of the insulating layer. The semiconductor chip and the insulating layer are attached to each other, and then a circuit pattern is formed to be electrically connected to the bumps exposed from the surface of the insulating layer.
By doing so, the present invention can not only enhance the bonding strength between the bumps and the circuit patterns, but also can safely expose the bumps without the residue of foreign matter.
In addition, the present invention does not require an open process for exposing the bump and a peeling process for electrically connecting the circuit pattern to the bump part exposed by the open process in order to bond the bump and the circuit patterns. Through this, the present invention can reduce the manufacturing time and manufacturing cost.
In addition, the present invention can prevent the non-uniform pressing of the bump during lamination to improve the bonding strength between the bump and the circuit patterns.
1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.
Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
As illustrated, a
An
A
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.
2A and 2B, a
In addition, an
The
Although not shown and described in detail, the
The
Referring to FIG. 2C, the
An
Meanwhile, when the
Referring to FIG. 2D, the
Meanwhile, the
In this case, the
Referring to FIGS. 2E and 2F, the
In the meantime,
Referring to FIG. 2F, the circuit wiring is patterned to form a
Referring to FIG. 2E, a
External mounting
As described above, the present invention attaches the semiconductor chip and the insulating layer to expose the bump surface from the surface of the insulating layer through which the bump of the semiconductor chip with bumps is formed in advance and is exposed from the surface of the insulating layer. By forming a circuit pattern to be electrically connected to the bumps, not only the bonding strength between the bumps and the circuit patterns can be strengthened but also the bumps can be safely exposed without remaining of foreign matter.
In addition, the present invention does not require an open process for exposing the bump and a peeling process for electrically connecting the circuit pattern to the bump part exposed by the open process in order to bond the bump and the circuit patterns. Through this, the present invention can reduce the manufacturing time and manufacturing cost.
In addition, the present invention can prevent the non-uniform pressing of the bump during lamination to improve the bonding strength between the bump and the circuit patterns.
As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
Description of the Related Art [0002]
100: semiconductor chip 102: bonding pad
104: bump 106: insulating layer
109: circuit patterns; 110: solder mask
112: sealing member 114: external mounting member
120: semiconductor package
Claims (8)
An insulation layer exposing the bonding pads and formed on the one surface;
Bumps formed on the respective bonding pads;
A circuit pattern connected to each of the bumps and formed on the insulating layer;
An encapsulation member surrounding the other surface and the side of the semiconductor chip;
A solder mask formed on the insulating layer and the circuit pattern to expose a portion of the circuit pattern; And
An external mounting member formed on the exposed circuit pattern;
Semiconductor package comprising a.
And the insulating layer has a cavity through which the bump passes.
Forming bumps on each bonding pad of the semiconductor chip;
Attaching the semiconductor chip onto the insulating film such that the bump penetrates the cavity;
Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip;
Removing the second layer of the insulating film so that each bump is exposed;
Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump;
Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And
Forming external mounting members on the exposed circuit patterns;
Method of manufacturing a semiconductor package comprising a.
The preparing of the insulating film may further include a metal layer between the first layer having the cavity and the second layer not having the cavity.
And attaching the semiconductor chip onto the insulating film such that the bump penetrates the cavity, using heat, pressure, and ultrasonic waves.
Removing the second layer of the insulating film so that each bump is exposed, manufacturing method of a semiconductor package, characterized in that performed by a grinding (Grinding) process.
Removing the second layer of the insulating film so that each bump is exposed, manufacturing method of a semiconductor package, characterized in that for removing by using UV.
Forming bumps on each bonding pad of the semiconductor chip;
Attaching the semiconductor chip onto the insulating film such that the bump penetrates the first layer and is inserted into the second layer;
Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip;
Removing the second layer of the insulating film so that each bump is exposed;
Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump;
Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And
Forming external mounting members on the exposed circuit patterns;
Method of manufacturing a semiconductor package comprising a.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100026304A KR20110107122A (en) | 2010-03-24 | 2010-03-24 | Semiconductor package and method of fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100026304A KR20110107122A (en) | 2010-03-24 | 2010-03-24 | Semiconductor package and method of fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20110107122A true KR20110107122A (en) | 2011-09-30 |
Family
ID=44956645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100026304A KR20110107122A (en) | 2010-03-24 | 2010-03-24 | Semiconductor package and method of fabricating the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20110107122A (en) |
-
2010
- 2010-03-24 KR KR1020100026304A patent/KR20110107122A/en unknown
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