KR20110107122A - Semiconductor package and method of fabricating the same - Google Patents

Semiconductor package and method of fabricating the same Download PDF

Info

Publication number
KR20110107122A
KR20110107122A KR1020100026304A KR20100026304A KR20110107122A KR 20110107122 A KR20110107122 A KR 20110107122A KR 1020100026304 A KR1020100026304 A KR 1020100026304A KR 20100026304 A KR20100026304 A KR 20100026304A KR 20110107122 A KR20110107122 A KR 20110107122A
Authority
KR
South Korea
Prior art keywords
layer
bump
insulating film
semiconductor chip
circuit pattern
Prior art date
Application number
KR1020100026304A
Other languages
Korean (ko)
Inventor
김기영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100026304A priority Critical patent/KR20110107122A/en
Publication of KR20110107122A publication Critical patent/KR20110107122A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The present invention discloses a semiconductor package and a method of manufacturing the same. According to an aspect of the present invention, there is provided a semiconductor package including: a semiconductor chip having one surface on which bonding pads are disposed and the other surface opposite to the surface; An insulation layer exposing the bonding pads and formed on the one surface; Bumps formed on the respective bonding pads; A circuit pattern connected to each of the bumps and formed on the insulating layer; An encapsulation member surrounding the other surface and the side of the semiconductor chip; A solder mask formed on the insulating layer and the circuit pattern to expose a portion of the circuit pattern; And an external mounting member formed on the exposed circuit pattern.

Description

Semiconductor package and method of fabricating the same

The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same that can enhance the bonding strength.

Packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization.

In addition, in order to realize high-speed operation, it is required to directly connect a logic element and a memory element which are non-memory elements. However, if the non-memory element and the memory element have different pad positions, or if the design of these elements is changed, it is impossible to connect directly to each other.

Accordingly, there is a need for a semiconductor package that can be interconnected regardless of the type or design of the semiconductor devices. As a result, the use of embedded technology is increasing.

On the other hand, the following briefly describes the manufacturing method of the embedded package.

A substrate having a surface having one surface and the other surface opposite to the surface and having a hole is provided. The semiconductor chip having bumps is cut, and the semiconductor chip is attached to the hole formed in the substrate. In this case, the semiconductor chip is attached such that the bump is positioned in a direction corresponding to the other surface of the substrate.

Then, after lamination of the other surface of the substrate with a material such as Resin coated copper foil (RCC), the RCC material is etched to expose the bumps and then opened to have vias. The open via is filled with a conductive material using a filling process to electrically contact the copper formed on the surface and the bump during the lamination.

Thereafter, the circuit pattern and the bump may be chemically bonded to each other by the aforementioned method.

However, this method is possible only in the process of opening the bump, for example, a pitch of about 130 μm or more, and at present there is a limit to opening the bump portion for a pitch less than that. In addition, since the bump opening process and the filling process for filling the via are performed, manufacturing time and manufacturing cost increase.

In addition, this method has a problem that the pressing of the bumps is not uniform during the lamination, thereby causing a step difference in surface, thereby weakening the joint coupling force between the bumps and the circuit patterns to be subsequently formed. In addition, there is a risk that cracks are generated in the semiconductor chip due to a lot of pressure applied.

The present invention provides a semiconductor package and a method of manufacturing the same that can enhance the bonding strength.

A semiconductor package according to an embodiment of the present invention includes a semiconductor chip having one surface on which bonding pads are disposed and the other surface opposite to the one surface; An insulation layer exposing the bonding pads and formed on the one surface; Bumps formed on the respective bonding pads; A circuit pattern connected to each of the bumps and formed on the insulating layer; An encapsulation member surrounding the other surface and the side of the semiconductor chip; A solder mask formed on the insulating layer and the circuit pattern to expose a portion of the circuit pattern; And an external mounting member formed on the exposed circuit pattern.

The insulating layer has a cavity through which the bump passes.

In a method of manufacturing a semiconductor package according to an embodiment of the present invention, an insulating film and bonding pads in which a first layer having a cavity and a second layer disposed on the first layer and not having the cavity are stacked are arranged. Providing a semiconductor chip having one surface and the other surface opposite to the one surface; Forming bumps on each bonding pad of the semiconductor chip; Attaching the semiconductor chip onto the insulating film such that the bump penetrates the cavity; Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip; Removing the second layer of the insulating film so that each bump is exposed; Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump; Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And forming external mounting members on the exposed circuit patterns, respectively.

The preparing of the insulating film may further include a metal layer between the first layer having the cavity and the second layer having no cavity.

The step of attaching the semiconductor chip on the insulating film so that the bump penetrates the cavity is performed using heat, pressure, and ultrasonic waves.

Removing the second layer of the insulating film so that each bump is exposed is performed by a grinding process.

Removing the second layer of the insulating film to expose each bump, is removed using UV.

In a method of manufacturing a semiconductor package according to another embodiment of the present invention, an insulating film and bonding pads in which a soft first layer and a second layer having a higher strength than the first layer are stacked are disposed. Providing a semiconductor chip having one surface and the other surface opposite to the one surface; Forming bumps on each bonding pad of the semiconductor chip; Attaching the semiconductor chip onto the insulating film such that the bump penetrates the first layer and is inserted into the second layer; Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip; Removing the second layer of the insulating film so that each bump is exposed; Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump; Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And forming external mounting members on the exposed circuit patterns, respectively.

According to the present invention, after providing an insulating layer having a semiconductor chip in which bumps are formed in advance and a cavity through which the bumps are transmitted, the bumps are transmitted to a portion corresponding to the cavity to expose the surface of the bumps from the surface of the insulating layer. The semiconductor chip and the insulating layer are attached to each other, and then a circuit pattern is formed to be electrically connected to the bumps exposed from the surface of the insulating layer.

By doing so, the present invention can not only enhance the bonding strength between the bumps and the circuit patterns, but also can safely expose the bumps without the residue of foreign matter.

In addition, the present invention does not require an open process for exposing the bump and a peeling process for electrically connecting the circuit pattern to the bump part exposed by the open process in order to bond the bump and the circuit patterns. Through this, the present invention can reduce the manufacturing time and manufacturing cost.

In addition, the present invention can prevent the non-uniform pressing of the bump during lamination to improve the bonding strength between the bump and the circuit patterns.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

As illustrated, a semiconductor chip 100 having one surface on which a plurality of bonding pads 102 are disposed and the other surface facing the one surface is disposed. An insulating layer 106 exposing the bonding pads 102 is disposed on the one surface of the semiconductor chip 100. The insulating layer 106 has a cavity (not shown) to allow the bump 104 to pass therethrough, and includes, for example, epoxy, resin, and polymer.

Bumps 104 are formed on the respective bonding pads 102 exposed by the insulating layer 106. Circuit patterns 109 made of a conductive material are formed on the insulating layer 106 and connected to the bumps 104, respectively.

An encapsulation member 112 is formed on the other surface of the semiconductor chip 100 to surround the other surface and the side surface of the semiconductor chip 100. For example, the encapsulation member 112 includes an epoxy molding compound (EMC).

A solder mask 110 made of a material such as solder resist is formed on the insulating layer 106 and the circuit patterns 109 so that a part of each circuit pattern 109 is exposed, and the exposed circuit pattern ( On the parts, an external mounting member 114 such as a solder ball is formed.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.

2A and 2B, a semiconductor chip 100 having one surface a and the other surface b opposite to the surface a is provided. A plurality of bonding pads 102 are formed on one surface a of the semiconductor chip 100, and bumps 104 are formed on each of the bonding pads 102 of the semiconductor chip 100.

In addition, an insulating film 106c including a first layer 106a having a cavity C and a second layer 106b having no cavity C is stacked on the first layer 106a. do. The first layer 106a has the cavity C to allow the bump 104 to pass therethrough, and includes, for example, epoxy, resin, and polymer.

The second layer 106b may include, for example, poly vinyl chloride (PVC) and polyolefin (PO).

 Although not shown and described in detail, the first layer 106a may be formed of a layer having no cavity, like the second layer 106b having no cavity. In this case, it is preferable that the first layer having no cavity is formed of a soft layer, and the second layer formed on the soft first layer is formed of a layer having a higher strength than the first layer.

The insulating film 106c further includes a metal layer (not shown) between the first layer 106a having the cavity C and the second layer 106b having no cavity C. FIG. Can be formed. Here, the bump 104 may be coined using the metal layer.

Referring to FIG. 2C, the bump 104 penetrates the first layer 106a of the insulating film 106a on the insulating film 106c with the semiconductor chip 100 having the bump 104 formed thereon. Attach in the form. When the semiconductor chip 100 is attached to the insulating film 106c, the bumps 104 may fit to a portion corresponding to the cavity C of the first layer 106a, for example. It can be attached using heat, pressure and ultrasonic waves.

An encapsulation member 112 is formed on the other surface b of the semiconductor chip 100 to cover the other surface b and side surfaces of the semiconductor chip 100. The encapsulation member 112 includes, for example, an epoxy molding compound (EMC).

Meanwhile, when the semiconductor chip 100 is attached onto the insulating film 106c, the bumps 104 may pass through the second layer 106b of the insulating film 106c, as shown.

Referring to FIG. 2D, the second layer 106b of the insulating film 106c is removed to expose the surface portion of each bump 104.

Meanwhile, the second layer 106b of the insulating film 106c may be removed by a grinding process or may be removed using UV to expose the surface portion of each bump 104.

In this case, the second layer 106b may be removed only because the surface portion of the bump 104 is exposed so that only part of the second layer 106b may be removed. Thus, the second layer 106b may have the bump ( 104 may remain between.

Referring to FIGS. 2E and 2F, the second layer 106b is removed so that the circuit is electrically connected to the bump 104 on the exposed first bump 104 and the first layer portion of the insulating film adjacent thereto, respectively. The wiring 108 is formed. The circuit wiring 108 is made of a conductive material.

In the meantime, reference numeral 106 will be referred to as an insulating layer in order to comply with the description of claims 1 and 2. That is, the first layer of the insulating film remaining after the second layer 106b is removed is referred to as the insulating layer 106.

Referring to FIG. 2F, the circuit wiring is patterned to form a circuit pattern 109 on the exposed bump 104 and the insulating layer 106.

Referring to FIG. 2E, a solder mask 110 exposing a part of each circuit pattern 109 is formed on the insulating layer 106 including the circuit pattern 109 and the bump 104. The solder mask 110 may be a solder resist.

External mounting members 114 such as solder balls are formed on the exposed portions of the circuit pattern 109.

As described above, the present invention attaches the semiconductor chip and the insulating layer to expose the bump surface from the surface of the insulating layer through which the bump of the semiconductor chip with bumps is formed in advance and is exposed from the surface of the insulating layer. By forming a circuit pattern to be electrically connected to the bumps, not only the bonding strength between the bumps and the circuit patterns can be strengthened but also the bumps can be safely exposed without remaining of foreign matter.

In addition, the present invention does not require an open process for exposing the bump and a peeling process for electrically connecting the circuit pattern to the bump part exposed by the open process in order to bond the bump and the circuit patterns. Through this, the present invention can reduce the manufacturing time and manufacturing cost.

In addition, the present invention can prevent the non-uniform pressing of the bump during lamination to improve the bonding strength between the bump and the circuit patterns.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Description of the Related Art [0002]
100: semiconductor chip 102: bonding pad
104: bump 106: insulating layer
109: circuit patterns; 110: solder mask
112: sealing member 114: external mounting member
120: semiconductor package

Claims (8)

A semiconductor chip having one surface on which bonding pads are disposed and the other surface opposite to the one surface;
An insulation layer exposing the bonding pads and formed on the one surface;
Bumps formed on the respective bonding pads;
A circuit pattern connected to each of the bumps and formed on the insulating layer;
An encapsulation member surrounding the other surface and the side of the semiconductor chip;
A solder mask formed on the insulating layer and the circuit pattern to expose a portion of the circuit pattern; And
An external mounting member formed on the exposed circuit pattern;
Semiconductor package comprising a. The method of claim 1,
And the insulating layer has a cavity through which the bump passes. An insulating film having a first layer having a cavity and an insulating film having a second layer disposed on the first layer and having no cavity, and a bonding pad disposed thereon, and a semiconductor chip having the other surface opposite to the one surface, respectively. Preparing;
Forming bumps on each bonding pad of the semiconductor chip;
Attaching the semiconductor chip onto the insulating film such that the bump penetrates the cavity;
Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip;
Removing the second layer of the insulating film so that each bump is exposed;
Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump;
Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And
Forming external mounting members on the exposed circuit patterns;
Method of manufacturing a semiconductor package comprising a. The method of claim 3, wherein
The preparing of the insulating film may further include a metal layer between the first layer having the cavity and the second layer not having the cavity. The method of claim 3, wherein
And attaching the semiconductor chip onto the insulating film such that the bump penetrates the cavity, using heat, pressure, and ultrasonic waves. The method of claim 3, wherein
Removing the second layer of the insulating film so that each bump is exposed, manufacturing method of a semiconductor package, characterized in that performed by a grinding (Grinding) process. The method of claim 3, wherein
Removing the second layer of the insulating film so that each bump is exposed, manufacturing method of a semiconductor package, characterized in that for removing by using UV. Each of the semiconductor chip has a soft first layer, an insulating film having a second layer having a higher strength than the first layer, and one side on which the bonding pads are disposed, and a semiconductor chip having the other surface facing the one surface. Preparing;
Forming bumps on each bonding pad of the semiconductor chip;
Attaching the semiconductor chip onto the insulating film such that the bump penetrates the first layer and is inserted into the second layer;
Forming an encapsulation member to cover the other surface and side surfaces of the semiconductor chip;
Removing the second layer of the insulating film so that each bump is exposed;
Forming a circuit pattern on the first layer of the insulating film so as to be connected to each exposed bump;
Forming a solder mask on the first layer of the insulating film including the circuit pattern and the bump to expose a portion of the circuit pattern; And
Forming external mounting members on the exposed circuit patterns;
Method of manufacturing a semiconductor package comprising a.
KR1020100026304A 2010-03-24 2010-03-24 Semiconductor package and method of fabricating the same KR20110107122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100026304A KR20110107122A (en) 2010-03-24 2010-03-24 Semiconductor package and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100026304A KR20110107122A (en) 2010-03-24 2010-03-24 Semiconductor package and method of fabricating the same

Publications (1)

Publication Number Publication Date
KR20110107122A true KR20110107122A (en) 2011-09-30

Family

ID=44956645

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100026304A KR20110107122A (en) 2010-03-24 2010-03-24 Semiconductor package and method of fabricating the same

Country Status (1)

Country Link
KR (1) KR20110107122A (en)

Similar Documents

Publication Publication Date Title
KR100427925B1 (en) Semiconductor device and method for fabricating same
TWI425896B (en) Circuit board with buried conductive trace formed thereon and method for manufacturing the same
JP5068990B2 (en) Electronic component built-in board
US7511365B2 (en) Thermal enhanced low profile package structure
TWI413223B (en) Package substrate having semiconductor component embedded therein and fabrication method thereof
US7790515B2 (en) Semiconductor device with no base member and method of manufacturing the same
CN104051395A (en) Chip package-in-package and method thereof
KR20070045929A (en) Electronic-part built-in substrate and manufacturing method therefor
WO2014129351A1 (en) Semiconductor device and method for manufacturing same
JP2007158331A (en) Packaging method of semiconductor device
JP2010251408A (en) Semiconductor device and method of manufacturing the same, and electronic device
JP2008218979A (en) Electronic packaging and manufacturing method thereof
JP2009105334A (en) Semiconductor device and manufacturing method therefor
JP6242231B2 (en) Semiconductor device and manufacturing method thereof
JP2008159955A (en) Substrate incorporating electronic component
US8963318B2 (en) Packaged semiconductor device
US20130313697A1 (en) Semiconductor package
JP2010287870A (en) Printed circuit board, semiconductor device including the same, and method of manufacturing the same
JP2006261485A (en) Semiconductor device and manufacturing method therefor
KR20130139600A (en) Package of electronic device with strengthened bump interconnection and method for manufacturing the same
JP2008288489A (en) Process for producing built-in chip substrate
CN104659000A (en) Substrates Having Ball Lands, Semiconductor Packages Including The Same, And Methods Of Fabricating Semiconductor Packages Including The Same
CN110581107A (en) Semiconductor package and method of manufacturing the same
US20100219522A1 (en) Semiconductor device and method of manufacturing the same, and electronic apparatus
TW201606964A (en) Chip package substrate, chip packaging structure and manufacturing method of same