KR20110103388A - Error detection method and a system including one or more memory devices - Google Patents

Abstract

A system including at least one memory device and an error detection and correction method is presented. The memory device of the system includes an input for receiving a packet. The first portion of the packet may include at least one command byte, and the second portion of the packet may include parity bits to facilitate command error detection. The memory device may include an error manager configured to detect whether an error exists in the at least one command byte based on the parity bits and circuitry configured to provide the packet to the error manager.

Description

ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICES

[Cross reference to related application]

This application claims priority to US patent provisional application 61 / 138,575, filed December 18, 2008, US patent provisional application 61 / 140,147, filed December 23, 2008, and US patent application 12 / 418,892, filed April 6, 2009. All of which are incorporated herein by reference in their entirety.

Computers and other information technology systems generally include semiconductor devices such as memories. The semiconductor device is controlled by a controller and may form part of or separate from a central processing unit (CPU) of a computer. The controller has an interface for transmitting and receiving information with the semiconductor device. Errors can often occur for a variety of reasons for the transmitted and received information, and it is known that many known systems lack the ability to correct errors or at least lack a satisfactory ability to correct many errors.

It is an object of the present invention to provide an improved system comprising one or more memory devices.

According to an aspect of the invention, there is provided a memory device, comprising: as input for receiving a packet, a first portion of the packet includes at least one command byte, and a second portion of the packet enables at least command error detection A memory device is provided that includes an input, the parity bit being included. The error manager is configured to detect whether an error exists in at least one command byte based on the parity bit.

According to another aspect of the invention, a system comprising: a plurality of semiconductor memory devices; And a control device for communicating with the device. The control device includes a command engine for generating a packet destined for the memory device. The first portion of the packet includes at least one command byte and the second portion of the packet includes parity bits to enable command error detection. The output of the controller may output the packet to a first device of the plurality of semiconductor memory devices. A series-interconnect structure exists between the controller of the system and the semiconductor memory device, so that the system has a point-to-point ring topology.

According to another aspect of the invention, a method is provided that is executed in a memory device having an input for receiving a packet. The method comprises receiving a packet, wherein the first portion of the packet includes at least one command byte and the second portion of the packet includes parity bits to enable command error detection. . The method also includes detecting whether there is an error in the at least one command byte based on the parity bit.

According to another aspect of the present invention, there is provided a means for receiving a packet, wherein the first portion of the packet comprises at least one command byte, and the second portion of the packet contains a parity bit to enable command error detection. Including, there is provided an apparatus comprising the means. The apparatus also includes means for detecting whether there is an error in the at least one command byte based on the parity bits. The apparatus also includes means for providing the packet to an error manager.

According to another aspect of the invention, a system is provided comprising a plurality of semiconductor memory devices and controller means for communicating with the devices. The controller means includes means for generating a packet destined for a memory device. The first portion of the packet includes at least one command byte and the second portion of the packet includes parity bits to enable command error detection. The controller means also includes means for outputting the packet to a first of the plurality of semiconductor memory devices. A series-interconnect structure exists between the semiconductor memory devices of the system, and the system has a point-to-point ring topology.

According to another aspect of the present invention, a memory device having an input means for receiving a packet is provided. The memory device also includes means for receiving a packet. The first portion of the packet includes at least one command byte and the second portion of the packet includes parity bits for enabling command error detection. The memory device also includes means for detecting whether there is an error in the at least one command byte based on the parity bits.

Therefore, an improved system has been proposed that includes one or more memory devices.

Reference is made to the accompanying drawings by way of example.

1A is a block diagram of an example system for receiving parallel clock signals.
1B is a block diagram of an example system for receiving a source synchronous clock signal.
FIG. 2A is a block diagram of a system example that is similar to the system of FIG. 1A but is a more specific system example.
3 is a diagram of an example memory device.
4 is a diagram of an example memory controller.
5 illustrates parity bit calculation according to an embodiment.
6 is a flowchart illustrating a method of processing an error according to an exemplary embodiment.
7 is a timing diagram illustrating a broadcast status read command according to the embodiment.

The same or similar reference numerals are used in different drawings to indicate similar features of the examples shown in the drawings.

Examples of systems with ring topologies are disclosed in US Patent Publication 2008/0201548 A1, published August 21, 2008, "SYSTEM HAVING ONE OR MORE MEMORY DEVICES", US Publication 2008/0049505 Al, published February 28, 2008, "SCALABLE MEMORY" SYSTEM ", and US Publication 2008/0052449 Al, published February 28, 2008," MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM. " In the following detailed description, reference is made to various examples of commands, addresses and data formats, protocols, embedded device structures, bus transactions, and the like, and those skilled in the art will understand that details of other examples may be obtained by reference to the above-mentioned patent documents.

See FIGS. 1A and 1B. According to some embodiments, the command packet comes from the controller, passes around the ring through each memory device in a point-to-point manner, goes back and ends at the controller. 1A is a block diagram of an example system for receiving parallel clock signals, and FIG. 1B is a block diagram of the same system of FIG. 1A for receiving a source synchronous clock signal. The clock signal may be a single end clock signal or a differential clock pair.

In FIG. 1A, the system 20 includes a memory controller 22 having at least one of an output port Sout and an input port Sin and a memory device 24, 26, 28, and 30 connected in series. There is a series-interconnection structure between the controller device and the memory device. Although not explicitly classified in FIG. 1A, each memory device has a Sin input port and a Sout output port. The input and output ports consist of one or more physical pins or connections that interface the memory device to the system. In some examples, the memory device is a flash memory device. The present example of FIG. 1A includes four memory devices, but in other examples it may include a single memory device or any suitable number of memory devices. Therefore, since the memory device 24 is connected to Sout of the memory controller 22, if the first device of the system 20, the memory device 30 is connected to Sin of the memory controller 22, the system ( As the Nth or last device of 20), N is an integer greater than zero. The memory devices 26 to 28 are intermediate serially connected memory devices between the first and last memory devices. Each memory device may take a separate identification (ID) number or device address (DA) during the initial startup of the system, so that it is individually addressable. Several shared US patent applications describe a method for generating and assigning device addresses for serially connected memory devices in a system. See, eg, US Patent Publication 2007/0233917 Al "APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES" and US Patent Publication 2008/0080492 AI "PACKET BASED IDGENERATION FOR SERIALLY INTERCONNECTED DEVICES".

Since the data input of one memory device is connected to the data output of the previous memory device, memory devices 24 to 30 (FIG. 1A) are considered to be connected in series, with the exception of the first and last memory devices in the form of chains, It will form a series connection system structure. The channel of the memory controller 22 includes data, address and control information provided by the same pin or individual pins connected to the conductive lines. The example of FIG. 1A includes one channel, where one channel includes Sout and a corresponding Sin port. However, memory controller 22 may include an appropriate number of channels to accommodate individual chains of memory devices. In the example of FIG. 1A, memory controller 22 provides a clock signal CK, which is connected in parallel to the entire memory device.

In normal operation, memory controller 22 issues a command through its Sout port, which includes an operation code (op code), device address, operation address information for reading or programming, and optional data for register programming. . The command may be issued as a serial bitstream command packet, where the packet may be logically subdivided into segments of a predetermined size. Each segment may be one byte in size, for example. A bitstream is a series of bits provided over an order or time. The command is received by the first memory device 24, through its input port Sin, which compares the device address with its assigned address. If the addresses match, the memory device 24 executes a command. The command passes through its own output port Sout to the next memory device 26, and the same procedure is repeated. As a result, the memory device having a matching memory address called the selected memory device will perform the operation defined by the command. If the command is a read data command, the selected memory device will output the read data through its output port Sout (no label) passed serially through the intermediate memory device until it reaches the Sin port of the memory controller 22. will be. Since commands and data are provided in a serial bitstream, a clock is used for each memory device to clock in and clock out the serial bits and to synchronize internal memory device operation. This clock is used by the entire memory device in system 20.

Since the clock frequency used in the system according to FIG. 1A is relatively low, an uninterrupted full swing CMOS signal level can be used to provide strong data communication. This is also known to those skilled in the art, but referred to as low voltage transistor transistor logic (LVTTL) signaling.

Further performance improvements to the system 20 of FIG. 1A may be obtained by the system of FIG. 1B. The system 40 of FIG. 1B is similar to the system 20 of FIG. 1A except that the clock signal CK is provided in series to each memory device from the previous device and not necessarily from the memory controller 42. . Each memory device 44, 46, 48, and 50 receives a source synchronous clock at the clock input port and forwards it to the next device in the system through its clock output port. In some examples of system 40, clock signal CK is passed from one memory device to another through short signal lines. In such environments, there are no clock performance issues associated with parallel clock distribution schemes (such as loading by multiple devices), and CK can operate at high frequencies. Thus, system 40 can operate at a higher speed than system 20 of FIG. 1A. For example, High Speed Transceiver Logic (HSTL) signaling can be used to provide high performance data communication. In the HSTL signaling format, each memory device may receive a reference voltage that is used to determine the logic state of the input data signal. Another similar signaling format is the Stub Series Terminated Logic (SSTL) signaling format. Thus, the data and clock input circuits in the memory devices of systems 20 and 40 are structurally different from each other. Both HSTL and SSTL signaling formats are known to those skilled in the art.

Reference is made to FIG. 2A to provide a more specific example of a system of the type shown in FIG. 1B. In FIG. 2A, system 100 includes a memory controller 102 and four memory devices 104, 106, 108, and 110. The memory controller 102 provides a control signal in parallel with the memory device. These include a chip enable signal CE # and a reset signal RST #. In an exemplary use of CE #, the device is enabled when CE # is at a low logic level. In many of the devices previously considered, if the flash memory device starts a program or erase operation, CE # may be deasserted or driven to a high logic level. However, in one embodiment, the deassertion of CE # has the effect of disabling communication from Sin to Sout of the disabled serial memory device. Since serial memory devices are connected in a ring form, disabling any device destroys communication around the ring, and the memory controller becomes unable to communicate with the entire memory device in the memory system. As a result, CE # is a signal common to all serial memory devices and is used to bring the entire memory into a low power state. In one example using RST #, the memory device is set to the reset mode when RST # is at a low logic level. In reset mode, power is stabilized and the device prepares itself for operation by initializing the entire legacy state machine and resetting the settings and status registers to their default state. Memory controller 102 has clock output ports CKO # and CKO for providing complementary clock signals CK and CK # and clock input ports CKI # and CKI for receiving complementary clock signals from the last memory device of the system. ). Each memory device includes a clock synthesizer, such as a DLL or a PLL, for generating the phase of the received clock. Certain phases may be used to center the clock edge internally within the input data valid window to ensure reliable operation. Each memory device in FIG. 2A has clock output ports CKO # and CKO for passing a complementary clock signal to the clock input port of the next memory device. The last memory device 110 provides a clock signal back to the memory controller 102.

The channels of the memory controller 102 include data output port Sout, data input port Sin, command strobe input CSI, command strobe output CSO, data strobe input DSI, and data strobe output DSO. It includes. The output port Sout and the input port Sin may be one bit wide or n bit wide, where n is a positive integer depending on the characteristics of the memory controller. For example, if n is 1, one byte of data is received after eight data latching edges of the clock. The data latching clock edge may be for example a rising clock edge in a single data rate (SDR) operation or for example a rising and falling clock edge in a double data rate (DDR) operation. If n is 2, one byte of data is received after four latching edges of the clock. If n is 4, one byte of data is received after two latching edges of the clock. The memory device may be statically or dynamically configured for Sout and Sin of any width. Thus, in a structure where n is greater than 1, the memory controller provides data in a parallel bitstream. The CSI is used to control or enable latching command data appearing at the input port Sin, and has a pulse duration for delimiting time when the command is present at the data input port Sin. More specifically, the command data will have a duration measured by a number of clock cycles and the pulse duration of the CSI signal will have a corresponding duration. The DSI is used to enable the output port (Sout) buffer of the selected memory device to output read data, and has a pulse duration to limit the range of read data provided from the data output port (Sout) of the memory device. The memory controller may control the amount of data in the read transaction.

Since the presently described embodiment of FIG. 2A takes into account high speed operation, a fast signaling format such as, for example, the HSTL signaling format is used. Thus, each memory device is provided with a reference voltage VREF used by each memory device to determine the logic level of the signal received at the Sin, CSI and DSI input ports. The reference voltage VREF can be generated, for example, by another circuit on the printed circuit board and is set to a predetermined voltage level based on the voltage swing midpoint of the HSTL signal.

In the embodiment of FIG. 2A, each memory device is positioned on a printed circuit board such that the distance between the Sout output port pin on one device and the Sin input port pin of the next device on the ring is minimized. Alternatively, four memory devices can be recruited in a system-in-package (SIP) module that further minimizes the signal track length. The memory controller 102 and the memory devices 104-110 are connected in series to form a ring topology, which means that the last memory device 110 provides its output back to the memory controller 102. Therefore, those skilled in the art will understand that the distance between the memory device 110 and the memory controller 102 will be easily minimized.

In FIG. 2B, system 150 includes memory controller 152 and memory devices 154, 156, 158, and 160. The memory controller 152 is provided with a clock signal in parallel so that the clock output ports CKO # and CKO of each memory device are not present or disconnected. It can be designed to provide a functional similarity to that. Moreover, for the system of FIG. 2B when compared to the system of FIG. 2A, the signaling formats for data and strobe signals are different. For example, the signaling format for the system of FIG. 2B may be a full swing non-terminated LVTTL signal format. LVTTL signaling used in conjunction with a low clock frequency does not use a reference voltage (VREF). The memory device used only in the system of FIG. 2B does not require a VREF input. In such a case, VREF is set to a voltage level excluding the signaling intermediate point or set to indicate the LVTTL signaling used. For example, for such an apparatus, VREF may be set to VDD or VSS to indicate the LVTTL signaling and network configuration according to FIG. 2B as opposed to the HSTL signaling and network structure according to FIG. 2A.

According to an embodiment, the memory devices 104, 106, 108 and 110 of FIG. 2A and the memory devices 154, 156, 158 and 160 of FIG. 2B are designed for serial interconnection with other memory devices. It may be any type of memory device having a. According to the present embodiment, the memory devices of Figs. 2A and 2B may be identical and thus operate in both systems as they have input and output buffer circuits capable of operating with LVTTL input signals or HSTL input signals. Those skilled in the art will appreciate that memory devices may include input and output buffer circuits to operate with these LVTTL or HSTL signal other types of signal formats.

As mentioned above, each system shown in the previous figures includes one or more memory devices, and in accordance with an embodiment, FIG. 3 is an example of a memory device 200 that may be provided within any one of the previously described systems. It is a drawing about. The novel memory device 200 has a memory bank 202, where in at least some examples is a NAND flash cell array structure having a plurality (n) of erasable blocks. Each erasable block is divided into a plurality (m) of programmable pages. Each page consists of (j + k) bytes. The page is divided into a j-byte data storage area where data is stored and a separate k-byte area that is typically used for error management functions. Each page is for example 2112 bytes, of which 2,048 bytes will be used for data storage and 64 bytes will be used for error management. The memory bank 202 described above is accessed by a page. 3 illustrates a single memory bank 202, the memory device 200 may have one or more memory banks 202.

The command for accessing the memory bank 202 is received by the command register 214 from the controller through the I / O (input / output) circuit 213. The received command enters the command register 214 and holds there until execution. The control logic 216 converts the command into a form that can be executed against the memory bank 202. In general, a command enters the memory device 200 through the assertion of different pins on an external package of the chip, where different pins can be used to represent different commands. For example, the command may include read, program, erase, register read, and register write. For register writes, for example, memory device 200 may process a 5-byte-1 byte containing one byte per ID for a command and the remaining bytes are a payload—a register write command packet.

Read and program commands are executed in units of pages, and erase commands are executed in units of blocks. Also, in some examples of memory device 200, each of the various pins of the device is associated with one of the strobe ports, one of the data ports, or another port as described above in conjunction with FIGS. 2A and 2B. The I / O circuit 213 is shown here between the data pins and the internal components of the memory device 200, and the chip interface circuit 215 is shown between the other pins and the internal components of the memory device 200.

When a read or program command is received by the command register 214 via the I / O circuit 213, the address for the page in the memory bank 200 to which the command is associated is addressed by the I / O circuit 213. To the buffer and latch 218. From the address buffer and latch 218, the address information is then controlled and predecoder 206, sense amplifier (S / A) and data register 204 and row decoder 208 for accessing the page indicated by the address. Is provided. For a read operation, the data register 204 receives a complete page, which is then used for output from the memory device 200 by the I / O circuit 213 (not shown in more detail, although I / O). Provided in the following lower components of the O circuit 213: I / O buffers and latches, and then output drivers).

The address buffer and latch 218 determine the page where the address is located and provide the row decoder 208 with a row address corresponding to the page. The corresponding row is activated. The data register and S / A 204 sense the page and transfer data from the page to the data register 204. When data from the entire page is transferred to the data register, the data is read sequentially from the device through the I / O circuit 213.

Program commands are also processed page by page. The program command is received by the command register 214 through the I / O circuit 213 and the attached address is received by the address buffer 218 through the I / O circuit 213. Input data is received by I / O circuitry 213 and transmitted to data register 204. Once the entire input data is in the data register 204, the page in which the input data is to be stored is programmed with the input data.

The erase command is processed in blocks. The erase command is received by the command register 214 through the I / O circuit 213, and the block address is received by the address buffer 218 through the I / O circuit 213.

The illustrated memory device 200 optionally also includes an ECC manager 217. The ECC manager 217 enables error detection and correction according to the embodiment, which is described in more detail below. The illustrated ECC manager is shown in communication with the control logic 216, but in a separate example the ECC manager is configured for one or more address buffers and other illustrated components, such as latches 218 and command registers 214. It may include circuitry and logic to allow direct operation. Those skilled in the art will appreciate that there may be various known circuits in which packets may be provided to the ECC manager 217 from the input of the memory device 200.

The illustrated memory device 200 also includes one or more status registers 249 (many types of prior art status registers are known to those skilled in the art). Under control from control logic 216, the status register can provide state type information intended for control of the system and generally does not interfere with other information and data communicating through I / O circuitry 213. To provide this information. For example, information stored in status register 249 may be specifically communicated through one or more dedicated pins on the memory device. In this regard, an optional ECC generator 251 may be provided between the status register 249 and the I / O circuit 213 to facilitate this process.

As mentioned above, each of the systems shown in FIGS. 1A, 1B, 2A, and 2B includes a memory controller, and a block diagram of an example of a suitable memory controller 310 is shown in FIG.

4, the novel flash controller 310 shown includes a central processing unit (CPU) 312; And a memory 314 having, for example, a random access memory (RAM) 316 and a read only memory (ROM) 318. Those skilled in the art will appreciate that the flash controller 310 can be configured as a system on chip, system in package, or multiple chips. The illustrated flash controller 310 also includes a flash command engine 322, an error correction code (ECC) manager 324, and a flash device interface 326. In some examples, the flash device interface may include a memory controller port shown in FIG. 2A or a memory controller port shown in FIG. 2B, each of which is a memory controller (as described similarly in relation to a memory device). Associated with each pin of 310. For simplicity of illustration, instead of the entire pins of the flash controller 310, as shown explicitly in FIG. 4, it is indicated by a labeled flash device interface 326.

Referring to FIG. 4, the illustrated flash controller 310 includes a host interface controller 332 and a host interface 334. The CPU 312, memory 314, flash command engine 322 and host interface controller 332 are connected via a common bus 330. The host interface 334 may be a bus, a connection link, an interface (eg, Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA), Universal Serial Bus (USB), or PCI Express (PCI Express)). The host interface 334 is controlled by the host interface controller 332. The CPU 312 of the illustrated example operates with instructions stored in the ROM 318, and the processed data is Stored in the RAM 316. The flash command engine 322 interprets the commands, and the flash controller 310 controls the operation of the flash device via the flash device interface 326. Also, in some examples, The flash command engine 322 generates a memory device-destined packet, among other possible functions such as program data error code generation, read data error code checking and read data correction. 324 generates an error correction code (ECC) to ensure that certain commands are executed successfully and completely, the ECC manager enables error detection and correction according to embodiments described in more detail below. .

If a transmission error occurs in the command packet, one way to handle this error is to detect the error by comparing the received packet with the packet originally sent by the controller 310. This is a useful feature of the ring topology when compared to a bus topology without the inherent mechanism by which the controller detects whether the memory device has properly received the command. However, even with this error detection method of a ring topology, correcting an error until it is detected can be too slow. For example, if the command packet is a program or erase command and an error occurs at one of the address bits (any one of the device address, block address or page address), the program or erase operation may occur when the controller detects the error. May already have started, and data may inevitably be lost if the wrong address is overwritten or erased. If a non-program or non-erase command is received with a program or erase command in error, another potential unrecoverable error occurs. In general, the error read command is not a problem since the controller can easily request another read operation and discard the unwanted data.

In general, there is more concern about errors in commands than data written to or read from a memory array. There are many ways to embed error detection and correction codes in the data. Some data is more important and may have a stronger error scheme with high overhead and greater performance impact. The system designer can determine the level of robustness required. The problem addressed in at least some embodiments relates to errors in the command, address and register write fields. These errors cannot be solved with error detection and correction codes in the read and write data. There are many types of commands, addresses, and register write errors that can occur. In general, unintentional reads are not a problem because the data can be ignored and the controller 310 can reissue the command. The page read into the memory bank in use will simply be ignored. The error may occur somewhere in the ring before or after the target device.

Table 1: Possible fatal single bit error scenarios.

3 and 4, the target device 200 is checked for an error, and if an error is detected, the command is canceled. According to at least one embodiment, an additional error code byte is appended to each memory device-specific command packet that can be generated by the flash command engine 322. In some embodiments, the packet may be truncated by the target device to save power in the ring. There is no problem truncating the data portion of the read packet or combined command and program data packets. However, the command portion of the packet plus this additional error code byte should not be truncated by the device in the ring, and the controller 310 can check the entire packet for errors. If an error is detected, the controller 310 can read the device status register 249 of the memory device to determine whether the device in the ring detects the error and whether the command is actually executed. According to some examples, the target device, which is the device 200 corresponding to the device ID field in the first byte of the packet, calculates an error code based on the received command byte and compares the result with the received error code byte. . If there is a difference, the command is not executed and the transfer error flag will be set in the status register 249. Alternatively, if the error code supports error correction, the device 200 may correct the error and execute the command. There are many considered possibilities for error detection codes, for example Cyclic Redundancy Code (CRC), Bose-Chaudhuri-Hocquenghem (BCH) code, Reed-Solomon (RS) code; According to at least one embodiment, a hamming code is used that allows the location of a single bit error to be identified and to detect a full double bit error. Table 2 below details the bits of an example of a 7-byte command packet with additional error code bytes.

TABLE 2 Example of 7-byte command packet with additional error code bytes.

D0-D62-Data Payload Bits

P0-P64-Parity Bit

Since the location of a single bit error is known, the single bit error can be corrected. Also, a two bit error can be detected but not corrected. This type of code is known as SECDED code (Single Error Correction, Double Error Detection).

Therefore, the Hamming code provides single bit error correction and two bit error detection. The 7 byte payload shown in Table 2 encompasses the entire indication disclosed in the aforementioned US Patent Publication Nos. 2008/0049505 A1 and 2008/0052449 A1. However, the 8-bit Hamming code is sufficient to cover the 15 byte payload, allowing future extension to a large possible command set. For command packets of less than 7 bytes, non-existent data bits may be considered zero. The parity bit is calculated as shown in FIG.

If the parity bits calculated on the received data payload bits are different from the received parity bits, the difference implies the data bits being an error. For example, if D3 is received in error, the calculated parity bits P0, P1 and P2 are different from the received parity bits. Each parity bit P64, P32, P16, P8, P4, P2, P1 has a different '1' and they are the 7-bit binary words with the same '0', i.e. 0,0,0,0,0,1,1 This implies D3 where a single bit error occurred. P0 is always different when there is a single error in the payload. If there is a single '1' in the word (ie, only one calculated parity bit is different from the received parity bit), this indicates an error of the parity bit. If the calculated parity bit P0 is the same as the received P0 and at least one of the other parity is different, then there is a double error in the packet that cannot be corrected.

According to some embodiments, status register 249 (FIG. 3) includes additional bits indicating that a command packet failure has occurred.

In one example, each of one or more memory devices in a system having a point-to-point ring topology is a memory device that includes four banks. In such an example, it may be a fully occupied byte of a status register containing a wait / busy flag and a pass / bad flag for each memory bank. Therefore, additional bytes should be added as shown in Table 3 below.

Table 3: Status Register Definitions and Status Register Definitions Supporting Command Packet Bad Flags

R / Bn-Wait / busy flag for memory bank n ('0'-standby, '1'-busy)

P / Fn-pass / bad flag for memory bank n ('0'-pass, '1'-bad)

ERR-command packet error flag ('0'-no error, '1'-error detection and command execution)

The ERR flag for the embodiment described above is persistent. This will keep '1' until a read status register command is subsequently received and will be cleared thereafter.

If the device supports single bit error correction, the status register format shown in Table 4 below may be used.

[Table 4]: Status register definition, status register definition according to another embodiment supports command packet bad flag and single bit error correction.

R / Bn-Wait / busy flag for memory bank n ('0'-standby, '1'-busy)

P / Fn-pass / bad flag for memory bank n ('0'-pass, '1'-bad)

ERR1-Command Packet Single Bit Error Flag ('0'-No Error, '1'-Single Bit Error Detection and Correction)

ERR2-Command packet to bit error flag ('0'-no error or single bit error, '1'-two bit error detected and command not executed)

It is understood that the above state register transition details are different in different memory examples. For example, for memory having fewer than four memory banks, the possibility of using a single byte status register is considered. Also, the use of byte status registers greater than two is contemplated. In addition, the status bit may be persistent until a status read command is received or cleared upon receipt of any next valid command.

According to at least one embodiment, the controller 310 (FIG. 4) may generate a command packet error by recalculating the parity bits in the memory device or by simply comparing the received packet with each word of the transmitted command packet. It can be determined that it has occurred. The difference between the latter approach and the former is that the latter approach can identify multi-bit errors. If an error is detected, the controller 310 must issue a read status register command to the target device 200 to read the status register 249. Alternatively, in the case of a device address field error, the controller 310 may issue a status register read command to a device (hereinafter referred to as an error addressed device) which incorrectly believes to be the intended recipient of a command packet for determining the status of the error flag. Must be issued.

6 shows a flowchart form of a method 500 according to an embodiment. First in step 501, the controller receives a command packet after cycling around the ring, and the controller checks for errors in step 503. If there are no errors, there is no further action associated with the method shown, but if at least one error exists, step 504 is reached.

In step 504, a determination is made as to whether an error has occurred in the ID field. If no error occurs in the ID field, flow proceeds to step 509 (step 509 is described later herein). If an error occurs in the ID field, go to Step 506. In step 506, the controller 310 (FIG. 4) issues a read status command to the device addressed with the error, causes the status register of the device addressed with the error to be read as appropriate, and clears the persistent error bit indicating the status register. something to do. The controller then receives the device byte addressed in error at step 507.

Step 509 follows step 507. In step 509, the register of the target device is read, and as shown in the next step 510, the controller 310 (FIG. 4) shows an error byte of the target device (e.g., shown in Table 3 above) from the last device in the ring. Received "Byte 1"). This step will clear the persistent error bit indication at the target device. In some examples, such error bytes are provided to the ECC manager 324 via the flash device interface 326. Next, in step 520, the ECC manager 324 may determine whether the ERR bit of the error byte is '0' or '1'. If the ERR bit is '0', this means that the command is properly received at the target device and an error has occurred somewhere in the ring after the target device. In such a case, the command does not need to be reissued. If the ERRo bit is '1', this means that an error has occurred somewhere before the target device. If so, the command is reissued (step 530). As is well known to those skilled in the art, the command engine 322 may result in the reissue of commands under the instruction of the CPU 312.

In some embodiments, every device in the ring checks the command packet for errors and sets the error flag appropriately. The controller 310 (FIG. 4) may check the status register 249 (FIG. 3) of the entire device in the ring to determine whether an error has occurred and at which point the target device receives and executes the command. . Rather than sending a separate status register command to each device in the ring, another approach would be to use a broadcast status read command. Consistent with the aforementioned U.S. Patent Publication No. 2008/0049505 A1, there may be a special device address, for example, "11111111", which is recognized as a Broadcast Device Address. The general comparison with the local device ID is ignored for the broadcast device address.

7 is a timing diagram illustrating an operation of a broadcast status read command according to the embodiment. In the timing diagram, a plurality of devices may be provided, for example, by signal diagrams for D0, Q0 / D1, Q1 / D2 to provide clear schematic details with respect to the attributes of the broadcast status read command communicated via one or more devices in the ring. Is displayed.

According to the schematic embodiment of FIG. 7, device 0 receives a 2-byte broadcast read status command on D0 indicated by the CSI0 signal. After a few clock cycles, a data strobe signal DSI0 is received indicating that the contents of the status register should be output on Q0. Device 0 extends the output data strobe DSO0 by one clock cycle and outputs two byte status register data on Q0 in the timeslot indicated by the extended portion of the DSO0 strobe. In this way, the length of the data strobe pulses increases with each device on the ring to provide a burst of status information from all devices on the ring. This command is useful for determining where command packet errors occur in a ring when the entire device checks the command packets for errors. It is also useful in normal operation to check the status of multiple read, program, and erase operations occurring simultaneously in different memory devices.

A broadcast status read operation has been described in which all devices have the same length 2-byte status register. This technique is also applicable to devices with different status register lengths. For ring initialization, the controller reads the device information register of each device and determines the length of the status register of each device. During a broadcast register read operation, each device appends its status register information in bursts of any length and extends the output data strobes to encompass this attached information. Upon receiving the full burst of status information, the controller knows the number of bytes expected from each device and can separate this information.

Memory devices that support the error detection and / or correction described above can be programmed to disable error detection and / or correction. For example, upon reset, the memory device may disable error detection and correction. If the controller wants to employ error detection and / or correction, it may write one or more bits in a control register in each memory device, for example, to enable these functions. When the controller disables these functions, an additional parity bit at the end of each command packet can be removed to save one bus timeslot or loaded with null data to be ignored by the memory device. In this way, a low cost system does not need to support error correction and / or detection, but a common memory device can be provided to a low cost system in addition to those requiring such command packet error detection and / or correction.

In some examples, error detection and correction schemes similar to those described previously are provided and applied to read and write data. In certain implementations of this additional approach, the same parity check logic circuitry employed for the command packets can be utilized to reduce chip area and complexity. Table 5 below describes an example of a write data packet having a command parity byte and a data parity byte.

[Table 5]: Example of a write data packet having a command parity byte and a data parity byte

In the example of Table 5, bytes 0-4 contain command portions and functions as described above. Any number of write data bytes up to the full page size follows the command portion. The last byte in the packet is the write data parity byte calculated on the write data byte. If the same SECDED Hamming code described above is used, it will only provide a single error correction coverage of up to 15 bytes. After 15 bytes, the parity equation simply wraps around, and single bit error correction is no longer implemented. Alternatively, a stronger CRC code may be selected with good error coverage for large data packets. Separate error detection bits for commands and data may be provided in the status register.

For read data parity, it can be achieved in a similar manner. Reading data from the internal memory array, the memory device will calculate a parity byte to append to the end of the read data packet. The controller determines the number of bytes to be read by controlling the length of the data strobe signal. When the memory device detects the falling edge of the data strobe signal that terminates the read data burst, the memory device outputs a cumulative parity byte. Upon receiving the read data, the controller performs the same parity calculation and compares the result with the received parity byte appended to the end of the read data to determine if a bit error exists. This is particularly useful for register read commands, such as status register read commands, since there is no way for a user to superimpose error correction codes on register data. With normal read and write data to and from the memory array, the user can select an appropriate error detection code to store the data.

Although some embodiments have been shown and described with respect to a system having a point-to-point ring topology, there are, for example, multi-drop systems because there is a series connection configuration existing between the controller device of the system and the plurality of semiconductor memory devices of the system. Some other embodiments related to other types of systems that can be represented by will be understood.

Other variations are also possible. For example, in another example similar to the four-bank memory device example described above with respect to Tables 3 and 4, each of one or more memory devices of a system having a point-to-point ring topology is a bridging device and four discrete devices. It is a compound memory including a memory device. (For further details regarding the composite memory considered, see US Patent Application No. 12 / 401,963 "A Composite Memory Having a Bridging Device for Connecting Discrete Memory Devices to a System", the entire contents of which are incorporated by reference. In such an example, the status register may be present in the bridging device.

Multiple embodiments include, for example, NAND flash EEPROM device (s), NOR flash EEPROM device (s), AND flash EEPROM device (s), DiNOR flash EEPROM device (s), serial flash EEPROM device (s), DRAM device (s). S), SRAM device (s), Ferro RAM device (s), Magnetic RAM device (s), phase change RAM device (s), or any suitable combination of these devices. This technique is applicable to both memory and non-memory devices that communicate over a ring or other interconnection topology whether organized in a single bus master and multiple slave or multiple bus master configurations.

When an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element or an intermediate element may be present. In contrast, when an element is referred to herein as "directly connected" or "directly copuled" to another element, there is no intermediate element. Other terms used to describe the relationships between devices are similar in nature (ie, "between" and "directly between", "adjacent" and "directly adjacent"). Etc.).

Certain modifications and variations are possible to the described embodiment. Therefore, it is to be understood that the foregoing embodiments are intended to be illustrative, and not restrictive.

Claims (41)

As a memory device,
An input for receiving a packet, wherein the first portion of the packet includes at least one command byte and the second portion of the packet includes a parity bit to enable command error detection;
An error manager configured to detect whether an error exists in the at least one command byte based on the parity bit; And
Circuitry configured to provide the packet to the error manager
Including, the memory device. The memory device of claim 1, wherein the error manager is further configured to determine whether the memory device can correct an error. The memory device of claim 2, wherein the error manager is further configured to correct the error if the error can be corrected. The memory device of claim 1, wherein the error manager is further configured to identify whether the error is an error resulting in a memory operation that cannot be corrected. The memory device of claim 4, wherein the memory device is a flash memory device, and the memory operation comprises one selected from a program operation and an erase operation. The memory device of claim 4, wherein the error manager is further configured to provide, upon positive identification of such an error, an indication that the error is an error resulting in a memory operation that cannot be corrected. The memory device of claim 1, wherein the error manager can be selectively disabled. 8. The memory device of claim 7, further comprising a control register configured to store a plurality of bits of information and at least one bit indicating whether the error manager is disabled. The memory device of claim 1, wherein the memory device is a nonvolatile memory device. The memory device of claim 9, wherein the nonvolatile memory device is a NAND flash memory device. The memory device as claimed in claim 1, wherein the parity bit enables command error detection in accordance with a Hamming code error detection scheme. As a system,
A plurality of semiconductor memory devices; And
A controller device for communicating with the device, the controller device comprising:
A command engine for generating a packet destined for a memory device, the first portion of the packet including at least one command byte and the second portion of the packet including parity bits to enable command error detection. engine; And
An output capable of outputting the packet to a first device of the plurality of semiconductor memory devices,
And there is a series-interconnect structure between said controller device and said semiconductor memory device of said system, said system having a point-to-point ring topology. The system of claim 12, wherein the controller device further comprises an error manager. The system of claim 13, wherein each of the plurality of semiconductor memory devices comprises an error manager. 15. The apparatus of claim 13, wherein the controller device is configured to receive an error addressed device error byte, and wherein the error manager is configured to determine whether the device prior to the intended target device is addressed as an error. The system is configured to process bytes. The system of claim 12, wherein the command engine is configured to cause a reissue of a command if the device prior to the intended target device is addressed in error. The method of claim 12, wherein the command engine is configured to receive a broadcast that can be received by each of the plurality of semiconductor memory devices so that information in each status register of each of the plurality of semiconductor memory devices can be provided to the controller device in a sequential manner. A system capable of generating cast commands. 18. The apparatus of claim 17, wherein the controller device determines at what point in the ring topology an error has occurred and whether the target device has received and executed a command issued by the controller device prior to the broadcast command. Further comprising an error manager configured to process the information. 19. The system of any of claims 12-15 and 17-18, wherein the parity bits enable command error detection in accordance with a Hamming code error detection scheme. 19. The system of any of claims 12-15 and 17-18, wherein the plurality of semiconductor memory devices is a nonvolatile memory device. The system of claim 20, wherein the nonvolatile memory device is a NAND flash memory device. A method executed in a memory device having an input for receiving a packet, the method comprising:
Receiving a packet, wherein the first portion of the packet includes at least one command byte and the second portion of the packet includes parity bits to enable command error detection; And
Detecting whether there is an error in the at least one command byte based on the parity bits
Including, the method. The method of claim 22, further comprising determining whether the memory device can correct an error. 24. The method of claim 23, further comprising correcting the error if the error can be corrected. The method of claim 22, further comprising identifying whether the error is an error resulting in an uncorrectable memory operation. 27. The method of claim 25, wherein the memory operation consists of a selected one of a program operation and an erase operation. 26. The method of claim 25, further comprising generating, upon positive identification of such an error, a device internal indication that the error results in a memory operation that cannot be corrected. 28. The method of any one of claims 22 to 27, wherein the parity bits enable command error detection in accordance with a Hamming code error detection scheme. As a device,
Means for receiving a packet, wherein the first portion of the packet comprises at least one command byte and the second portion of the packet includes parity bits for enabling command error detection;
Means for detecting whether an error exists in the at least one command byte based on the parity bit; And
Means for providing the packet to an error manager
Including, the device. 30. The apparatus of claim 29, wherein the means for detecting is configured to determine whether the apparatus can correct the error. 31. The apparatus according to claim 30, wherein the detecting means is further configured to correct the error if the error can be corrected. 30. The apparatus of claim 29, wherein the means for detecting is further configured to identify whether the error is an error resulting in an uncorrectable memory operation. 33. The apparatus of claim 32, wherein the means for detecting is further configured to provide, upon positive identification of such an error, an indication of the error resulting in the memory operation that the error cannot be corrected. 34. The apparatus according to any one of claims 29 to 33, wherein the detection means can be selectively disabled. As a system,
A plurality of semiconductor memory devices; And
Controller means for communicating with the apparatus, the controller means being:
Means for generating a packet destined for a memory device, wherein the first portion of the packet comprises at least one command byte and the second portion of the packet includes parity bits for enabling command error detection. ; And
Means for outputting the packet to a first one of the plurality of semiconductor memory devices,
And a series-interconnect structure between the semiconductor memory devices of said system, said system having a point-to-point ring topology. 36. The system of claim 35, wherein the controller means further comprises an error manager. 37. The system of claim 36, wherein each of the plurality of semiconductor memory devices comprises an error manager. 37. The apparatus of claim 36, wherein the controller means is configured to receive an error addressed device error byte, and wherein the error manager is configured to determine whether the device prior to the intended target device is addressed as an error. The system is configured to process bytes. 39. The system of any one of claims 35 to 38, wherein the generating means is configured to cause a reissue of a command if the device before the intended target device is addressed in error. 36. The apparatus of claim 35, wherein the generating means is received by each of the plurality of semiconductor memory devices so that information in each of the register means of each of the plurality of semiconductor memory devices can be provided to the controller means in a sequential manner. A system capable of generating cast commands. As a memory device,
Means for receiving a packet, wherein the first portion of the packet comprises at least one command byte and the second portion of the packet includes parity bits for enabling command error detection;
Means for detecting whether an error exists in the at least one command byte based on the parity bit
Including, a memory device.

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