KR20110088916A - Semiconductor memory device and operating method the same - Google Patents

Semiconductor memory device and operating method the same Download PDF

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KR20110088916A
KR20110088916A KR1020100008648A KR20100008648A KR20110088916A KR 20110088916 A KR20110088916 A KR 20110088916A KR 1020100008648 A KR1020100008648 A KR 1020100008648A KR 20100008648 A KR20100008648 A KR 20100008648A KR 20110088916 A KR20110088916 A KR 20110088916A
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bit line
bit lines
test
cell0
line bars
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KR1020100008648A
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Korean (ko)
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송청기
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

PURPOSE: A semiconductor memory device and an operation method thereof are provided to reduce a test data input time by successively activating a plurality of word lines after modulating test data in a plurality of bit lines and bit line bar. CONSTITUTION: In a semiconductor memory device and an operation method thereof, a data sense amplifying operation controller(400) compulsorily activates sense amplification enable signal in a test operation mode. The sense amplification enable signal determines the operation of a plurality of sense amplifiers. A plurality of sense amplifiers are connected between a plurality of bit lines and a plurality of bit line bars. A test equalizing operation control part(420) compulsorily deactivates a voltage level equalizing control signal. The voltage level equalizing control signal controls the voltage level equalizing operation of a plurality of bit line and a plurality of bit line bars. The column address variable part successively changes a column address. The column address variable part respectively modulates a test data in the plural of bit lines and bit line bar.

Description

Semiconductor memory device and its operation method {SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly, to circuits and methods for testing semiconductor memory devices.

1 is a circuit diagram illustrating a cell array configuration of a general semiconductor memory device.

Referring to FIG. 1, a cell array of a general semiconductor memory device may include a plurality of bit lines BL0, BL1,..., BLN, a bit line bar (/ BL0, / BL1,..., / BLN) and a plurality of word lines. A plurality of cells (CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N) and a plurality of bit lines configured in an array form by WL0, WL1, ..., WLM A plurality of sense amplifiers SA0, SA1, ..., SAN connected between (BL0, BL1, ..., BLN) and bit line bars (/ BL0, / BL1, ..., / BLN), and a plurality of sense amplifiers ( On / off control that the operating power sources VCORE, VSS are provided to SA0, SA1, ..., SAN) by using the core voltage supply control signal SPA and ground voltage supply control signal SNA. Sense amplification operation control unit 10 for controlling the on / off, and voltage level equalizing operation of the plurality of bit lines (BL0, BL1, ..., BLN) and bit line bars (/ BL0, / BL1, ..., / BLN) Control-bit A plurality of equalizing operation controllers SAE0, SAE1, ..., SAEN are used to use the line equalizing control signal BLEQ and the sense amplifying equalizing control signal SAEQ.

2A is a flowchart illustrating a method of writing data to a cell array of a general semiconductor memory device in a test operation mode according to the related art.

FIG. 2B is a timing diagram illustrating a method of writing data to a cell array of a typical semiconductor memory device in a test operation mode according to the related art.

Referring to FIG. 2A, in a test operation mode that is generally performed at a low frequency, when the value of the column address YS is determined due to the cell data retention time, the value is fixed. The data is stored in each of the plurality of word lines WL0, WL1,..., WLM while increasing the value of the row address in the state. Thereafter, while the column address YS is increased by one, the data is stored in each of the plurality of word lines WL0, WL1, ..., WLM while increasing the value of the row address. This operation is repeated repeatedly until the column addresses YS all increase.

Referring to FIG. 2B, in the test operation mode according to the related art, when a row address is determined, a corresponding word line WLO is activated, and a column address YS having a fixed value is activated to transmit test data to a cell. After writing, it can be seen that the operation of precharging the activated word line WL0 is repeated.

Accordingly, the time required for writing all the test data into the cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N is 2 gigabytes. Assuming that it is a byte (2Gbyte), it is as shown in <Equation 1>.

Figure pat00001

<N means the number of column addresses, 2 ^ 14 = 16384, M means the number of row addresses, 2 ^ 7 = 128>

In this state, assuming that tRCD, tWR, tRP = 20 ns, (CWL + tCCD) * tCK = 50 ns, the result of Equation 1 is (60 ns + 50 ns) * 16384 * 128 = 230 ms so that the entire semiconductor memory device It can be seen that the time required for writing test data into cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N is 230ms.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems in the prior art, and an object thereof is to provide a circuit and a method capable of reducing the time taken to write test data to a semiconductor memory device.

According to an aspect of the present invention for achieving the above object to be solved, a plurality of bit lines and a bit line bar, the driving is controlled by the column address respectively-and the plurality of word lines-driving by the row address, respectively 10. A semiconductor memory device comprising a plurality of cells configured in an array form by being controlled, comprising: sense amplifier enable for determining whether to operate a plurality of sense amplifiers connected between the plurality of bit lines and bit line bars, respectively. A test detection amplification operation control unit for forcibly activating a signal in a test operation mode; A test equalizing operation controller for forcibly deactivating a voltage level equalizing control signal for controlling voltage level equalizing operations of the plurality of bit lines and the bit line bars in the test operation mode; A column address changing unit configured to sequentially change the column addresses to load test data set on the plurality of bit lines and bit line bars, respectively; And a row address changer configured to sequentially change the row addresses to store the test data respectively loaded in the plurality of bit lines and the bit line bars in the plurality of cells.

In addition, according to another aspect of the present invention for achieving the above object to be solved, a plurality of bit lines and bit line bars, each of which is controlled by a column address-and a plurality of word lines-driven by a row address A method of operating a semiconductor memory device including a plurality of cells configured in an array form, each controlled by: a sensing amplification enable signal in response to a test operation mode entry signal, between the plurality of bit lines and the bit line bars. Forcibly activating on / off whether a plurality of sense amplifiers, each connected to an on / off operation; Forcibly deactivating a voltage level equalizing control signal in response to the test operation mode entry signal, for turning on / off voltage level equalizing operations of the plurality of bit lines and the bit line bars; Loading the set test data on the plurality of bit lines and the bit line bars by sequentially changing the column addresses while deactivating the row addresses; And after the loading of the test data is completed, the row addresses are sequentially changed while the column address is inactivated, and the test data stored in the plurality of bit lines and bit line bars are stored in the plurality of cells, respectively. It provides a method of operating a semiconductor memory device comprising the step of.

The present invention described above allows test data to be loaded on a plurality of bit lines and bit line bars when entering a test operation mode, and then sequentially activates a plurality of word lines, thereby greatly reducing the time required to write test data to a semiconductor memory device. It can be effected.

1 is a circuit diagram illustrating a cell array configuration of a general semiconductor memory device.
2A is a flowchart illustrating a method of writing data to a cell array of a general semiconductor memory device in a test operation mode according to the related art.
FIG. 2B is a timing diagram illustrating a method of writing data to a cell array of a typical semiconductor memory device in a test operation mode according to the related art.
3 is a flowchart illustrating a method of writing data to a cell array of a general semiconductor memory device in a test operation mode according to an exemplary embodiment of the present invention.
4 is a circuit diagram illustrating in detail a circuit to be added to a general semiconductor memory device for implementing a test operation mode according to an exemplary embodiment of the present invention.
FIG. 5 is a timing diagram illustrating a method of writing data to a cell array of a general semiconductor memory device in a test operation mode according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

The embodiment of the present invention can be applied when performing a test operation in a general semiconductor memory device, and the configuration of the general semiconductor memory device is the same as that described in FIG.

Therefore, referring to FIG. 1 again, a configuration of a cell array included in a general semiconductor memory device will be described. A plurality of bit lines BL0, BL1, ..., BLN and bit line bars / BL0, / BL1, ..., / BLN) and a plurality of cells (CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ... formed in an array form by a plurality of word lines WL0, WL1, ..., WLM). , CELLM_N, a plurality of sense amplifiers SA0, SA1, ..., connected between the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN, respectively. SAN) and the operation power supply (VCORE, VSS) are provided to the plurality of sense amplifiers SA0, SA1, ..., SAN. The amplification operation control section 10 which controls the operation on / off by a plurality of bit lines and a plurality of bit lines BL0, BL1, ..., BLN and bit line bars (/ BL0, / BL1, ..., / BLN). Voltage And a to plurality of equalizing operation control for (SAE0, SAE1, ..., SAEN) - bell-equalizing (equalizing) controls the operation-bit line equalizing control signal (BLEQ) and the sense amplifier equalization using a control signal (SAEQ).

3 is a flowchart illustrating a method of writing data to a cell array of a general semiconductor memory device in a test operation mode according to an exemplary embodiment of the present invention.

Referring to FIG. 3, it can be seen that an operation called a background write is performed before a plurality of word lines WL0, WL1,..., WLM are sequentially active-precharged. .

That is, when entering the test operation mode, an operation called a background write is first performed, and then a plurality of word lines WL0, WL1,..., WLM are sequentially activated by sequentially increasing row addresses. -Precharged.

On the other hand, it can be seen that there is no operation of sequentially increasing the column address YS in the flowchart shown in FIG. 3, which sequentially increases the column address YS in an operation called a background write. This is because the operation to add.

That is, an operation of sequentially increasing the column address YS during the background write operation, which is the first operation performed while entering the test operation mode, is added to the plurality of cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0. , CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N to write test data to a plurality of bit lines (BL0, BL1, ..., BLN) and bit line bars (/ BL0, / BL1, ..., / BLN).

4 is a circuit diagram illustrating in detail a circuit to be added to a general semiconductor memory device for implementing a test operation mode according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a circuit to be added to a general semiconductor memory device for implementing a test operation mode according to an embodiment of the present invention includes a plurality of bit lines BL0, BL1,..., BLN and a bit line bar (//). In the test operation mode, the sense amplifier enable signals SPA and SNA for determining whether to operate the plurality of sense amplifiers SA0, SA1, ..., SAN connected between BL0, / BL1, ..., / BLN, respectively. Equivalent voltage level equalization of the test sense amplification operation control unit 400 for forcibly activating, the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN. And a test equalizing operation controller 420 for forcibly deactivating the voltage level equalizing control signals BLEQ and SAEQ in the test operation mode.

Here, the sense amplifier enable signals SPA and SNA are core voltage supply control signals for controlling the supply of the core voltage VCRE to the plurality of sense amplifiers SA0, SA1,..., SAN as described above. And a ground voltage supply control signal SNA for controlling supply of the SPA and the ground voltage VSS.

Therefore, forcibly activating the sense amplification enable signals SPA and SNA in the test operation mode means that the bit lines are sensed and amplified in response to the test operation mode entry signal TM_EN being activated with logic 'high'. The data of (BL0, BL1, ..., BLN) and the bit line bars (/ BL0, / BL1, ..., / BLN) are kept until the test operation mode entry signal TM_EN is deactivated to logic 'low'. It means to fix it.

That is, in the present invention, a plurality of bit lines BL0, BL1, ..., BLN and bit line bars (/ BL0, / BL1) are used as the place where the test data stays through the background write operation described with reference to FIG. ,…, / BLN).

The voltage level equalization control signals BLEQ and SAEQ include a bit line equalization control signal BLEQ and a sense amplifier equalization control signal SAEQ.

At this time, equalizing the voltage levels of the bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN means that the bit lines BL0, BL1, ..., BLN are equalized. ) And the bit line bars (/ BL0, / BL1, ..., / BLN) to have the same voltage level, which generally frees a plurality of word lines (WL0, WL1, ..., WLM) This operation is performed together with the operation of precharging.

However, since the test data is to be stored in the bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN in the test operation mode entry state of the present invention, the bit line The voltage levels of (BL0, BL1, ..., BLN) and bit line bars (/ BL0, / BL1, ..., / BLN) must not be the same.

Therefore, in the test operation mode according to the embodiment of the present invention, even when an operation of precharging a plurality of word lines WL0, WL1,..., WLM is performed, the bit lines BL0, BL1,..., BLN and the bit line bar (/ The voltage level equalization control signals BLEQ and SAEQ are forcibly deactivated so that an equalizing operation is not performed between BL0, / BL1, ..., / BLN.

As described above, in the test operation mode according to the exemplary embodiment of the present invention, the bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN are shown through the simple circuit shown in FIG. You can achieve the same effect as storing test data in between.

Of course, in order to store the test data between the bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN, after entering the test operation mode, it is shown in FIG. The circuit as described above performs an operation, and then the test data set by sequentially changing the column address YS is divided into a plurality of bit lines BL0, BL1, ..., BLN and bit line bars (/ BL0, / BL1). ,…, / BLN).

The operation necessary for the test data set as described above to be carried on the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN, respectively, is a sequential column address. Since only the counting operation is performed, it can be easily implemented through a column address decoder that is already implemented in a general semiconductor memory device.

In addition, if a column address decoder is not available, it may be possible to add a column address counter to a general semiconductor memory device that can change column addresses sequentially.

The detailed circuit and operation of the above-described column address decoder and column address counter are well known techniques, and thus will not be described in detail here.

The test data loaded on the bit lines BL0, BL1, ..., BLN and the bit line bars (BL0, / BL1, ..., / BLN) may have a row address that is sequentially changed, and thus a plurality of word lines WL0, WL1, When the WLMs are sequentially activated, the test data carried on the bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN is stored in a plurality of cells CELL0_0 and CELL0_1. , ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N).

For example, assuming that N bit test data is loaded on bit lines BL0, BL1, ..., BLN and bit line bars / BL0, / BL1, ..., / BLN, a plurality of word lines WL0, WL1 N bits of test data are stored in the N cells CELL0_0, CELL0_1, ..., CELL0_N connected to the first word line WL0 in response to the activation of the first word line WL0 among the ..., WLM. . Thereafter, when the first word line WL0 is precharged and the second word line WL1 is activated, N cells CELL1_0, CELL1_1, ..., CELL1_N connected to the second word line WL0 in response. N bits of test data are stored. If this process is repeated M times the number of word lines, the test data is stored in all the cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N. Can be written.

Here, in order to sequentially activate the plurality of word lines WL0, WL1,..., WLM, an operation of sequentially counting row addresses is required. This operation can be easily performed through a row address decoder already existing in a conventional semiconductor memory device. Can be implemented.

In addition, if a row address decoder is not available, a row address counter capable of sequentially changing row addresses may be added to a general semiconductor memory device.

The detailed circuit and operation of the above-described row address decoder and row address counter are well known techniques, and thus will not be described in detail here.

FIG. 5 is a timing diagram illustrating a method of writing data to a cell array of a general semiconductor memory device in a test operation mode according to an exemplary embodiment of the present invention.

Referring to FIG. 5, upon entering the test operation mode, the sense amplifier enable signals SPA and SNA are forcibly activated so that a plurality of sense amplifiers SA0, SA1,..., SAN can be forcibly operated. .

In addition, the voltage level equalization control signals BLEQ and SAEQ are forcibly deactivated so that the voltage levels of the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN Do not let them be the same.

Due to this operation, the plurality of bit lines BL0, BL1, ..., BLN and bit line bars (/ BL0, / BL1, ..., / BLN) once sensed and amplified in the timing diagram shown in FIG. 5 continue to be amplified. Although not shown directly in the drawing, the voltage level may be equalized again after the test operation mode is terminated.

As described above, the operation of the background write operation is performed when the voltage levels of the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars (BL0, / BL1, ..., / BLN) are sensed and amplified. It can be seen that the operation is performed. Looking at the operation in detail, it can be seen that the row address is an operation of sequentially changing only the column address YS while all of the row addresses are inactivated.

When the voltage levels of the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN are sensed and amplified, only the column address YS is sequentially changed. The set test data previously waiting on the local line is sequentially loaded on the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN.

Therefore, after all the column addresses YS are counted, the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN store the test data. It is in the same state as that.

Thus, after all column addresses YS are counted and the test data is loaded on the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN, , As in the drawing

When the row addresses are sequentially counted while the column address YS is inactivated to sequentially activate the plurality of word lines WL0, WL1,..., WLM, the plurality of bit lines BL0, BL1,..., BLN ) And the test data contained in the bit line bars (/ BL0, / BL1, ..., / BLN) are sequentially stored in a plurality of cells (CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1). , ..., CELLM_N).

In this way, when all the row addresses are counted and the test data is written to a plurality of cells (CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N), the test operation mode becomes May be terminated.

In the test operation mode of the semiconductor memory device according to the embodiment of the present invention, a plurality of cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N Assuming that the time required to write data is a capacity of the semiconductor memory device is 2 gigabytes (2Gbyte) can be defined as follows.

First, the time taken to load test data on a plurality of bit lines BL0, BL1, ..., BLN and bit line bars / BL0, / BL1, ..., / BLN is shown in Equation 2.

Figure pat00002

<N means the number of column addresses, 2 ^ 14 = 16384

The data contained in the plurality of bit lines BL0, BL1, ..., BLN and the bit line bars / BL0, / BL1, ..., / BLN is stored in the plurality of cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, The time taken to store CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N) is shown in Equation (3).

Figure pat00003

<M means the number of row addresses, 2 ^ 7 = 128>

In this state, it can be assumed that tRCD, tWR, tRP = 20 ns, tRAS = 100 ns, tCCD * tCK = 40 ns, so that the multiple bit lines (BL0, BL1, ..., BLN) and bit line bars (/ BL0, / BL1) , ..., / BLN) takes 1.64ms to load test data, and is loaded on a plurality of bit lines (BL0, BL1, ..., BLN) and bit line bars (/ BL0, / BL1, ..., / BLN). The time taken to store the existing data in a plurality of cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N becomes 123us.

Therefore, the plurality of cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1, ..., CELLM_N in the test operation mode of the semiconductor memory device according to the embodiment of the present invention as described above. The time required to write the data in the) is about 1.76ms. This means that only 1% of the time is required as compared to 230 ms in the test operation mode of the semiconductor memory device according to the prior art.

As described above, according to the exemplary embodiment of the present invention, the test data is stored in the plurality of cells CELL0_0, CELL0_1, ..., CELL0_N, CELL0_0, CELL0_1, ..., CELL0_N, ..., CELLM_0, CELLM_1 in the test operation mode of the semiconductor memory device. When inserting into ... CELLM_N, the set test data is first loaded on a plurality of bit lines BL0, BL1, ..., BLN and bit line bars / BL0, / BL1, ..., / BLN, and then By using the method of sequentially activating the word lines WL0, WL1,..., WLM, the time taken to write test data into the semiconductor memory device can be greatly reduced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

400: test detection amplification operation control unit
420: test equalization operation control unit

Claims (2)

A semiconductor memory device including a plurality of cells configured in an array by a plurality of bit lines and bit line bars, each of which is controlled by column addresses, and a plurality of word lines, each of which is controlled by row addresses. To
A test sense amplifier operation control unit for forcibly activating a sense amplifier enable signal in a test operation mode for determining whether a plurality of sense amplifiers connected between the plurality of bit lines and the bit line bars are operated;
A test equalizing operation controller for forcibly deactivating a voltage level equalizing control signal for controlling voltage level equalizing operations of the plurality of bit lines and the bit line bars in the test operation mode;
A column address changing unit configured to sequentially change the column addresses to load test data set on the plurality of bit lines and bit line bars, respectively; And
A row address changing unit configured to sequentially change the row addresses to store the test data respectively loaded on the plurality of bit lines and bit line bars in the plurality of cells
And the semiconductor memory device.
A semiconductor memory device including a plurality of cells configured in an array by a plurality of bit lines and bit line bars, each of which is controlled by column addresses, and a plurality of word lines, each of which is controlled by row addresses. In the operation method of,
Forcibly activating a sense amplifier enable signal in response to a test operation mode entry signal, determining on / off whether to operate a plurality of sense amplifiers connected between the plurality of bit lines and the bit line bars, respectively;
Forcibly deactivating a voltage level equalizing control signal in response to the test operation mode entry signal, for turning on / off voltage level equalizing operations of the plurality of bit lines and the bit line bars;
Loading the set test data on the plurality of bit lines and the bit line bars by sequentially changing the column addresses while deactivating the row addresses; And
After the loading of the test data is ended, the row address is sequentially changed while the column address is inactivated to store the test data in the plurality of bit lines and bit line bars, respectively, in the plurality of cells. step
Method of operating a semiconductor memory device comprising a.
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