KR20110078733A - Method of programming a non volatile memory device - Google Patents

Method of programming a non volatile memory device Download PDF

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Publication number
KR20110078733A
KR20110078733A KR1020090135615A KR20090135615A KR20110078733A KR 20110078733 A KR20110078733 A KR 20110078733A KR 1020090135615 A KR1020090135615 A KR 1020090135615A KR 20090135615 A KR20090135615 A KR 20090135615A KR 20110078733 A KR20110078733 A KR 20110078733A
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South Korea
Prior art keywords
program
memory cell
voltage
cell group
program voltage
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KR1020090135615A
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Korean (ko)
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최대일
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주식회사 하이닉스반도체
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Publication of KR20110078733A publication Critical patent/KR20110078733A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: A method for programming a non volatile memory device is provided to prevent a program voltage which is gradually boosted from being applied to a group of memory cells, thereby enhancing the electrical features of the memory cells. CONSTITUTION: A first program voltage(1) is applied to a first memory cell group for programming into a first state. A second program voltage(2) is applied to first and second memory cell groups for programming into a second state whose threshold voltage distribution is lower than the first data. A third program voltage(3) is applied to the second memory group and a third memory cell group for programming into a third state whose threshold voltage distribution is lower than the second data. A fourth program voltage(4) is applied to the third memory cell group.

Description

Method of programming a non volatile memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of programming a nonvolatile memory device, and more particularly, to a method of programming a memory cell group according to an initial threshold voltage distribution using a gradually falling program voltage.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

Recently, in order to increase the program speed of a nonvolatile memory device, a program using an incremental step pulse programming (ISPP) method of programming a selected page several times while gradually increasing the word line bias voltage for each step (ie, program cycle). The method is implemented.

1A is a graph illustrating a program voltage according to an ISPP scheme according to the related art.

1B is a graph illustrating changes in threshold voltages during a program operation using a conventional ISPP scheme.

Referring to FIGS. 1A and 1B, a program method according to a conventional ISPP scheme is described below.

If the initial threshold voltage distribution of the memory cells is distributed in the A, B, and C regions as shown in FIG.

First, the threshold voltage distribution is shifted to the right by applying the initial ISPP program voltage (①). At this time, even if the ISPP program voltage ① is applied for a predetermined time or more, the threshold voltage distribution no longer moves to the right, and the threshold voltage distributions of the memory cells remain in the B and C regions. After that, the second ISPP program voltage ② is applied by the step voltage higher than the initial ISPP program voltage ①. As a result, the threshold voltage distributions of the memory cells remaining in the B and C regions are shifted to the right. At this time, even if the ISPP program voltage ② is applied for a predetermined time or more, the threshold voltage distribution no longer moves to the right, and the threshold voltage distribution of the memory cells may remain in the C region. Accordingly, the third ISPP program voltage ③ is applied to increase the step voltage by more than the ISPP program voltage ②. As a result, the threshold voltage distribution of the memory cells remaining in the C region moves to the right to be distributed in the D region. In this way, the ISPP program voltage is gradually increased to remain in the target threshold voltage distribution region to proceed with the program operation.

However, according to the above-described ISPP program method, a memory cell programmed to a target threshold voltage distribution region by an initial low ISPP program voltage is continuously applied with gradually increasing ISPP program voltages, thereby deteriorating electrical characteristics of the memory cell. . These cells are programmed too quickly during the next program operation, which adversely affects cell uniformity of the memory device.

The technical problem to be achieved by the present invention is to group the memory cells according to the threshold voltage distribution of the memory cells, and apply the program voltage in a manner of gradually decreasing with time, by selectively programming a corresponding group according to the level of the program voltage Another aspect of the present invention is to provide a method of programming a nonvolatile memory device, which prevents a rising program voltage from being applied to a group of programmed memory cells to improve electrical characteristics of the memory cell.

According to an embodiment of the present disclosure, a program method of a nonvolatile memory device includes reading a plurality of memory cells and grouping the plurality of memory cells by a threshold voltage distribution, and a group of the first lowest memory cell among threshold voltage distributions. Programming a second memory cell group having a higher threshold voltage distribution than the first memory cell group among the threshold voltage distributions by using a second program voltage, and the threshold value. Programming a third memory cell group having a threshold voltage distribution higher than that of the second memory cell group using a third program voltage, wherein the first program voltage is higher than the second program voltage, The second program voltage is higher than the third program voltage.

In the program operation of the first memory cell group, a program inhibit voltage is applied to bit lines connected to the second memory cell group and the third memory cell group.

In the program operation of the second memory cell group, a program inhibit voltage is applied to bit lines connected to the third memory cell group.

The plurality of memory cells are included in the same page.

A program method of a nonvolatile memory device according to an exemplary embodiment of the present disclosure may include reading a plurality of memory cells and grouping the plurality of memory cells by a threshold voltage distribution, and adjacent memory cells among the grouped plurality of memory cell groups. Selecting groups to form pairs of memory groups, and programming a first memory cell group having the highest threshold voltage distribution of the first memory cell group pair having the lowest threshold voltage distribution among the memory cell group pairs using a first program voltage. And programming a second memory cell group having a lower threshold voltage distribution among the first memory cell group pairs using a second program voltage, and a second having a higher threshold voltage distribution than the first memory cell group pair. The third memory cell group having a high threshold voltage distribution of the memory cell group pairs may use the third program voltage. And a program stage, and wherein the second program by using a program voltage to the fourth memory cell group the pair of low threshold voltage distribution of the fourth memory cell group.

The first program voltage is lower than the second program voltage, and the third program voltage is lower than the fourth program voltage.

The third program voltage is lower than the first program voltage, and the fourth program voltage is lower than the first program voltage.

During the program operation of the first memory cell group pair, a program inhibit voltage is applied to bit lines connected to the second memory cell group pair.

In the program operation of the first memory cell group, a program inhibit voltage is applied to bit lines connected to the second memory cell group and the second memory cell group pair.

After the program operation of the fourth memory cell group, a fifth memory cell group having a higher threshold voltage distribution of a third memory cell group pair having a higher threshold voltage distribution than the second memory cell group pair is programmed using a fifth program voltage. And programming a sixth memory cell group having a low threshold voltage distribution among the third memory cell group pairs using a sixth program voltage.

According to a third aspect of the present disclosure, a program method of a nonvolatile memory device includes applying a first program voltage to a first group of memory cells for programming to a first state, and having a lower threshold voltage distribution than the first state. Applying a second program voltage to the second memory cell group and the first memory cell group for programming to a second state; and a third memory for programming to a third state with a lower threshold voltage distribution than the second state. And applying a third program voltage to the cell group and the second memory cell group, and applying a fourth program voltage to the third memory cell group.

The first program voltage is greater than the second program voltage, the second program voltage is greater than the third program voltage, and the third program voltage is greater than the fourth program voltage.

In the applying of the third program voltage, a program prohibition voltage is applied to a bit line of the first memory cell group.

In the applying of the fourth program voltage, a program prohibition voltage is applied to bit lines of the first memory cell group and the second memory cell group.

According to an embodiment of the present invention, the memory cells are grouped according to the threshold voltage distribution of the memory cells, and the program voltage is applied in a manner of gradually decreasing with time, and the corresponding group is selectively programmed according to the level of the program voltage. As a result, an increasing program voltage may be prevented from being applied to a group of programmed memory cells, thereby improving electrical characteristics of the memory cell.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2 is a circuit diagram illustrating a memory cell array of a general nonvolatile memory device.

Referring to FIG. 2, a nonvolatile memory device may include a drain select transistor DST, a plurality of memory cells MC <0> to MC <31>, and a source select transistor SST connected in series between a bit line and a common source line. It consists of a number of string structures, including). In this case, memory cells sharing the same word line WL may be divided into pages. In general, in a nonvolatile memory device, memory cells of the same page are programmed at the same time.

A first embodiment of the present invention will be described below.

3A is a graph showing threshold voltage distributions of memory cells included in one page before applying a program voltage. According to an exemplary embodiment of the present invention, a program operation of one page sharing a word line WL <0> of the memory cell array shown in FIG. 2 will be described as an example.

Referring to FIG. 3A, before applying the program voltage, memory cells included in one page are read and grouped by threshold voltage distributions. That is, the memory cells of the region A are grouped using the first read voltage read1, the memory cells of the region B are grouped using the second read voltage read2, and the third read voltage read3 is used. Group memory cells of the C region. At this time, the memory cells have similar program rates for each group, because the threshold voltages of the memory cells are distributed according to the program speeds.

3B to 3D are threshold voltage distribution diagrams for describing a program method according to an exemplary embodiment of the present invention.

Referring to FIG. 3B, the first program voltage ① is applied to the word line WL <0> for a predetermined time so that the memory cell group of the lowest region of the threshold voltage distribution, that is, the threshold voltage is distributed in the A region. The cells move the threshold voltage to the D region. The first program voltage ① is the highest program voltage among the program voltages applied during the program operation. In this case, the memory cell groups in which threshold voltages are distributed in the remaining areas, that is, the B and C areas, do not perform a program operation by applying a program inhibit voltage to a bit line.

Referring to FIG. 3C, the second program voltage ② is applied to the word line WL <0> for a predetermined time to move the threshold voltages of the memory cells in which the threshold voltage is distributed in the B region to the D region. The second program voltage ② is a program voltage lower than the first program voltage ① by a predetermined potential. In this case, the memory cell group in which the threshold voltages are distributed in the remaining regions, that is, the C region and the D region, does not apply the program inhibit voltage to the bit line to perform the program operation. Memory cells already programmed and distributed in the D region receive the second program voltage ② through the word line WL <0>, but the second program voltage ② is lower than the first program voltage ①. Therefore, the threshold voltages of the memory cells do not change.

Referring to FIG. 3D, the third program voltage ③ is applied to the word line WL <0> for a predetermined time to move the threshold voltages of the memory cells having the threshold voltage distributed in the C region to the D region. The third program voltage ③ is a program voltage lower than the second program voltage ② by a predetermined potential. In this case, the memory cell group in which the threshold voltage is distributed in the remaining region, that is, the D region, does not perform a program operation by applying a program inhibit voltage to the bit line. At this time, the memory cells already programmed and distributed in the D region are also applied with the third program voltage ③ through the word line WL <0>, but the third program voltage ③ is greater than the second program voltage ②. Since it is low, the threshold voltage does not change.

3E is a graph illustrating a program voltage used in the first embodiment of the present invention.

Referring to FIG. 3E, the program voltage Program Bias is a second program voltage lower than the first program voltage ① after the first program voltage ① is applied for a predetermined time when the initial program voltage is applied. ②) is applied for a predetermined time, and is applied in order of the third program voltage ③ lower than the second program voltage ②. That is, gradually decreasing program voltages are sequentially applied.

According to the first embodiment of the present invention, the memory cells are grouped according to the threshold voltage distribution of the memory cells, and the program voltage is applied in a manner of gradually decreasing with time, but a corresponding group is selectively selected according to the level of the program voltage. Programming prevents the application of high program voltages to the programmed memory cells, thereby improving the electrical characteristics of the memory cells. However, this method requires an operation control for prohibiting program operation for each group during the program operation according to the time due to the operation of reading all the memory cells before applying the program voltage and the threshold voltage distribution.

A second embodiment of the present invention will be described below.

4A is a graph illustrating a program voltage according to another embodiment of the present invention.

4B is a threshold voltage distribution diagram for describing a program operation according to another embodiment of the present invention.

2, 4A, and 4B, before applying a program voltage, memory cells included in one page are read and grouped into a plurality of groups A to F by threshold voltage distributions.

Thereafter, the memory cell groups adjacent to each other in threshold voltage distribution are programmed as a pair.

In more detail, the first program voltage ① is applied to the word line WL <0> for a predetermined time to move the threshold voltage to the G region of the memory cell group belonging to the region B of the threshold voltage distribution. Thereafter, the second program voltage ② is applied to the word line WL <0> for a predetermined time to move the threshold voltage of the memory cell group belonging to the A region adjacent to the B region to the G region. The second program voltage ② is a program voltage higher than the first program voltage ① by a predetermined potential. In this case, the memory cell groups in which the threshold voltages are distributed in the remaining regions, that is, the C to F regions, do not perform a program operation by applying a program inhibit voltage to the bit line.

Thereafter, the third program voltage ③ is applied to the word line WL <0> for a predetermined time to move the threshold voltage to the G region of the memory cell group belonging to the region D of the threshold voltage distribution. The third program voltage ③ is a program voltage lower than the first program voltage ① by a predetermined potential. Thereafter, the fourth program voltage ④ is applied to the word line WL <0> for a predetermined time to move the threshold voltage of the memory cell group belonging to the C region adjacent to the D region to the G region. The fourth program voltage ④ is a program voltage lower than the first program voltage ① and a predetermined potential higher than the third program voltage ③. In this case, the memory cell groups in which the threshold voltages are distributed in the remaining regions, that is, the E and F regions, do not perform a program operation by applying a program inhibit voltage to the bit line.

Thereafter, the fifth program voltage ⑤ is applied to the word line WL <0> for a predetermined time to move the threshold voltage to the G region of the memory cell group belonging to the region F of the threshold voltage distribution. The fifth program voltage ⑤ is a program voltage lower than the third program voltage ③ by a predetermined potential. Thereafter, the sixth program voltage ⑥ is applied to the word line WL <0> for a predetermined time to move the threshold voltage to the G region of the memory cell group belonging to the E region adjacent to the F region. The sixth program voltage ⑥ is a program voltage lower than the third program voltage ③ and higher than the fifth program voltage ⑤ by a predetermined potential.

According to the second embodiment described above, memory cells divided into a plurality of groups are programmed in pairs adjacent to each other according to a threshold voltage distribution, but each group of the same group pair is programmed in a manner in which a program voltage increases, and The other group pairs are programmed in such a way that the program voltage drops. As a result, the program operation time is reduced by programming for each group pair, and each group pair uses a falling program voltage. Therefore, the group pair already programmed does not receive a high program voltage.

A third embodiment of the present invention will be described below.

5A is a graph illustrating threshold voltage distribution of a multi-level cell capable of programming a threshold voltage distribution of an erase cell state into a plurality of threshold voltage distribution regions (A, B, and C), that is, programming multi-bit data. to be.

5B is a graph illustrating a program voltage according to a third embodiment of the present invention.

5C is a graph illustrating an application sequence of a program voltage according to a third embodiment of the present invention.

2 and 5A to 5C, first to third program voltages ① to ③ are used to program the memory cells having the threshold voltage distribution state of the erase state to the A region, and to the B region. In order to program the second to fourth program voltages ② to ④, the third to fifth program voltages ③ to ⑤ are used to program the C region. The fifth to first program voltages ⑤ to ① that are sequentially applied are voltages that sequentially fall.

The fifth fifth program voltage ⑤ is applied to the word line WL <0> for a predetermined time to program memory cells for programming to the C region. At this time, some of the memory cells for programming to the C region are programmed to the C region, and the remaining memory cells are programmed to the C region when the fourth program voltage (④) and the third program voltage (③) are subsequently applied. In addition, the memory cells for programming to the A and B regions while applying the fifth program voltage ⑤ apply a program inhibit voltage to the bit line to prevent the program.

Thereafter, the fourth program voltage ④ is applied to the word line WL <0> for a predetermined time to simultaneously program the memory cells for programming to the C region and the memory cells for programming to the B region. In addition, the memory cells for programming to the A region while applying the fourth program voltage ④ apply a program inhibit voltage to the bit line to prevent the program.

Thereafter, a third program voltage ③ is applied to the word line WL <0> for a predetermined time, memory cells for programming to the C region, memory cells for programming to the B region, and for programming to the A region. Program memory cells at the same time. At this time, the memory cells for programming to the C region are programmed while the fifth and fourth program voltages ⑤ and ④ and the third program voltage ③ applied previously are completed to complete the program operation.

Thereafter, the second program voltage ② is applied to the word line WL <0> for a predetermined time to simultaneously program the memory cells for programming to the B region and the memory cells for programming to the A region. In this case, since the memory cells for programming to the C region are already programmed, a program inhibit voltage is applied to the connected bit line to prevent the program operation. In addition, the memory cells for programming to the B region are programmed while the fourth and third program voltages (4) and (3) and the second program voltage (2) applied above are applied to complete the program operation.

Thereafter, the first program voltage ① is applied to the word line WL <0> for a predetermined time to program memory cells for programming to the A region. In this case, since the memory cells for programming to the C region and the B region are already programmed, a program inhibit voltage is applied to the connected bit line to prevent the program operation. In addition, the memory cells for programming to the A region are programmed while the third and second program voltages ③ and ② and the first program voltage ① applied previously are completed to complete the program operation.

According to the third embodiment described above, a memory cell group that is programmed with different threshold voltage distributions during a program operation of a multi-level cell is simultaneously programmed in a section in which program voltages overlap each other, thereby reducing program time and using the entire program operation. The memory cells programmed by sequentially decreasing the program voltages are prevented from applying high program voltages, thereby improving electrical characteristics of the memory cells.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A is a graph illustrating a program voltage according to an ISPP scheme according to the related art.

1B is a graph illustrating changes in threshold voltages during a program operation using a conventional ISPP scheme.

2 is a circuit diagram illustrating a memory cell array of a general nonvolatile memory device.

3A is a graph showing threshold voltage distributions of memory cells included in one page before applying a program voltage.

3B to 3D are threshold voltage distribution diagrams for describing a program method according to an exemplary embodiment of the present invention.

3E is a graph illustrating a program voltage used in the first embodiment of the present invention.

4A is a graph illustrating a program voltage according to another embodiment of the present invention.

4B is a threshold voltage distribution diagram for describing a program operation according to another embodiment of the present invention.

5A is a graph illustrating threshold voltage distributions of multi-level cells that can program multi-bit data.

5B is a graph illustrating a program voltage according to a third embodiment of the present invention.

5C is a graph illustrating an application sequence of a program voltage according to a third embodiment of the present invention.

Claims (16)

Grouping a plurality of memory cells included in one page by a threshold voltage distribution; Applying a program voltage sequentially descending from a high voltage to a low voltage to a word line of the page; And And controlling and programming the bit lines from the group of memory cells having a low threshold voltage distribution to the high group. The method of claim 1, Program a memory cell group having a low threshold voltage distribution when the high voltage program voltage is applied, and program a memory cell group having a high threshold voltage distribution when the low program voltage is applied. . Reading a plurality of memory cells in a page unit and grouping the plurality of memory cells by threshold voltage distributions; Programming a first group of memory cells having the lowest threshold voltage distribution using a first program voltage; Programming a second memory cell group having a higher threshold voltage distribution than the first memory cell group among the threshold voltage distributions using a second program voltage; And Programming a third memory cell group having a higher threshold voltage distribution than the second memory cell group among the threshold voltage distributions by using a third program voltage; And the first program voltage is higher than the second program voltage and the second program voltage is higher than the third program voltage. The method of claim 3, wherein And a program inhibit voltage is applied to bit lines connected to the second memory cell group and the third memory cell group during a program operation of the first memory cell group. The method of claim 3, wherein And a program inhibit voltage is applied to bit lines connected to the third memory cell group during a program operation of the second memory cell group. The method of claim 3, wherein And the plurality of memory cells are included in the same page. Reading a plurality of memory cells and grouping the plurality of memory cells by threshold voltage distributions; Selecting adjacent memory cell groups among the grouped plurality of memory cell groups to form memory group pairs; Programming the first memory cell group having the highest threshold voltage distribution of the first memory cell group pair among the memory cell group pairs using a first program voltage; Programming a second memory cell group having a low threshold voltage distribution among the first memory cell group pairs using a second program voltage;  Programming a third memory cell group having a higher threshold voltage distribution of a second memory cell group pair than a first memory cell group pair using a third program voltage; And And programming a fourth memory cell group having a low threshold voltage distribution among the pair of second memory cell groups by using a fourth program voltage. The method of claim 7, wherein And the first program voltage is lower than the second program voltage and the third program voltage is lower than the fourth program voltage. The method of claim 7, wherein The third program voltage is lower than the first program voltage, and the fourth program voltage is lower than the first program voltage. The method of claim 7, wherein And a program inhibit voltage is applied to bit lines connected to the second memory cell group pair during a program operation of the first memory cell group pair. The method of claim 7, wherein And a program inhibit voltage is applied to bit lines connected to the second memory cell group and the second memory cell group pair during a program operation of the first memory cell group. The method of claim 7, wherein After the program operation of the fourth memory cell group, Programming a fifth memory cell group having a higher threshold voltage distribution of a third memory cell group pair than a second memory cell group pair using a fifth program voltage; And And programming a sixth memory cell group having a low threshold voltage distribution among the third memory cell group pairs using a sixth program voltage. In program operation of a multi-level cell having multiple program threshold voltage distributions, Applying a first program voltage to a first group of memory cells for programming to a first state; Applying a second program voltage to the second memory cell group and the first memory cell group for programming to a second state having a threshold voltage distribution lower than that of the first state; Applying a third program voltage to the third memory cell group and the second memory cell group for programming to a third state having a threshold voltage distribution lower than that of the second state; And And applying a fourth program voltage to the third memory cell group. The method of claim 13, And the first program voltage is greater than the second program voltage, the second program voltage is greater than the third program voltage, and the third program voltage is greater than the fourth program voltage. The method of claim 13, The applying of the third program voltage may include applying a program prohibition voltage to a bit line of the first memory cell group. The method of claim 13, The applying of the fourth program voltage may include applying a program prohibition voltage to bit lines of the first memory cell group and the second memory cell group.
KR1020090135615A 2009-12-31 2009-12-31 Method of programming a non volatile memory device KR20110078733A (en)

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