KR20110077687A - Semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to prevent the reduction of the size of the exposed areas of the edges of an active area on which a storage node contact plug is formed. CONSTITUTION: A plurality of bit lines(41) crosses a word line(42). A plurality of active areas is inclined around the word line or the bit lines. The active areas, which are located on the same crossing line around any active area, are arranged in a zigzag shape.

Description

Semiconductor memory device and manufacturing method therefor {SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, to a semiconductor memory device capable of increasing a contact area between an active region and a storage node contact plug, and a method of manufacturing the same.

Until now, research on semiconductor memory devices such as DRAM has focused only on scale down of design rules that require the development of lithography technology.

However, this approach leads to problems such as limitations of lithography technology and yield decline as the difficulty of process technology increases. In addition, the semiconductor memory device uses a structure in which one cell area applied from 16M DRAM has 8F ² , which shows a limit to high integration.

In order to overcome this limitation of the 8F ² structure, a structure in which one cell area has 6F ² has recently been proposed. Here, 'F' represents a minimum feature size.

1 is a plan view illustrating a semiconductor memory device having a 6F ² structure according to the prior art.

As shown in FIG. 1, a plurality of active regions 13 defined in a diagonal direction and defined by an element isolation layer 12 formed on the substrate 11 and a word line 22 simultaneously crossing the element isolation layer and the active region. And a plurality of bit lines 21 crossing the word line 22 and a bit line contact plug 20 connecting the center of the active region 13 and the bit line 21. Although not shown in the drawings, storage node contact plugs connecting the storage node of the capacitor and the active region 13 are formed at both edges of the active region 13 (see reference numeral 'X').

However, the semiconductor memory device having the 6F ² structure of the related art having the above-described structure has a form in which the active regions 13 positioned on the same diagonal line are arranged in a line with respect to any one of the active regions 13. As a result, as the degree of integration of the semiconductor memory device increases, the exposed area of the active region 13 in which the storage node contact plug is to be formed is preformed by the word line 22 and the bit line 21. The problem arises that the contact area between the node contact plugs is gradually reduced. That is, a problem arises in that the contact resistance between the active region 13 and the storage node contact plug increases.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and has a semiconductor memory device capable of increasing the contact area between an active region and a storage node contact plug in a semiconductor memory device having a 6F ² structure and a manufacturing method thereof. The purpose is to provide.

According to one aspect of the present invention, a semiconductor memory device includes a plurality of word lines; A plurality of bit lines intersecting the word lines; And a plurality of active regions disposed in an oblique direction inclined at a predetermined angle with respect to the word line or the bit line, and the active regions positioned in the same diagonal line with respect to any one of the active regions are arranged in a zigzag pattern. It is characterized by.

In addition, a bit line contact plug connecting the center of the active region and the bit line; And a storage node contact plug connecting the active area edge and the storage node.

Two word lines and one bit line may cross one active area, and the word line may include a buried gate.

According to an aspect of the present invention, a method of manufacturing a semiconductor memory device according to an aspect of the present invention defines a plurality of active regions disposed in an oblique direction by forming an isolation layer on a substrate, the same diagonal line based on any one of the active regions. Forming the device isolation layer such that the active regions positioned in the zigzag are disposed in a zigzag manner; Forming a plurality of word lines crossing the device isolation layer and the active region at the same time; And forming a plurality of bit lines that intersect the word lines.

The method may further include forming a bit line contact plug connecting the bit line and a central portion of the active region before forming the bit line; And forming a storage node contact plug connected to an edge of the active region after forming the bit line.

The forming of the device isolation layer defining the active region may include forming a hard mask pattern extending diagonally on the substrate and having a stepped shape; Selectively etching the curved portions of the hard mask patterns; Forming a trench by etching the substrate using the hard mask pattern as an etch barrier; Forming an isolation layer filling the trench; And removing the hard mask pattern.

Here, the forming of the hard mask pattern having the step shape may include forming a sacrificial pattern extending diagonally on the substrate and having a step shape; And forming hard mask patterns on both sidewalls of the sacrificial pattern. In this case, the hard mask pattern may be formed by an SPT process.

One of the active regions may be formed such that the two word lines and one bit line cross each other, and the word line may include a buried gate.

According to the above-described problem solving means, the semiconductor memory device of the present invention has a word line that is pre-formed even if the degree of integration of the semiconductor memory device is increased as the active regions located in the same diagonal line are arranged in a zigzag form based on any one of the active regions. And reducing the exposed area of the edge of the active region where the storage node contact plug is to be formed by the bit line.

Through this, it is possible to increase the contact area between the storage node contact plug and the active region, and to reduce the contact resistance therebetween.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention to be described later provides a semiconductor memory device capable of increasing a contact area between an active region and a storage node contact plug in a semiconductor memory device having a 6F ² structure and a method of manufacturing the same. To this end, in the present invention, a plurality of active regions are disposed in an oblique direction inclined at an angle with respect to a word line or a bit line, and the active regions located on the same diagonal line with respect to any one of the active regions are zigzag. Placement is a technical point.

2 is a plan view illustrating a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 2, a semiconductor memory device according to an exemplary embodiment of the present invention may include a plurality of word lines 42, a plurality of bit lines 41 and word lines 42 that intersect the word lines 42, or It includes a plurality of active areas 33 arranged in an oblique direction inclined by a predetermined angle with respect to the bit line 41, the active areas 33 located on the same diagonal line with respect to any one active area 33 ) Is arranged in a zigzag.

Further, the semiconductor device may further include a bit line contact plug 40 connecting the bit line 41 and the active region 33 and a storage node contact plug connecting the storage node and the active region 33, although not shown in the drawing. Can be. In this case, the bit line contact plug 40 may be located at the center of the active region 33, and the storage node contact plug may be located at the edge of the active region.

A semiconductor memory device according to an embodiment of the present invention may have a 6F ² structure in which two word lines 42 and one bit line 41 cross one active region 33. In this case, the word line 42 fills a trench (not shown) formed in the substrate 31, a gate insulating film (not shown) formed on the trench surface, a gate electrode (not shown) partially filling the trench on the gate insulating film, and the remaining trenches. It may be a buried gate (BG) structure consisting of a sealing film.

The semiconductor memory device having the above-described structure has a structure in which the active regions 33 positioned on the same diagonal line with respect to one active region 33 are arranged in a zigzag form. Compared to the structure in which the active regions 33 positioned in the same diagonal line are arranged in a line with respect to any one of the active regions 33 in the related art, the edge of the active region 33 in which the storage node contact plug is to be formed (reference numeral 'X'). It can be prevented that the exposed area of ') gradually decreases as the degree of integration of the semiconductor memory device increases.

That is, according to the present invention, since the active regions 33 positioned on the same diagonal line with respect to any one of the active regions 33 are arranged in a zigzag form, the word lines 42 and the preformed word lines 42 may be formed even if the degree of integration of the semiconductor memory device is increased. The bit line 41 may prevent the exposed area of the edge of the active region 33 in which the storage node contact plug is to be formed from being reduced, thereby increasing the contact area therebetween. Therefore, the contact resistance between them can also be reduced.

Hereinafter, a method of manufacturing a semiconductor memory device having a structure shown in FIG. 2 will be described in detail in the method of manufacturing a semiconductor memory device according to an embodiment of the present invention. Typically, to form active regions according to an embodiment of the present invention, an active region mask having a structure in which active regions located in the same diagonal line are arranged in a zigzag form based on one active region is used. To form. However, due to the diffraction limit of the photolithography process, the semiconductor memory device according to an embodiment of the present invention may be formed by only an active region mask defining an active region zigzagly arranged in an oblique direction as the degree of integration of the semiconductor memory device increases. There is a limit to the implementation. Therefore, in the method of manufacturing a semiconductor memory device according to an embodiment of the present invention described below, an embodiment of the present invention uses SPT (Spacer Patterning Technology) technology in response to the limitation of the photolithography process and the increase in the degree of integration of the semiconductor memory device. A manufacturing method for implementing a semiconductor memory device according to the present invention will be described.

3A to 3G are process plan views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, a sacrificial pattern 43 extending in a diagonal direction inclined at an angle with respect to a word line or a bit line to be formed through a subsequent process is formed on the substrate 31. In this case, the sacrificial pattern 43 may have a step shape. Specifically, the sacrificial pattern 43 is composed of a connection pattern 43B connecting the line pattern 43A and the line pattern 43A, and the line width W2 of the connection pattern 43B is two line patterns 43A. It is equal to the sum of the line widths (W1) of (W2 = W1 + W1). That is, the sacrificial pattern 43 has a stepped shape in which the line pattern connected to one side and the line pattern 43A connected to one side and the line pattern 43A connected to the other side are not positioned on the same diagonal line based on the connection pattern 43B.

The sacrificial pattern 43 may be formed of a carbon-containing film, for example, an amorphous carbon layer (ACL), which can be easily removed during subsequent processes.

As shown in FIG. 3B, a hard mask pattern 44 having a spacer shape is formed on both sidewalls of the sacrificial pattern 43 using the SPT technique. In this case, the hard mask pattern 44 may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are stacked.

For example, in the case where the hard mask pattern 44 is formed of a nitride film, after the nitride film is deposited along the surface of the structure including the sacrificial pattern 43, the top surface of the sacrificial pattern 43 is exposed. The hard mask pattern 44 may be formed through a series of process of performing etchback. In this case, the line width W3 of the hard mask pattern 44 may be adjusted in consideration of the line width in the uniaxial direction of the active region to be formed through the subsequent process. This may be implemented by controlling the deposition thickness of the insulating film deposited to form the hard mask pattern 44.

As shown in FIG. 3C, the sacrificial pattern 43 is removed. For example, a sacrificial pattern 43 by using the case of forming an amorphous carbon film by an oxygen plasma treatment on (O ₂ plasma treatment), a so-called ashing (ashing) process may remove the sacrificial pattern 43. Through this, the hard mask pattern 44 having a step shape may be formed.

As shown in FIG. 3D, the curved portion of the hard mask pattern 44 having the step shape is selectively etched. At this time, by selectively etching the bent portion of the hard mask pattern 44 extending in the diagonal direction to form the discontinuously arranged hard mask pattern 44, the hard mask pattern 44 in consideration of the long axis line width of the active region. ) Is preferably etched. Hereinafter, the reference numeral of the etched hard mask pattern 44 is changed to '44A' and described. As a result, the hard mask patterns 44A positioned on the same diagonal line with respect to any one of the hard mask patterns 44A may be arranged in a zigzag form.

As shown in FIG. 3E, the substrate 31 is etched using the hard mask pattern 44A as an etch barrier to form a trench (not shown), and then the trench is filled with an insulating material to form an isolation layer 32. ). Subsequently, the hard mask pattern 44A is removed.

Here, as the device isolation layer 32 is formed, a plurality of active regions 33 may be defined, and the active regions 33 are zigzag with active regions positioned on the same diagonal line based on any one of the active regions 33. It has a structure arranged in the form.

Next, a plurality of word lines 42 are formed on the substrate 31 to cross the active region 33 and the device isolation layer 32 at the same time. In this case, the word line 42 may be formed to cross two word lines 42 in one active region 33 and may have a buried gate structure. For reference, a word line 42 having a buried gate structure may form a gate insulating film (not shown) on the trench surface after forming a trench (not shown) in the substrate 31, and then partially filling the trench on the gate insulating film. The gate electrode may be formed through a series of processes in which a sealing film (not shown) is deposited on the entire surface of the substrate 31 to fill the remaining trenches on the gate electrode and the gate electrode.

As shown in FIG. 3F, an interlayer insulating film (not shown) is formed on the entire surface of the substrate 31 to cover the word line 42, and then penetrates the interlayer insulating film between the word lines 42 to form the active region 33. A bit line contact plug 40 in contact with the center is formed.

As shown in FIG. 3G, a plurality of bit lines 41 are formed on the interlayer insulating film to intersect the word line 42 and contact the bit line contact plug 40. In this case, the bit line 41 may be formed such that one bit line 41 crosses one active region 33.

Subsequently, although not shown in the drawings, an interlayer insulating layer covering the bit line is formed, and a storage node contact plug connected to the edge of the active region 33 is formed through the interlayer insulating layer, and then the storage node is formed on the storage node contact plug. do.

In the semiconductor memory device of the present invention formed through the above-described process, any one of the active regions 33 positioned on the same diagonal line with respect to any one of the conventional active regions 33 is arranged in one line. As the active regions 33 positioned on the same diagonal line with respect to the region 33 are arranged in a zigzag form, the exposed area of the edge of the active region 33 where the storage node contact plug is to be formed is integrated. It can be prevented from gradually decreasing as it increases. That is, according to the present invention, the active regions 33 positioned on the same diagonal line with respect to any one of the active regions 33 are formed to be arranged in a zigzag form, so that the word lines 42 that have been formed even though the degree of integration of the semiconductor memory device increases. ) And the bit line 41 may prevent the exposed area of the edge of the active region 33 in which the storage node contact plug is to be formed from being reduced, thereby increasing the contact area therebetween. Therefore, the contact resistance between them can also be reduced.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a plan view showing a semiconductor memory device having a 6F ² structure according to the prior art.

2 is a plan view illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

3A to 3G are process plan views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32 device isolation film

33: active area 40: bit line contact hole

41: bit line 42: word line

43: sacrificial pattern 43A: line pattern

43B: connection pattern 44, 44A: hard mask pattern

Claims (11)

A plurality of word lines; A plurality of bit lines intersecting the word lines; And A plurality of active regions disposed in an oblique direction inclined by a predetermined angle with respect to the word line or the bit line, A semiconductor memory device in which the active regions located in the same diagonal line with respect to any one of the active regions are arranged in a zigzag. The method of claim 1, A bit line contact plug connecting the center of the active region and the bit line; And A storage node contact plug that connects the edge of the active region and the storage node. The semiconductor memory device further comprising. The method of claim 1, 2. The semiconductor memory device of claim 2, wherein the word line and the bit line cross one active region. The method of claim 1, And the word line includes a buried gate. Forming a device isolation film on a substrate to define a plurality of active areas arranged in an oblique direction, and forming the device isolation film so that the active areas located in the same diagonal line are arranged in a zigzag with respect to any one of the active areas; Forming a plurality of word lines crossing the device isolation layer and the active region at the same time; And Forming a plurality of bit lines intersecting the word line A semiconductor memory device manufacturing method comprising a. The method of claim 5, Forming a bit line contact plug connecting the bit line and a central portion of the active region before forming the bit line; And Forming a storage node contact plug connected to an edge of the active region after forming the bit line; The semiconductor memory device manufacturing method further comprising. The method of claim 5, Forming the device isolation layer defining the active region, Forming a hard mask pattern extending diagonally on the substrate and having a step shape; Selectively etching the curved portions of the hard mask patterns; Forming a trench by etching the substrate using the hard mask pattern as an etch barrier; Forming an isolation layer filling the trench; And Removing the hard mask pattern A semiconductor memory device manufacturing method comprising a. The method of claim 7, wherein Forming the hard mask pattern having a step shape, Forming a sacrificial pattern extending diagonally on the substrate and having a step shape; And Forming a hard mask pattern on both sidewalls of the sacrificial pattern A semiconductor memory device manufacturing method comprising a. The method of claim 8, The hard mask pattern is formed by the SPT process. The method of claim 5, And forming one active region so that two word lines and one bit line cross each other. The method of claim 5, The word line includes a buried gate.

Images