KR20110077540A - Semiconductor device, and fabricating method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to enable random access of a unit bit and highly dense storage capacity. CONSTITUTION: A trench(20) has a square shape. The trench includes an inclined wall. The trench is formed on a semiconductor substrate(10). An ion implantation layer and a multilayer film are successively formed on the wall of the trench. A control gate is formed in the trench. First to fourth source/drain areas are formed on the semiconductor substrate exposed to four corners of the trench. Contacts are formed on the first to fourth source/drain areas respectively. A contact is formed on the control gate.

Description

Semiconductor device and fabrication method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a semiconductor device having a high density memory device structure and a manufacturing method thereof.

Non-volatile semiconductor memory began with magnetic core memory and came to the present form as it came to EEPROM (electrically erasable and programmable read only memory). Flash memory is the most representative of the EEPROMs currently used, and is rapidly increasing in demand due to the recent expansion of digital cameras and mobile phones.

As the demand for flash memory grows, competition for storing large amounts of data in the same area of semiconductor is also heating up.

Until recently, it has been common to store one bit (two state) of information in one memory cell, but MLC (multi level cell) technology has emerged as an effort to store a large amount of information in a given area.

The most typical MLC technique is to control the amount of charge stored in the floating gate to create several intermediate levels, which can store two bits of information in a cell.

The other MLC method is called a mirror bit method and is a technology capable of storing two bits of data.

Among high density memory products based on MLC technology, random access (NOR type) products have drain contacts. In the case of NOR-type products, the source uses a self-aligned source (SAS), and in the drain, two transistors share the same contact.

In the case of a NAND type memory, contacts for source and drain do not exist in each transistor. Therefore, it can be implemented as a high density memory. However, NAND memory cannot perform bit base program / erase / read operation due to random access, and has a disadvantage in that it is slow.

Disclosure of Invention An object of the present invention has been made in view of the above points, and in particular, a semiconductor device capable of realizing a high density storage capability possible in a NAND type memory structure as well as random access of unit bits possible in a NOR type memory structure, and a method of manufacturing the same. To provide.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can implement bits corresponding to a plurality of cells by applying a new cell structure to a region corresponding to a unit cell.

A feature of the semiconductor device according to the present invention for achieving the above object is a rectangular trench having a wall surface inclined to the semiconductor substrate; A gate pattern including a channel ion implantation layer on the first to fourth walls of the trench, a tunneling oxide film, a trap nitride film, a blocking oxide film, and a control gate in the center of the trench; First to fourth source / drain regions on a semiconductor substrate corresponding to a vertex of the gate pattern; And first to fifth contacts connected to the first to fourth source / drain regions and the control gate, respectively.

A feature of the method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a rectangular trench having an inclined wall surface on the semiconductor substrate; Sequentially forming an ion implantation layer and a multilayer film on the wall surface of the trench; Forming a control gate in the trench formed up to the multilayer film; Forming first to fourth source / drain regions on the exposed semiconductor substrate corresponding to the four vertex portions of the trench; And forming a contact on the control gate while forming a contact on the first to fourth source / drain regions, respectively.

In the present invention, while using a cell structure that can implement four bits in the area corresponding to the unit cell, and also using a silicon-oxide-nitride-oxide-silicon (SONOS) structure, random access of unit bits as well as high-density storage Ability to be realized

In addition, when using one of the MLC mirror bit (mirror bit) or when using another MLC can be extended from 8 to 32 bits.

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a configuration and an operation of an embodiment of the present invention will be described with reference to the accompanying drawings, and the configuration and operation of the present invention shown in and described by the drawings will be described as at least one embodiment, The technical idea of the present invention and its essential structure and action are not limited.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of a semiconductor device and a method for manufacturing the same in detail.

The semiconductor device described below is preferably a flash memory device, and basically uses a SONOS structure.

1A to 1F are cross-sectional views illustrating a manufacturing process of a semiconductor memory device according to the present invention.

As shown in FIG. 1A, an active region is defined in the semiconductor substrate 10. For example, the semiconductor substrate 10 may be a silicon substrate, and the active region may be defined by forming a plurality of device isolation layers (not shown) on the semiconductor substrate 10.

The trench 20 for the SONOS structure is formed in the active region corresponding to the unit cell region.

2A is a perspective view illustrating an example in which a trench is formed in a unit cell region, and FIG. 2B is a cross-sectional view of FIG. 2A.

In particular, the trench 20 is preferably formed in the shape of a square or a square at the center of the defined active region, the trench 20 having an inclined wall surface. Most preferably, since the four walls of the trench 20 should have the same memory characteristics, the trench 20 is formed in a trapezoidal column shape in which the cross section is square and the cross section decreases toward the inside of the semiconductor substrate.

Subsequently, as shown in FIG. 1B, the ion implantation layer 30 and the ONO (oxide-nitrice-oxide) films 40 to 60 are sequentially formed on the wall surface of the trench 20.

In detail, first, the ion implantation layer 30 is formed by implanting impurity ions into the semiconductor substrate 10 including the trench 20. At this time, the ion implantation uses a tilt ion implantation. The ion implantation layer 30 is formed on the inner wall of the trench 20 as well as on the upper surface of the semiconductor substrate 10 around the trench 20. Here, a portion of the ion implantation layer 30 formed on the inner wall surfaces of the trench 20 becomes a channel layer 30a later, and a portion formed on the upper surface of the semiconductor substrate 10 around the trench 20 is removed later. do.

After the ion implantation layer 30 is formed, the first oxide film 40 for tunneling, the nitride nitride film 50 for charge storage, and the second oxide film 60 for blocking are sequentially inside the trench 20. Form on the walls.

The first oxide film 40 may be formed through oxidation of the inner walls of the trench 20, and the nitride film 50 may be formed by depositing silicon nitride (SiN) on the first oxide film 40. The second oxide layer 60 may be formed by depositing a silicon-based oxide layer on the nitride layer 60.

As shown in FIG. 1B, the AA ′ cross-section of FIG. 1B is illustrated in the state in which the ion implantation layer 30 and the multilayer oxide-nitrice-oxide (ONO) films 40 to 60 are sequentially formed on the wall surface of the trench 20 as described above. to be.

Subsequently, as shown in FIG. 1C, the gate poly is formed on the entire surface of the semiconductor substrate 10 including the trench 20 on which the ion implantation layer 30 and the oxide-nitrice-oxide (ONO) films 40 to 60 are formed. Silicon 70 is deposited. As a result, the gate polysilicon 70 is embedded in the trench 20. 4 is a perspective view showing after the gate polysilicon 70 is deposited.

Subsequently, as shown in FIG. 1D, the gate polysilicon 70 is patterned for the control gate to form a control gate pattern 70a corresponding to the formation region of the trench 20.

That is, after the photoresist pattern 80 is formed on the gate polysilicon 70, the gate polysilicon 70 around the trench 20 is removed using the photoresist pattern as a mask. Here, the patterned control gate pattern 70a is present only in the region of the trench 20 in which the ion implantation layer 30 and the oxide-nitrice-oxide (ONO) films 40 to 60 are formed and on the upper portion thereof, and thus photoresist. The pattern is formed only on the portion where the gate polysilicon 70 is embedded in the trench 20. Thereafter, the photoresist pattern is removed.

On the other hand, as a further step, a portion of the semiconductor substrate 10 corresponding to the edge of the active region corresponding to the unit cell region is etched to form a semiconductor substrate 10a having a step S. Here, the process of forming the semiconductor substrate 10a having the step may be performed after the CMP described later.

After the control gate pattern 70a is formed, a planarization process for removing the control gate pattern 70a to BB ′ of FIG. 1D is performed. That is, the planarization process of exposing the surface of the semiconductor substrate 10a around the trench 20 is performed.

Here, the planarization process uses CMP (chemical mechanical polishing), and the photoresist pattern may be removed together during the CMP.

As the planarization process is completed, the channel layer 30a, the tunneling oxide film 40a, the trap nitride film 50a, and the trapezoidal film 50a are sequentially formed in the inverted trapezoidal trench 20 as shown in FIG. 1E. A blocking oxide film 60a is formed, and a control gate 70b is formed in the center. 5 is a top view plan view illustrating the planarization process after the process.

Through the processes of FIGS. 1A to 1E, a gate trapezoidal gate pattern is formed in the trench 20.

1F, impurity ions are implanted into the exposed semiconductor substrate 10a corresponding to four vertex portions of the gate pattern to form source / drain regions 80 and 81. Subsequently, the first to fourth contacts 90 and 91 are formed on the four regions of the source / drain regions 80 and 81, and the fifth contact 92 is formed on the control gate 70b.

Here, the source / drain regions 80 and 81 and the first to fourth contacts 90 and 91 are not located in the longitudinal section corresponding to FIG. 1F and should be understood by FIG. 7. That is, FIG. 1F corresponds to a longitudinal cross-sectional view of F-F 'of FIG. 7.

Meanwhile, FIG. 6A shows the portion “D” in FIG. 1F, and FIG. 6B shows the cross section of E-E ′ in FIG. 1F.

FIG. 6A is a three-dimensional view showing one direction among inverted trapezoidal gate patterns, and the channel layer 30a is provided on the wall surface of the trench 20 in the horizontal direction of the control gate 70b, and both sides of the channel layer 30a. Thus, the first to second source / drain regions 81a and 81b and the first to second contacts 91a and 91b connected to the first to second source / drain regions 81a and 81b are formed at two vertices of the gate pattern. It is provided.

Current flows through the channel layer 30a between the first and second source / drain regions 81a and 81b, and the horizontal direction of the channel layer 30a is a current flow path (CP). Therefore, the horizontal direction of the channel layer 30a corresponds to the channel length (CH length), and the vertical direction of the channel layer 30a corresponds to the channel width (CH width). Here, the channel length corresponds to the length of one side of the control gate 70b, and the channel width corresponds to the depth of the control gate 70b. That is, the thickness of the gate polysilicon 70 embedded in the trench 20 corresponds to the channel width.

FIG. 6B illustrates a layer structure of one surface of an inverted trapezoidal gate pattern, which is composed of a semiconductor substrate 10a, a channel layer 30a, an ONO 40a, 50a, 60a and a control gate 70b from the outside.

7 is a top view plan view illustrating a structure of a semiconductor memory device according to the present invention. The gate pattern formed in the present invention is an inverted trapezoidal shape but is described in plan in FIG.

As shown in FIG. 7, the semiconductor memory device according to the present invention includes a square control gate 70b at the center of the active region, and a blocking oxide film and a trap nitride film in turn on four peripheral sides of the control gate 70b. An ONO film 400 including a tunneling oxide film is provided, and channel layers 300 to 330 are provided immediately outside the ONO film 400 to form a square gate pattern implementing four cells.

Source / drain regions 81a, 81b, 80a, and 80b are provided at vertices of the gate pattern, respectively, and are connected to four first to fourth source / drain regions 81a, 81b, 80a, and 80b. To fourth contacts 91a, 91b, 90a, and 90b, and a fifth contact 92 connected to the control gate 70b.

Meanwhile, one side of the square gate pattern operates as one unit cell, and accordingly, the semiconductor memory device according to the present invention operates as four cells. For example, in the case of using the mirror bit structure, since four cells can be stored in a total of 8 bits.

The control gate 70b is biased by the fifth contact 92.

In the case of the first cell, the first contact 91a and the second contact 91b are used as the source terminal and the drain terminal.

In the case of a second cell, the second contact 91b and the third contact 90a are used as the source terminal and the drain terminal.

In the case of a third cell, the third contact 90a and the fourth contact 90b are used as the source terminal and the drain terminal.

In the case of the fourth cell, the fourth contact 90b and the first contact 91a are used as the source terminal and the drain terminal.

In the case of using the mirror bit structure, the positions of the source terminal and the drain terminal may be changed.

8A is a perspective view illustrating a contact structure of a semiconductor memory device according to the present invention, and FIG. 8B is a perspective view illustrating a metal line structure coupled to the contact structure of FIG. 8A.

In the present invention, the contacts 91a, 91b, 90a, 90b, and 92 are formed at different heights in order to reduce the load of the metal line and configure the cell array. And, unlike the conventional use of only one bit line, the bit line is divided into two.

Of the first to fourth contacts 91a, 91b, 90a, and 90b, the second contact 91b and the fourth contact 90b have the same height, so that the two metal lines M1 for the bit line are respectively contacted with the second contact. 91b and the fourth contact 90b.

Of the first to fourth contacts 91a, 91b, 90a, and 90b, the first contact 91a and the third contact 90a have the same height, so that the two metal lines M2 for the word line are respectively contacted with the first contact. 91a and the third contact 90a. Here, the first and third contacts 91a and 90a have different heights from the second and fourth contacts 91b and 90b.

The fifth contact 92 having a height different from that of the first to fourth contacts 91a, 91b, 90a, and 90b is connected to the other metal line M3 for biasing.

While the preferred embodiments of the present invention have been described so far, those skilled in the art may implement the present invention in a modified form without departing from the essential characteristics of the present invention.

It is therefore to be understood that the embodiments of the invention described herein are to be considered in all respects as illustrative and not restrictive, and the scope of the invention is indicated by the appended claims rather than by the foregoing description, Should be interpreted as being included in.

1A to 1F are cross-sectional views illustrating a manufacturing process of a semiconductor memory device according to the present invention.

2A is a perspective view illustrating an example in which trenches are formed in a unit cell region, and FIG. 2B is a cross-sectional view of FIG. 2A.

Figure 3 is a cross-sectional view showing the AA 'cross-section of Figure 1b.

4 is a perspective view showing after the gate polysilicon is deposited.

Figure 5 is a top view plan view after the planarization process.

FIG. 6A is a three-dimensional view showing a portion “D” of FIG. 1F, and FIG. 6B is a cross-sectional view showing a cross section taken along the line E-E ′ of FIG. 1F.

7 is a top view plan view showing the structure of a semiconductor memory device according to the present invention.

8A is a perspective view illustrating a contact structure of a semiconductor memory device according to the present invention.

8B is a perspective view illustrating a metal line structure that couples with the contact structure of FIG. 8A.

Claims (10)

Forming a rectangular trench having an inclined wall surface in the semiconductor substrate; Sequentially forming an ion implantation layer and a multilayer film on the wall surface of the trench; Forming a control gate in the trench formed up to the multilayer film; Forming first to fourth source / drain regions on the exposed semiconductor substrate corresponding to the four vertex portions of the trench; Forming a contact on the control gate while forming a contact on the first to fourth source / drain regions, respectively. The method of claim 1, wherein the trench is formed in the center of an active region of a unit cell, and is formed in an inverted trapezoidal column shape whose cross-sectional area decreases from the center to the inside of the semiconductor substrate. The method of claim 1, wherein the step of sequentially forming the ion implantation layer and the multilayer film, Implanting impurity ions into the inner wall of the trench as well as the upper surface of the semiconductor substrate around the trench to form the ion implantation layer for the channel; Forming a first oxide film for tunneling on the ion implantation layer on the inner wall of the trench; Forming a nitride film for traps on the first oxide film for charge storage; And forming a second oxide film for blocking on the nitride film. The method of claim 1, wherein the forming of the control gate pattern comprises: Depositing a gate polysilicon on an entire surface of the semiconductor substrate including the trench formed up to the multilayer film; Patterning the gate polysilicon to form a control gate pattern corresponding to a formation position of the trench; Removing the control gator pattern until the surface of the semiconductor substrate around the trench is exposed so that the control gate is formed in the trench. A rectangular trench having an inclined wall surface on the semiconductor substrate; A gate pattern including a channel ion implantation layer on the first to fourth walls of the trench, a tunneling oxide film, a trap nitride film, a blocking oxide film, and a control gate in the center of the trench; First to fourth source / drain regions on a semiconductor substrate corresponding to a vertex of the gate pattern; And first to fifth contacts connected to the first to fourth source / drain regions and the control gate, respectively. The semiconductor device of claim 5, wherein the trench is disposed at the center of the active region of the unit cell, and the first to fourth wall surfaces have an inverted trapezoidal shape that decreases in cross section toward the inside of the semiconductor substrate. The method of claim 6, wherein the gate pattern, And an inverted trapezoidal column shape in which the cross-sectional area decreases from the surface of the semiconductor substrate to the inside of the inverted trapezoidal trench. The method of claim 5, wherein the fifth contact among the first to fifth contacts is a biasing contact connected to the control gate, and the first to fourth contacts are respectively connected to the first to fourth source / drain regions. A semiconductor device comprising a contact for drain or drain. The method of claim 5, The first channel ion implantation layer, the first tunneling oxide film, the first trap nitride film, and the first blocking oxide film provided on the first wall surface of the trench form a first cell together with the common control gate. A second channel ion implantation layer, a second tunneling oxide film, a second trap nitride film, and a second blocking oxide film formed on the second wall surface of the trench form a second cell together with the common control gate. The third channel ion implantation layer, the third tunneling oxide film, the third trap nitride film, and the third blocking oxide film formed on the third wall surface of the trench form a third cell with the common control gate. The fourth channel ion implantation layer, the fourth tunneling oxide film, the fourth trap nitride film, and the fourth blocking oxide film formed on the fourth wall of the trench form a fourth cell with the common control gate. Semiconductor device. The method of claim 9, Among the first to fifth contacts, the first contact is a source terminal of the first cell, the second contact is a drain terminal of the first cell, The second contact is a source terminal of the second cell, the third contact is a drain terminal of the second cell, The third contact is a source terminal of the third cell, the fourth contact is a drain terminal of the third cell, And the fourth contact is a source terminal of the fourth cell, and the first contact is a drain terminal of the fourth cell.

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