KR20110075333A - Flash memory apparatus and solid state storage system using the same - Google Patents

Abstract

PURPOSE: A flash memory apparatus and a solid state storage system using the same are provided to control the threshold voltage of a flash memory cell by a desired level to enable a cell to be normally operated when trap charge increases due to the increase of a cycling time. CONSTITUTION: In a flash memory apparatus and a solid state storage system using the same, a flash memory(130) comprises a plurality of memory blocks A temperature compensation stage(140) heats and cools down the flash memory. The temperature compensation stage comprises a temperature controller(142) and a temperature control device(144) A temperature controller drives the temperature control device which heats or cools down the flash memory.

Description

Flash memory device and semiconductor storage system using the same {Flash Memory Apparatus and Solid State Storage System Using the Same}

The present invention relates to a semiconductor device, and more particularly to a flash memory device and a semiconductor storage system using the same.

Flash memory is a type of nonvolatile memory. This has the advantages of RAM, which is easy to write / delete data, and ROM, which preserves data even after the power supply is cut off. It has the characteristics of small size, light weight, high speed and low power consumption. .

Flash memory is generally capable of changing the stored data from 1 to 0, but not from 0 to 1. Therefore, the data in the storage area is erased before programming new data. Is changed to 1 (erase-before-write).

In the flash memory, an erase process is performed in units of blocks, and each block is no longer erased after a predetermined number of times, for example, 100,000 times. As such, the erase count for each block of the flash memory serves as a factor for determining the life of the flash memory. Therefore, the erase operation should be performed equally for each block to extend the life of the flash memory as much as possible.FTL (Flash) is used to prevent program dynamic concentration on a specific block by allocating an empty area or a small number of erased blocks during data programming. Translation Layer) algorithm is used.

However, as the number of erase-program cycling increases, electrons are trapped in the tunnel insulating layer, and the threshold voltage is changed, which causes a malfunction of the flash memory device. In addition, even if the FTL algorithm is applied, as the erase and program operations are repeated, the lifetime of the flash memory is bound to reach its limit.

On the other hand, when the flash memory erases all the memory cells of a particular sector at the same time, an over erase phenomenon may occur in which a threshold voltage of some flash memory cells is lower than a specified level. As the threshold voltage is shifted as described above, the corresponding cell and other cells sharing the wiring may malfunction, and thus, the reliability of the flash memory device may not be guaranteed.

On the other hand, recently, SSD (Solid State Drive) using NAND flash memory has been released in place of HDD (Hard Disk Drive) in PC (Personal Computer), and it is expected to rapidly invade HDD market.

Therefore, in order to fully function as such a storage system, it is necessary to secure the life of the flash memory and the operation reliability to the maximum.

The present invention provides a flash memory device capable of increasing the number of rewrites and a semiconductor storage system using the same.

Another object of the present invention is to provide a flash memory device capable of adjusting a threshold voltage of a flash memory through temperature control and a semiconductor storage system using the same.

A flash memory device according to an embodiment of the present invention for achieving the technical problem of the present invention comprises a flash memory including a plurality of memory blocks consisting of a plurality of memory cells; And a temperature compensator which is driven according to preset conditions to heat or cool the flash memory.

On the other hand, a semiconductor storage system according to an embodiment of the present invention includes a flash memory area including a plurality of memory blocks consisting of a plurality of memory cells; A memory controller for providing a program, erase, or read command to the memory area, and performing file and directory management, address mapping, and wear-leveling for the memory area; And a temperature compensator for heating or cooling the memory cell when a preset condition is satisfied by referring to management information of the memory controller for the memory area.

According to an embodiment of the present invention, the threshold voltage can be controlled to a desired level by heating or cooling the flash memory cell. Therefore, even when the number of cycling increases and the trap electron amount increases or in the case of an over-erased cell, the threshold voltage level may be readjusted to operate as a normal cell.

As a result, it is possible to extend the life of the flash memory device or the semiconductor storage system using the same, as well as to improve operational reliability during use.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a block diagram of a flash memory device according to an embodiment of the present invention.

As shown, the flash memory device 10 according to an embodiment of the present invention is a flash memory 130 including a plurality of memory blocks, data in the flash memory 130 in response to a request transmitted from an application as a user program The temperature compensation unit 140 for adjusting the threshold voltages of the controller 110, the driver 120 performing physical access to the flash memory 130, and the memory cells constituting the flash memory 130 to perform the operation. It includes.

Here, the control unit 110 includes a file system 112 and a software translation layer (FTL) 114.

The file system 112 performs functions such as file and directory management in order to provide a user with a more efficient storage environment.

The FTL 114 allows the flash memory 130 to be used as a virtual block device, and performs the address mapping function. That is, the logical address delivered from the application is changed to the physical address used by the flash memory 130.

In addition, the FTL 114 performs a wear-leveling function. Since the flash memory 130 cannot over-write the data, it is necessary to erase the previous data before performing the write operation. If the erase operation is performed more than the designated number of times, the block is no longer available. There is a problem. Therefore, the erase operation must be uniformly performed for each block to extend the life of the flash memory as much as possible, and wear-leveling is possible. The FTL 114 manages the erase count for each block, so that the data stored in the block having a large erase operation is replaced with the non-operating operation so that the flash memory can fully function as a disk.

The temperature compensator 140 includes a temperature controller 142 and a temperature control element 144. The temperature controller 142 may generate an operation error for a predetermined number of times or when the erase-program cycle for a specific block of the flash memory 130 satisfies the specified number of times, or when the flash memory cell is over-erased. The temperature control element 144 is driven when the threshold voltages of the flash memory cells of a specified number or more are changed by a specified level or higher and need to be readjusted. Accordingly, the temperature control element 144 heats or cools the flash memory cells.

The temperature for heating or cooling the flash memory cells can vary depending on the heating or cooling purpose and the changed threshold voltage level. By heating or cooling each cell by the temperature control element 144, the threshold voltage level can be adjusted to a desired level, thereby increasing the lifespan of the flash memory device 10 as well as ensuring operational reliability.

The configuration of the temperature compensator 140 illustrated in FIG. 1 will be described below with reference to FIG. 2.

FIG. 2 is a configuration diagram illustrating the temperature compensator shown in FIG. 1.

First, the temperature controller 142 includes a comparison circuit 1421, a driving circuit 1423, and a temperature detection circuit 1425. On the other hand, the temperature control element 144 is configured to include a sensor (1441), and may include at least one of the heating element (1443) or the cooling element (1445).

The comparison circuit 1421 of the temperature controller 142 determines whether it is necessary to adjust the threshold voltage of the flash memory 130 in association with the controller 110. When the threshold voltage needs to be adjusted, as described above, when the preset period arrives, or when the erase-program cycle for a specific block of the flash memory 130 satisfies a specified number of times, or when the flash memory cell is over-erased. , Error occurs more than a specified number of times, and various other causes may exist.

The driving circuit 1423 drives the corresponding device when heating or cooling of the flash memory 130 is required as a result of the determination of the comparison circuit 1421, and stops driving of the corresponding device when heating or cooling is performed to a predetermined temperature. That is, when heating is required, the heat generating element 1443 is driven, and when cooling is required, the cooling element 1445 is driven.

When the temperature of the heat generating element 1443 or the cooling element 1445 converges the temperature of the heat generating element 1443 or the cooling element to a predetermined temperature, the temperature detection circuit 1425 may notify the driving circuit 1423 of the heat generating element 1443 or the cooling element 1445. ) Is stopped.

In an embodiment of the present invention, the heating element 1443 may be configured as a thin film heater, but is not limited thereto.

On the other hand, the temperature control element 144 includes at least one of the heat generating element (1443) or the cooling element (1445). In addition, the sensor 1442 of the temperature control element 144 senses the temperature of the heat generating element 1443 or the cooling element 1445 driven by the driving circuit 1423 and transmits the temperature to the temperature detection circuit 1425. Accordingly, the temperature detection circuit 1425 determines whether the driving of the heat generating element 1443 or the cooling element 1445 is stopped.

As described above, in the present invention, the threshold voltage is compensated by heating or cooling each cell constituting the flash memory 130. Therefore, even when the erase-program cycling count reaches its peak, the threshold voltage can be adjusted to the original level, thereby increasing the life of the flash memory.

In addition, it is possible to compensate the threshold voltage for the over-erased cell, thereby preventing the over-erased cell and its neighboring cells from malfunctioning.

3 is a configuration diagram of a semiconductor storage system according to an embodiment of the present invention.

As illustrated, the semiconductor storage system 20 may include a host interface 210, a buffer unit 220, a micro control unit 230, a memory controller 240, a memory region 250, and a temperature compensation unit. 260.

The host interface 210 is connected to the buffer unit 220 to relay control commands, address signals, and data signals between an external host (not shown) and the buffer unit 220. The interface method between the host interface 210 and an external host (not shown) may be any one of serial serial technology attachment (SATA), parallel parallel advanced technology attachment (ATA), and SCSI, Express Card, and PCI-Express methods. Of course, it is also possible to apply other interface methods.

The buffer unit 220 buffers output signals from the host interface 210 or temporarily stores mapping information between logical addresses and physical addresses, block allocation information of a memory area, and data received from the outside. In one embodiment of the present invention, the buffer unit 220 may be configured using a static random access memory (SRAM).

Meanwhile, the MCU 230 is connected to the buffer unit 220, and is connected between the host interface 210 and the memory controller 240. In addition, the host controller 210 may transmit and receive a control command, an address signal, a data signal, and the like, or control the memory controller 240 based on the signals.

The memory controller 240 selects a predetermined NAND flash memory device among the plurality of NAND flash memory devices of the memory area 250 and provides a program, erase, or read command. In particular, the memory controller 240 according to an embodiment of the present invention may be the controller 110 shown in FIG. 1. Therefore, file and directory management functions, address mapping functions, wear-leveling functions, and the like are performed.

The memory area 250 is controlled by the memory controller 240 to perform program, erase, and read operations of data. In this case, the memory area 250 may be configured as a flash memory, in particular, a NAND flash memory. In one embodiment of the present invention, each cell of the NAND flash memory may be a single level cell (SLC) or a multi level cell (MLC). The memory area 150 may be provided with a plurality of chips including a plurality of blocks including a plurality of pages.

The temperature compensator 260 includes a temperature controller 262 and a temperature control element 264. The temperature controller 262 refers to the memory controller 240 to operate the temperature control element 264 when a preset condition for heating or cooling of the flash memory cell is satisfied, thereby configuring the flash area 250. Heat or cool the memory.

Here, the specified condition may be a case where the threshold voltages of the flash memory cells of the specified number or more are changed by a specified level or more and need to be readjusted. More specifically, the predetermined condition or the memory area 250 may be configured. And when the erase-program cycle for the memory block satisfies the specified number of times, or when the flash memory cell is over-erased, an operation error occurs more than the designated number of times.

In addition, the temperature of heating or cooling the temperature control element 264 may vary according to the heating or cooling purpose and the changed threshold voltage level.

Each of the temperature controller 262 and the temperature control element 264 of the temperature compensator 260 illustrated in FIG. 3 may be configured as shown in FIG. 2, for example.

As described above, in the present exemplary embodiment, the level of the threshold voltage can be adjusted to a desired level by heating or cooling the flash memory cell constituting the memory area 250 by the temperature compensator 262. Thus, the semiconductor storage system 20 ) Can increase the service life and improve the operation reliability.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a flash memory device according to an embodiment of the present invention;

2 is a configuration diagram of a temperature compensator shown in FIG. 1;

3 is a configuration diagram of a semiconductor storage system according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: flash memory device 110: control unit

120: driver 130: flash memory

140, 260: temperature compensation unit 20: semiconductor storage system

Claims (13)

A flash memory including a plurality of memory blocks consisting of a plurality of memory cells; And A temperature compensator which is driven according to a preset condition to heat or cool the flash memory; Flash memory device comprising a. The method of claim 1, The temperature compensator includes a temperature controller and a temperature control element, And the temperature control unit drives the temperature control element when the preset condition is satisfied, and the temperature control element is driven by the temperature control unit to heat or cool the flash memory. The method of claim 2, The temperature control unit may include a comparison circuit that determines whether the preset condition is satisfied; A driving circuit for operating the temperature control element in accordance with a determination result of the comparison circuit; And A temperature detection circuit for causing the driving circuit to stop the operation of the temperature control element as the temperature of the temperature control element driven by the drive circuit converges to a specified temperature; Flash memory device comprising a. The method of claim 2, The temperature control element, at least one of a heating element or a cooling element; And A sensor for sensing a temperature of the heating element or the cooling element and transmitting the detection result to the temperature controller; Flash memory device comprising a. The method according to claim 1 or 2, The preset condition is a case where a threshold voltage of the flash memory cells of a specified number or more is changed by a predetermined level or more. The method according to claim 1 or 2, The preset condition may include at least one of a specified period, or a number of erase-program cycles for the memory block, whether the flash memory cell is over-erased, and a number of operating errors of the flash memory. . The method according to claim 1 or 2, The heating or cooling temperature of the temperature compensator is variable according to the heating or cooling purpose for the flash memory cell. A flash memory area including a plurality of memory blocks consisting of a plurality of memory cells; A memory controller for providing a program, erase, or read command to the memory area, and performing file and directory management, address mapping, and wear-leveling for the memory area; And A temperature compensator configured to heat or cool the memory cell by referring to management information of the memory controller for the memory area when a preset condition is satisfied; Semiconductor storage system comprising a. The method of claim 8, The temperature compensator includes a temperature controller and a temperature control element, The temperature control unit may include a comparison circuit that determines whether the preset condition is satisfied; A driving circuit for operating the temperature control element in accordance with a determination result of the comparison circuit; And A temperature detection circuit for causing the driving circuit to stop the operation of the temperature control element as the temperature of the temperature control element driven by the drive circuit converges to a specified temperature; Semiconductor storage system comprising a. The method of claim 9, The temperature control element, at least one of a heating element or a cooling element; And A sensor for sensing a temperature of the heating element or the cooling element and transmitting the detection result to the temperature controller; Semiconductor storage system comprising a. The method of claim 8, The predetermined condition is a case where the threshold voltage of the memory cell of the specified number or more is changed by a predetermined level or more. The method of claim 8, The predetermined condition may include at least one of a predetermined cycle or a number of erase-program cycles for a specific memory block, whether the memory cell is over-erased, or the number of operating errors in the flash memory area. . The method of claim 8, The heating or cooling temperature of the temperature compensation unit is variable according to the heating or cooling purpose for the memory cell.

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