KR20110071291A - Thermoelectric module using superlattice structure - Google Patents

Abstract

PURPOSE: A thermoelectric device a super lattice structure is provided to dry-etch the entire insulation film without forming a photo resist pattern, thereby forming upper and lower electrodes through one time lithography process. CONSTITUTION: A first insulation layer(120) and a second insulation layer(130a) are formed on a substrate(110). An n-type electrode(140n) and a p-type electrode(140p) are separated on the first insulation layer. A lower electrode(140) is formed on the second insulation layer. Super lattice structures(150n,150p) are formed on the n-type electrode and the p-type electrode respectively. A common electrode(170) is formed on the super lattice structures.

Description

Thermoelectric module using superlattice structure

The present invention relates to a thermoelectric element, and more particularly to a thermoelectric element using a superlattice.

The present invention is derived from a study conducted as part of the IT source technology development project of the Ministry of Knowledge Economy [Task management number: 2008-F-035-02, Title: Development of element technology for commercial quantum cryptography communication system].

Thermoelectric element is a device that converts thermal energy into electrical energy, and can use heat sources of various scales from small heat sources such as body heat of the human body to large heat sources such as nuclear power, and are used in almost all energy conversion devices to improve efficiency. There is an advantage that can be improved.

On the other hand, as the size of the semiconductor device decreases, the heat density generated per unit area is gradually increasing, which deteriorates the characteristics of the device, thereby inhibiting the scaling down characteristics of the device. Therefore, the thermoelectric cooling device which is integrated with the semiconductor device and can emit heat generated from the semiconductor device to the outside also has a great advantage as a device using a thermoelectric method.

Thermoelectric performance of heat to electricity or electricity to heat is generally expressed as a figure of merit ZT value and is expressed as Equation 1 below.

Where S is the Seebeck coefficient, σ is the electrical conductivity, T is the average temperature, and K is the thermal conductivity.

In the conventional thermoelectric device, there is a difficulty in optimizing the ZT value by combining the variables shown in Equation 1.

However, the use of superlattice structures allows the Seebeck coefficient and electrical conductivity to be increased due to the special state density functions in the superlattice structure, and doping can also optimize electrical conductivity. In addition, due to the characteristics of the superlattice structure, it is difficult to transfer phonons due to the difference in the medium, thereby lowering the thermal conductivity and increasing the efficiency by reducing the cross-sectional area of the superlattice structure.

Recently, many thermoelectric performances of two-dimensional superlattice structures have been reported, and methods using synthesized superlattice nanowires have been studied. The performance of a superlattice thermoelectric element is further improved when its cross-sectional area is reduced to nanoscale. However, the conventional method using superlattice nanowire growth is not easy to control the thickness, length and density of nanowires. There is this.

Therefore, there is a need for a technique capable of improving thermoelectric performance by forming a superlattice structure in a simple manner.

It is therefore an object of the present invention to provide a method of manufacturing a thermoelectric element using a superlattice by a simple method.

In addition, another object of the present invention is to provide a thermoelectric element with greatly improved thermoelectric performance.

Other objects to be provided by the present invention can be understood by the following description and embodiments of the present invention.

To this end, the thermoelectric device using a superlattice according to an embodiment of the present invention, n-type electrode and p-type electrode formed spaced apart from each other on the substrate; At least one n-type leg formed on the n-type electrode and the p-type electrode in a semiconductor superlattice structure, respectively, wherein the stacked structure of the first material and the second material is repeated at least once; One p-type leg; And a common electrode formed on the n-type leg and the p-type leg.

According to the present invention as described above, there is an advantage to provide a thermoelectric element with a greatly improved thermoelectric efficiency, there is an advantage that can form a superlattice structure in a simple way, and the silicon process is easy, There is an advantage to provide a thermoelectric element that can be integrated into a substrate.

On the other hand, various other effects will be disclosed directly or implicitly in the detailed description of the embodiments of the present invention to be described later.

In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users and operators. Therefore, the definition should be made based on the contents throughout the specification.

As described above, the thermoelectric device has a disadvantage in that it is difficult to increase performance because variables related to the figure of merit ZT, that is, Seebeck coefficient, electrical conductivity and thermal conductivity, are associated with each other.

Accordingly, in order to solve the above problems, the present invention provides a thermoelectric device having a superlattice structure having improved thermoelectric performance expressed by a figure of merit ZT value using characteristics of the superlattice structure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a thermoelectric device according to an embodiment of the present invention.

Referring to FIG. 1, a thermoelectric device according to an exemplary embodiment may include a first insulating layer 120, a second insulating layer 130a, an n-type electrode 140n, and p− formed on a substrate 110. Superlattice structures 150n and 150p formed on a type electrode 140p, a lower electrode 140, the n-type electrode 140n and a p-type electrode 140p, and an insulating film 160 surrounding the superlattice structure, respectively. ) And a common electrode 170 which is an upper electrode formed on the superlattice structures 150n and 150p.

As the substrate 110, an SOI substrate having an insulating layer (BOX) may be used, and a substrate in which an oxide film is formed by subjecting a general bulk silicon substrate to an oxidation process may be used. In the drawings, an SOI substrate is illustrated, and for convenience of description, an embodiment of the present invention uses an SOI substrate as an example. On the other hand, to distinguish from the other insulating layer formed on the thermoelectric element according to an embodiment of the present invention, the insulating layer formed on the SOI substrate is referred to as a first insulating layer 120 hereinafter.

The n-type electrode 140n and the p-type electrode 140p are formed to be spaced apart from each other on the first insulating layer 120. The n-type electrode 140n and the p-type electrode 140p may be formed by ion implanting the n-type dopant and the p-type dopant into the silicon layer, which is the uppermost layer of the SOI substrate, respectively. Alternatively, n-type doped silicon or n-type doped poly silicon and p-type doped silicon (p-) may be formed on the first insulating layer 120. Type doped silicon or p-type doped poly silicon may be formed by deposition.

Superlattice structures 150n and 150p are formed on the n-type electrode 140n and the p-type electrode 140p, respectively. The superlattice structures 150n and 150p include a repeat stack structure of Si / SiGe, a repeat stack structure of Si _X Ge _{1 -X} / Si _Y Ge _1-Y , or a repeat stack structure of PbTe / Pb _{1 - X} Eu _X Te. do. Alternatively, the structure may include a PbSeTe / PbTe superlattice quantum dot or a nanoparticle.

Silicon buffer layers 151n and 151p are formed on the lowermost layers of the superlattice structures 150n and 150p, that is, the portions adjacent to the n-type electrode 140n and the p-type electrode 140p. The silicon buffer layers 151n and 151p prevent lattice mismatch with the underlying structure upon growth of the superlattice structures 150n and 150p. In addition, the silicon buffer layers 151n and 151p buffer the stress due to different thermal expansion rates of the lower structure and the superlattice structure 150n and 150p formed under the superlattice structures 150n and 150p.

On the other hand, the n-type doped silicon layer 159n and the p-type doped silicon layer 159p are formed on the uppermost layers of the superlattice structures 150n and 150p, that is, the portions adjacent to the common electrode 170. .

The insulating layer 160 surrounding the superlattice structures 150n and 150p is formed on the n-type electrode 140n and the p-type electrode 140p. The insulating layer 160 may be formed by an LP-TEOS method or a porous SiO ₂ formation method. The superlattice structures 150n and 150p are cut off from the outside by the insulating layer 160 except for the doped silicon layers 159n and 159p formed on the uppermost layer. The insulating layer 160 serves to prevent leakage of current flowing from the common electrode 170 to the n-type electrode 140n and the p-type electrode 140p. Also, the heat generated from the heat sink side is superlattice structure. It serves to prevent divergence to the sides of (150n, 150p). The insulating layer 160 may include SiO ₂ , air, and a vacuum.

Meanwhile, some of the n-type electrode 140n and the p-type electrode 140p are exposed to the outside.

The n-type electrode 140n and the p-type electrode 140p exposed to the outside are connected to the lower electrode 140, respectively, and have a superlattice structure on the insulating layer 160 surrounding the superlattice structures 150n and 150p. A common electrode 170 is formed, which is an upper electrode conducting with the doped silicon layers 159n and 159p, which are the top layers of 150n and 150p.

Hereinafter, a manufacturing process of a thermoelectric device using a superlattice according to an embodiment of the present invention as described above will be described with reference to related drawings.

2 is a view for explaining a method of manufacturing a thermoelectric device according to an embodiment of the present invention.

First, as shown in FIG. 2A, a substrate is prepared. As the substrate, a silicon on insulator (SOI) substrate may be used, or the bulk silicon substrate may be subjected to an oxidation process. In the drawing, the SOI substrate 100 having the structure of the bulk silicon layer 110, the first insulating layer 120, and the silicon layer 130 is illustrated. Hereinafter, in describing a method of manufacturing a thermoelectric device using a superlattice according to an embodiment of the present invention, an SOI substrate is used as an example.

On the other hand, when the bulk silicon substrate is used in an oxidation process, it is preferable to form a thin oxide film for heat dissipation to the silicon substrate, and the back surface of the substrate may be etched to form a heat sink.

When the substrate is prepared, n-type electrodes and p-type electrodes are formed on the substrate. An ion implantation method may be used to form the n-type electrode and the p-type electrode, and the process thereof is as follows.

First, as shown in FIG. 2B, a photoresist pattern 131 for forming an n-type doped region 140n ′ is formed in the silicon layer 130 of the SOI substrate. Thereafter, as shown in FIG. 2C, the n-type doped region 140n ′ is formed by implanting the n-type dopant through an ion implantation process.

Thereafter, as shown in FIG. 2D, the photoresist pattern 131 used to form the n-type doped region 140n 'is removed, and the formation of the p-type doped region 140p' is performed. The photoresist pattern 132 is formed. Thereafter, as shown in FIG. 2E, the p-type dopant is formed by implanting the p-type dopant through an ion implantation process.

Thereafter, when the photoresist pattern 132 used to form the p-type doped region 140p 'is removed, a structure as shown in FIG. 2F is completed.

Then, in order to form the n-type electrode and the p-type electrode, as shown in (g) of FIG. 2, the photo on the n-type doped region 140n 'and the p-type doped region 140p'. After the resist pattern 133 is formed, an etching process is performed to remove the silicon layer 130, thereby forming the n-type electrode 140n and the p-type electrode 140p as shown in FIG. Complete the final structure.

In the above description, the n-type electrode 140n is first formed and then the p-type electrode 140p is formed as an example. However, the n-type electrode 140n may not be formed after the p-type electrode 140p is formed. It may be. Also, instead of using an ion implantation process, n-type doped silicon or n-type doped poly silicon and p-type doped silicon (p) on the oxide layer It is also possible to use a method of depositing -type doped silicon or p-type doped poly silicon.

Thereafter, as shown in FIG. 2 (i), the second insulating layer 130a is formed using a thermal oxidation method or a low pressure-tetra ethyl ortho silicate (LP-TEOS) method. The second insulating layer 130a may be formed of a silicon oxide (SiO _X ) layer or a silicon nitride (Si ₃ N ₄ ) layer. After forming the second insulating layer 130a, a planarization process for planarizing the surface of the structure is performed. In this case, a chemical mechanical polishing (CMP) process may be used to planarize the structure.

As described above, when the structure having the planarization of the surface is completed, a step for forming a superlattice structure is then performed. A process for forming the superlattice structure will be described as follows.

First, as shown in (j) of FIG. 2, a superlattice structure 150n 'for forming an n-type leg on the planarized structure is formed. The superlattice structure 150n 'may be formed of a repetitive lamination structure of Si / SiGe, a repetitive lamination structure of Si _X Ge _{1 -X} / Si _Y Ge _{1 -Y} , or a repetitive lamination structure of PbTe / Pb _{1 - X} Eu _X Te. Alternatively, the present invention may be formed of a repeating laminated structure containing PbSeTe / PbTe superlattice quantum dots or nanoparticles.

At this time, the lowermost layer of the superlattice structure 150n 'is formed of a silicon buffer layer 151, and the uppermost layer is formed of an n-type doped silicon layer 159n.

The superlattice structure is preferably formed in one or more multiple periods to suppress the flow of phonons in a wide range of energy bands. At this time, the side closer to the heat source is formed in a form capable of suppressing high frequency phonons, and the side closer to the heat sink is capable of suppressing low frequency phonons. It is desirable to form in a form that can be.

For example, in the case of forming the superlattice structure 150n 'with a repeated stack structure of Si / SiGe to form n-type leg 150n, the thickness of the SiGe layer serving as a barrier is thin and uniform. In the holding state, the thickness of the Si layer becomes thinner toward the side closer to the heat source, that is, toward the common electrode 170, and the thickness of the Si layer becomes closer toward the side closer to the heat sink, that is, toward the n-type electrode 140n. It is preferable to form so that it may be able to suppress the flow of a high frequency phonon and a low frequency phonon.

On the contrary, in the case where the superlattice structure 150p 'is formed by the repeated lamination structure of Si / SiGe to form the p-type leg 150p, the thickness of the Si layer serving as a barrier is kept thin and constant. To form a thinner SiGe layer toward the common electrode 170, the SiGe layer becomes thicker toward the p-type electrode 140p so as to suppress the flow of the high frequency phonon and the low frequency phonon. desirable.

In forming the superlattice structure, Molecular Beam Epitaxy (MBE) or Chemical Vapor Deposition (CVD) may be used.

On the other hand, in the superlattice structure, the electrical conductivity in the quantum well should be improved, so that the delta (δ) -doping or modulation doping method is applied to the middle part of the barrier of the quantum well so as not to disturb the flow of electrons and holes. Doping is preferred.

For example, the Si / SiGe superlattice structure for the formation of n-type leg is doped with Phosphotous, Antimony and Arsenic on SiGe, and the Si / SiGe superlattice structure for the formation of p-type leg is boron, Dopants such as gallium and aluminum.

Subsequently, as shown in FIG. 2 (k), an etch mask pattern 161 is formed, and an etching process is performed to remove the superlattice structure formed on the p-type doped region. To form a structure as shown. In this case, the etching mask pattern 161 may be SiO ₂ , Si ₃ N _4, or Si ₃ N ₄ SiO ₂ , which may be used as a photoresist or an etching mask. Substances, such as these, can be used.

Thereafter, as shown in FIG. 2 (m), a superlattice structure 150p 'for forming a p-type leg is formed. Super lattice structure (150p ') is repeated in the Si / SiGe layered structure, Si _X Ge _{1 -X} / Si _1-Y Ge _Y repeated laminate structure or PbTe / Pb of _{1 -} growing a repeating stack structure of Eu _{X X} Te by It may be formed, or may be formed in a repeating laminated structure including PbSeTe / PbTe superlattice quantum dots and nanoparticles. At this time, the lowermost layer of the superlattice structure 150p 'is formed of a silicon buffer layer 151p, and the uppermost layer is formed of a p-type doped silicon layer 159p.

Subsequently, as shown in FIG. 2 (n), a photoresist pattern 162 is formed and an etching process is performed to form a superlattice formed on the n-type doped silicon layer 159n on the n-type doped region. The structure is removed to form a structure as shown in FIG. Thereafter, the remaining photoresist pattern 162 is removed. In this case, after removing the photoresist pattern 162, the surface planarization process may be performed using a CMP process or the like.

Subsequently, as shown in FIG. 2 (p), the photoresist pattern 171 or the E-beam resist pattern 171 for forming the n-type leg and the p-type leg is formed and then etched. The process proceeds to form the final structures of n-type leg 150n and p-type leg 150p as shown in FIG.

Thereafter, as shown in (r) of FIG. 2, an insulating film 160 covering the structure formed in the step is formed. The insulating layer 160 may be formed by an LP-TEOS method or a porous SiO ₂ formation method.

When the structure as described above is completed, a process for forming an electrode for connection with the outside in a later step is carried out. A process for forming an electrode is as follows.

First, as shown in (s) of FIG. 2, the photoresist pattern 181 is formed on the structure on which the insulating film 160 is formed, and an etching process is performed to form the n-type electrode 140n and the p-type electrode ( 140p) to the outside.

Thereafter, as shown in (t) of FIG. 2, the lower electrode 140 is formed by depositing a metal, and a lift-off process is performed to complete the structure as shown in (u) of FIG. 2.

Thereafter, to form the upper electrode, a photoresist pattern 182 is formed as shown in FIG. Thereafter, after etching the insulating layer 160 on the n-type leg and the p-type leg, the upper electrode 170 is formed as shown in FIG. Complete the final structure as shown in (x).

Meanwhile, in the step for forming the lower electrode 140 and the upper electrode 170, the lower electrode 140 and the upper electrode 170 are dry-etched by dry etching the insulating film 160 as a whole without forming the photoresist pattern 181. After removing the insulating layer 160 to be formed, the lower electrode 140 and the upper electrode 170 may be formed through a single lithography process.

While the above has been shown and described with respect to preferred embodiments of the invention, the invention is not limited to the specific embodiments described above, it is usually in the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or prospect of the present invention.

1 is a view showing a thermoelectric device according to an embodiment of the present invention;

2 is a view for explaining a method of manufacturing a thermoelectric device according to an embodiment of the present invention.

Claims (1)

An n-type electrode and a p-type electrode formed spaced apart from each other on the substrate; At least one n-type leg formed on the n-type electrode and the p-type electrode in a semiconductor superlattice structure, respectively, wherein the stacked structure of the first material and the second material is repeated at least once; One p-type leg; And A common electrode formed on the n-type leg and the p-type leg Thermoelectric element using a superlattice comprising a.

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