KR20110070577A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to secure a valid surface of a log signal by informing an output direction of a gate signal. CONSTITUTION: A liquid crystal display device includes as follows. A liquid crystal display panel distinguishes into a display area and a non display area. A first and a second gate driving unit provide a gate signal with a plurality of gate line. A printed circuit board provides a driving signal and a driving voltage to the first and second gate driving unit and a data driving unit. A first and second log signal line group(150,150b) provides the driving signal and a driving voltage to the first and second gate driving unit.

Description

Liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can secure line width margin of a LOG signal line and improve reliability of a gate driver by eliminating signal lines that determine a gate output direction.

Recently, the liquid crystal display device is manufactured in a small and medium size, and is used in a GPS system that enables navigation services to aircraft, ships, and passenger cars, and devices made to enjoy multimedia while carrying images, music, and videos.

Such a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal display panel in which liquid crystal cells are arranged in a matrix by adjusting light transmittance of liquid crystal cells according to a video signal. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and a driving circuit for driving the liquid crystal display panel.

The driving circuit unit includes a gate driver supplying a scan signal to a gate line of the liquid crystal display panel, and a data driver supplying a data signal to a data line of the liquid crystal display panel. In this case, the data driver and the gate driver are integrated into a plurality of integrated circuit chips.

Each integrated data drive IC chip and gate drive IC chip are mounted on a tape carrier package (TCP) and connected to a liquid crystal display panel by a tape automated bonding (TAB) method and a TFT array substrate. There is a chip on glass (COG) method that directly mounts the drive IC chip.

Recently, in order to further reduce the size of the liquid crystal display by minimizing the size of the PCB, signal lines connected to the drive IC chips are being formed on a glass substrate in a line on glass (LOG) manner. By mounting the signal lines connected to the drive IC chips on the thin film transistor array substrate in the LOG method, the printed circuit board may be removed and the liquid crystal display panel may be further thinned.

In particular, since signal lines connected to gate drive ICs requiring relatively few signal lines are formed on the thin film transistor array substrate in a LOG method, a method of removing a gate printed circuit board is widely used.

In the LOG method in which the gate printed circuit board is removed, the gate drive ICs drive and control signals from a timing controller and a power supply mounted on the data printed circuit board through LOG signal lines formed on the thin film transistor array substrate. The voltages are supplied.

The LOG signal lines are formed on a non-display area of the liquid crystal display panel, and the LOG signal lines are formed using a mask process similarly to a plurality of gate lines and data lines formed on the liquid crystal display panel.

In this case, the LOG signal lines supplied with the control signals and the driving voltages from the data printed circuit board to the gate drive IC formed on the thin film transistor array substrate are formed to fit the limited area of the non-display area, so that the line thickness is increased. It is difficult to secure enough. In particular, since the LOG signal line further includes a DIR signal line for determining the gate output direction in the left / right direction of the liquid crystal display panel, it is difficult to sufficiently secure the LOG signal line margin.

As a result, distortion of a plurality of control signals and driving voltages supplied to the gate drive IC through the LOG signal line may result in deterioration of display quality of the liquid crystal display panel.

The present invention removes the DIR LOG signal line that determines the left / right gate output direction of the liquid crystal display panel, and uses the power supply voltage (Vcc) and ground (GND) voltage pads among the gate pads located on the left and right sides of the liquid crystal display panel. It is an object of the present invention to provide a liquid crystal display that can secure the effective area of a LOG signal line by informing the output direction of a gate signal.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a liquid crystal display panel in which a plurality of gate lines and data lines are arranged, and is divided into a display area and a non-display area, and are positioned on the left and right sides of the non-display area. First and second gate drivers for providing a gate signal to the substrate, a printed circuit board for providing a driving signal and a driving voltage to the first and second gate drivers and the data driver, and a non-display area of the liquid crystal display panel. And first and second LOG signal line groups configured to provide the driving signal and the driving voltage to the first and second gate drivers, respectively, and the first LOG signal line group. The second gate driver is connected to a first gate pad part and the second LOG signal line group positioned on a left side of the non-display area of the panel, and the second gate driver is a non-table of the liquid crystal display panel. Including a second portion of the gate pad on the right side of the area, and the first and second gate pads, respectively, the part comprising the first and second direction to set the gate signal output direction of the second gate driver set pad.

The liquid crystal display according to the present invention determines the gate output direction by determining the output direction of the gate signal by using the power supply voltage Vcc and ground GND voltage pads among the gate pads positioned on the left and right sides of the liquid crystal display panel. The effective area of the LOG signal line can be secured by removing the DIR LOG signal line.

In addition, the LCD according to the present invention can reduce the resistance of the LOG signal line by reducing the LOG signal line to minimize the malfunction of the gate driver to improve the reliability of the product.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other, and a liquid crystal cell Clc is disposed at an intersection thereof. A liquid crystal display panel 100 having a thin film transistor TFT for driving a light source, a gate driver 110 for supplying a scan signal to the gate lines GL1 to GLn, and a data line DL1 to DLm. A common voltage is supplied to a data driver 120 for supplying data, a timing controller 130 for controlling the gate driver 110 and the data driver 120, and a common electrode of the liquid crystal display panel 100. The common voltage generator 140 is included.

The liquid crystal display panel 100 has a liquid crystal formed between two glass substrates, and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersect each other on the lower glass substrate. . The thin film transistor TFT formed at the intersection of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm is in response to a scan signal from the gate lines GL1 to GLn. The data from DLm is supplied to the liquid crystal cell Clc.

To this end, the gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, and the source electrode is connected to the data lines DL1 to DLm. The drain electrode of the thin film transistor TFT is connected to the pixel electrode of the liquid crystal cell Clc.

In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line, or may be formed between the liquid crystal cell Clc and a separate common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to each pixel area in which the thin film transistors TFT are formed, and the gate lines GL1 to GLn border each other. And a black matrix covering the data lines DL1 to DLm, the thin film transistor TFT, and the like, and a common electrode covering all of them.

The gate driver 110 supplies a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 130. These multiple scan signals cause the multiple gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronization signal. The gate driver 110 may include a plurality of gate driver integrated circuits.

The data driver 120 generates a plurality of pixel data voltages whenever any one of the gate lines GL1 to GLn is enabled in response to the data control signals DCS from the timing controller 130. And a plurality of data lines DL1 to DLm on the liquid crystal display panel 100. The data driver 120 may include a plurality of data driver integrated circuits.

The timing controller 130 may enable data synchronization and synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown). The gate control signal GCS for controlling the gate driver 110 and the data control signal DCCS for controlling the data driver 120 are generated using the signal DE and the clock signal CLK.

In addition, the timing controller 130 arranges the image data Data input from an external system and supplies the sorted data to the data driver 120.

The common voltage generator 140 generates the common voltage Vcom using the power voltage Vdd supplied from the power supply unit and supplies the common voltage Vcom to the common electrode of the liquid crystal display panel 100. .

In this case, the timing controller 130 and the common voltage generator 140 may be disposed together with the power supply unit on a data printed circuit board (not shown) on which the data driver 120 is mounted.

FIG. 2 is a schematic view of the liquid crystal display panel of FIG. 1.

As shown in FIGS. 1 and 2, the liquid crystal display panel 100 includes a color filter substrate 101, a thin film transistor array substrate 103, and a liquid crystal layer formed between two substrates.

In the thin film transistor array substrate 103, the gate lines arranged to be spaced apart in the lateral direction and the data lines arranged to be spaced apart in the longitudinal direction intersect with each other, and the gate lines intersected with the pixels are divided into the data lines. Is defined. The pixels are arranged on the thin film transistor array substrate 103 in a matrix form.

In addition, first and second gate pad portions 115a and 115b connected to the gate driver 110 of FIG. 1 are disposed in the non-display area of the thin film transistor array substrate 103. . The first gate pad part 115a is connected to the gate driver 110 of FIG. 1 located on the left side of the non-display area, and the second gate pad part 115b is located on the right side of the non-display area. It is connected to the driving unit 110.

In this case, the gate drivers 110 positioned on the left and right sides of the liquid crystal display panel 100 should output gate signals in different directions.

In the non-display area of the thin film transistor array substrate 103, a data pad part 125 connected to a data driver (120 of FIG. 1) for driving the plurality of data lines is positioned.

The color filter substrate 101 has red, green, and blue color filters formed at positions corresponding to the pixels, and has a black matrix to prevent color interference of light passing through the color filters. And a common electrode for applying an electric field to the liquid crystal layer together with the pixel electrode of the thin film transistor array substrate 103.

A pixel electrode and a common electrode are provided on an inner surface of the thin film transistor array substrate 103 and the color filter substrate 101 to drive the liquid crystal molecules of the liquid crystal layer by a voltage difference between the pixel electrode and the common electrode. The luminance of the image displayed on the liquid crystal display panel 100 changes according to the size of the image information applied to the pixels.

First and second LOG signal line groups 150 and 160 are formed in the non-display area of the thin film transistor array substrate 103. The first LOG signal line group 150 is positioned on the left non-display area of the thin film transistor array substrate 103, and the second LOG signal line group 160 is not displayed on the right side of the thin film transistor array substrate 103. Located in the area.

The first LOG signal line group 150 is electrically connected to the first gate pad unit 115a, and the second LOG signal line group 160 is electrically connected to the second gate pad unit 115b. .

The first and second signal line groups 150 and 160 may control various control signals and driving voltages from a timing controller (130 of FIG. 1) or a power supply (not shown), respectively. Is provided by the gate driver connected to the

FIG. 3 is an enlarged view of region A of FIG. 2.

As shown in FIGS. 2 and 3, the first LOG signal line group 150 includes first to eighth LOG signal lines 150a to 150h. The first to eighth LOG signal lines 150a to 150h extend from the data pad part 125 of FIG. 2.

The first LOG signal line 150a is a signal line to which the gate low voltage VGL provided from the data pad unit 125 is applied, and the second LOG signal line 150b is a signal to which a ground GND voltage is applied. The third LOG signal line 150c is a signal line to which a power supply voltage Vcc is applied.

The fourth LOG signal line 150d is a signal line to which a gate output enable (GOE) signal is applied, and the fifth LOG signal line 150e is a signal line to which a gate shift clock (GSC) signal is applied, and the sixth LOG The signal line 150f is a signal line to which the gate start pulse GSP is applied.

The seventh LOG signal line 150g is a signal line to which a gate high voltage VGH is applied, and the eighth LOG signal line 150h is a signal line to which a common voltage Vcom is applied.

The first LOG signal line group 150 including the first to eighth LOG signal lines 150a to 150h is electrically connected to the first gate pad part 115a positioned on the thin film transistor array substrate 103 (see FIG. 2). Connected.

4 is a diagram illustrating a connection relationship between a first LOG signal line group and a first gate pad unit of FIG. 3.

As shown in FIGS. 3 and 4, the first LOG signal line group 150 is electrically connected to the first gate pad part 115a. The first gate pad part 115a includes a plurality of gate pads including first to eighth gate pads 118a to 118h.

The first gate pad 118a is electrically connected to the first LOG signal line 150a of the first LOG signal line group 150 to form a gate low voltage VGL from the first LOG signal line 150a. It is supplied to the gate driver (110 in FIG. 1) to be electrically connected to the first gate pad unit 115a.

The second gate pad 118b is electrically connected to the second LOG signal line 150b of the first LOG signal line group 150 to receive a ground (GND) voltage from the second LOG signal line 150b. This is supplied to the gate driver 110. The third gate pad 118c is electrically connected to the third LOG signal line 150c of the first LOG signal line group 150 to receive a power supply voltage Vcc from the third LOG signal line 150c. This is supplied to the gate driver 110.

The fourth gate pad 118d receives a gate output enable signal (GOE) from the fourth LOG signal line 150d of the first LOG signal line group 150 and supplies it to the gate driver 110. The fifth gate pad 118e receives a gate shift clock (GSC) signal from the fifth LOG signal line 150e of the first LOG signal line group 150 and supplies it to the gate driver 110.

The sixth gate pad 118f receives the gate start pulse GSP from the sixth LOG signal line 150f of the first LOG signal line group 150 and supplies it to the gate driver 110. The seventh gate pad 118g receives the gate high voltage VGH from the seventh LOG signal line 150g of the first LOG signal line group 150 and supplies the gate high voltage VGH to the gate driver 110. The gate pad 118h is connected to the gate line of the liquid crystal display panel 100 to provide a gate signal to the gate line.

In this case, the third gate pad 118c is integrally formed with a direction setting pad for setting a gate signal output direction of the gate driver 110 positioned on the left side of the liquid crystal display panel 100 of FIG. It has twice the area when compared with.

The third gate pad 118c supplies a power supply voltage Vcc to the gate driver 110, and simultaneously outputs a gate signal of the gate driver 110 positioned on the left side of the liquid crystal display panel 100 in FIG. 2. It is responsible for setting up.

When a power supply voltage Vcc is applied to the direction setting pad for setting the gate signal output direction, the gate driver 110 positioned on the left side of the liquid crystal display panel 100 is directed from the upper end of the liquid crystal display panel 100 to the lower end thereof. The gate signal is supplied to the gate line.

By integrally forming a direction setting pad for setting the gate signal output direction of the gate driver 110 positioned on the left side of the liquid crystal display panel 100 to the third gate pad 118c to which the power voltage Vcc is applied. The LOG signal line to which the DIR signal for setting the output direction of the gate signal is applied can be removed. In addition, as the LOG signal line is removed, an effective area of the LOG signal line can be secured, and the output characteristics of the gate driver can be improved to improve product reliability.

FIG. 5 is an enlarged view of region B of FIG. 2.

As shown in FIGS. 2 and 5, the second LOG signal line group 160 includes first to eighth LOG signal lines 160a to 160h. The first to eighth LOG signal lines 160a to 160h extend from the data pad unit 125 of FIG. 2.

The first to eighth LOG signal lines 160a to 160h included in the second LOG signal line group 160 are the first to eighth LOG signal lines 150a to 160 included in the first LOG signal line group 150. 150h), so a description thereof will be briefly provided.

The second LOG signal line group 160 including the first to eighth LOG signal lines 150a to 150h is electrically connected to the second gate pad portion 115a positioned on the thin film transistor array substrate 103 (see FIG. 2). Connected.

FIG. 6 is a diagram illustrating a connection relationship between the second LOG signal line group and the second gate pad unit of FIG. 5.

As shown in FIGS. 5 and 6, the second LOG signal line group 160 is electrically connected to the second gate pad part 115b. The second gate pad part 115b includes a plurality of gate pads including first to eighth gate pads 119a to 119h.

The first gate pad 119a is electrically connected to the first LOG signal line 160a of the second LOG signal line group 160 to receive a gate low voltage VGL from the first LOG signal line 160a. It is supplied to the gate driver (110 in FIG. 1) to be provided and electrically connected to the second gate pad part 115b.

The second gate pad 119b is electrically connected to the second LOG signal line 160b of the second LOG signal line group 160 to receive a ground (GND) voltage from the second LOG signal line 160b. This is supplied to the gate driver 110. The third gate pad 119c is electrically connected to the third LOG signal line 160c of the second LOG signal line group 160 to receive a power supply voltage Vcc from the third LOG signal line 160c. This is supplied to the gate driver 110.

The fourth gate pad 119d receives a gate output enable signal (GOE) from the fourth LOG signal line 160d of the second LOG signal line group 160 and supplies it to the gate driver 110. The fifth gate pad 119e receives a gate shift clock (GSC) signal from the fifth LOG signal line 160e of the second LOG signal line group 160 and supplies it to the gate driver 110.

The sixth gate pad 119f receives the gate start pulse GSP from the sixth LOG signal line 160f of the second LOG signal line group 160 and supplies it to the gate driver 110. The seventh gate pad 119g receives the gate high voltage VGH from the seventh LOG signal line 160g of the second LOG signal line group 160 and supplies the gate high voltage VGH to the gate driver 110. The gate pad 119h is connected to the gate line of the liquid crystal display panel 100 to provide a gate signal to the gate line.

In this case, the second gate pad 119b is integrally formed with a direction setting pad for setting a gate signal output direction of the gate driver 110 positioned on the right side of the liquid crystal display panel 100 of FIG. It has twice the area when compared with.

The second gate pad 119b supplies a ground (GND) voltage to the gate driver 110 and at the same time the gate signal output direction of the gate driver 110 positioned on the right side of the liquid crystal display panel 100 of FIG. 2. It is responsible for setting up.

When the ground (GND) voltage is applied to the direction setting pad for setting the gate signal output direction, the gate driver 110 positioned on the right side of the liquid crystal display panel 100 is directed from the upper end of the liquid crystal display panel 100 to the lower end thereof. The gate signal is supplied to the gate line.

By integrally forming a direction setting pad for setting the gate signal output direction of the gate driver 110 positioned on the right side of the liquid crystal display panel 100 to the second gate pad 119b to which the ground (GND) voltage is applied. The LOG signal line to which the DIR signal for setting the output direction of the gate signal is applied can be removed. In addition, as the LOG signal line is removed, an effective area of the LOG signal line can be secured, and the output characteristics of the gate driver can be improved to improve product reliability.

As described above, when the power supply voltage Vcc and the ground GND are supplied to the direction setting pad for setting the gate signal output directions included in the first and second gate pad parts 112a and 112b, respectively, The gate drivers 110 of FIG. 1 positioned on the left and right sides of the liquid crystal display panel 100 connected to the first and second gate pad parts 112a and 112b may output gate signals in different directions.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic view of the liquid crystal display panel of FIG. 1; FIG.

3 is an enlarged view of a region A of FIG. 2;

4 is a diagram illustrating a connection relationship between a first LOG signal line group and a first gate pad unit of FIG. 3.

5 is an enlarged view of a region B of FIG. 2;

FIG. 6 is a diagram illustrating a connection relationship between a second LOG signal line group and a second gate pad part of FIG. 5; FIG.

<Brief description of the main parts of the drawing>

100: liquid crystal display panel 110: gate driver

115a: first gate pad portion 115b: second gate pad portion

118a to 118h, 119a to 119h: first to eighth gate pads

120: data driver 125: data pad unit

130: timing controller 140: common voltage generator

150: first LOG signal line group 160: second LOG signal line group

150a to 150h: first to eighth LOG signal lines

160a to 160: first to eighth LOG signal line

Claims (5)

A liquid crystal display panel in which a plurality of gate lines and data lines are arranged and divided into a display area and a non-display area; First and second gate drivers positioned on left and right sides of the non-display area and providing gate signals to a plurality of gate lines; A printed circuit board configured to provide a driving signal and a driving voltage to the first and second gate drivers and the data driver; First and second LOG signal line groups formed in the non-display area of the liquid crystal display panel to provide the driving signal and the driving voltage to the first and second gate drivers, respectively; A first gate pad part connected to the first LOG signal line group to position the first gate driver to the left of the non-display area of the liquid crystal display panel; And A second gate pad part connected to the second LOG signal line group to position the second gate driver to the right of the non-display area of the liquid crystal display panel; And a directional pad configured to set the gate signal output direction of the first and second gate drivers in each of the first and second gate pad parts. The method according to claim 1, And the direction setting pad of the first gate pad part is integrally formed with a gate pad to which a power voltage Vcc is applied to the first gate driver. The method of claim 2, When the power supply voltage Vcc is applied to the direction pad of the first gate pad unit, the first gate driver provides a gate signal to a gate line in a direction from an upper end portion to a lower end portion of the liquid crystal display panel. Device. The method according to claim 1, The directional pad of the second gate pad part may be integrally formed with a gate pad to which a ground (GND) voltage is applied to the second gate driver. 5. The method of claim 4, When the ground (GND) voltage is applied to the direction pad of the second gate pad unit, the second gate driver provides a gate signal to a gate line in a direction from an upper end portion to a lower end portion of the liquid crystal display panel. Device.

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