KR20110068386A - Semiconductor system and method for operating the same - Google Patents

Abstract

PURPOSE: A semiconductor system and method for operating the same are provided to process data rapidly between a memory device and processors by using the memory device as a path for transmitting instruction, address, and data. CONSTITUTION: A first save area stores the access command outputted from a first processor (20). A second save area stores data corresponding to the access command. A second processor(40) is outputted from the first processor according to the access command, and reads the data saved on the second save area to write the data on a non-volatile memory device(50) or record the data read from the non-volatile memory to the second save area.

Description

Semiconductor system and method for operating the same

Embodiments of the inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device capable of using a shared memory bank as a path for transferring commands, addresses, and data, and a semiconductor system including the same.

In a data processing system including a memory device and processors, a technique for processing desired data at high speed between the memory device and the processors is required.

Accordingly, the technical problem to be achieved by the present invention is to provide an apparatus and a method capable of processing data at high speed between a memory device and a processor.

In an embodiment, a memory device may include a first storage area for storing a plurality of access commands output from a first processor and to be read by a second processor; A second storage area for storing data corresponding to each of the plurality of access commands; And a third storage area for storing indices for the plurality of access commands.

In an embodiment, a semiconductor system may include a nonvolatile memory device; A memory device including a first storage area for storing an access command output from a first processor, and a second storage area for storing data corresponding to the access command; And a second processor.

The second processor reads the access command stored in the first storage area and reads the data output from the first processor and stored in the second storage area according to the read access command to the nonvolatile memory device. And a second processor for writing the data read from the nonvolatile memory device to the second storage area as the data.

According to an embodiment of the present disclosure, a method of operating a semiconductor system may include: writing, by a first processor, write data corresponding to an access command to a second storage area of a memory device; Writing, by the first processor, the access command to a first storage area of the memory; Reading, by a second processor, the access command stored in the first storage area in response to an interrupt signal output from the memory device; And reading, by the second processor, the write data stored in the second storage area and writing the read write data to a nonvolatile memory device according to the access command.

According to another exemplary embodiment of the inventive concept, a method of operating a semiconductor system may include: writing, by a first processor, an access command to a first storage area of a memory device; Reading, by a second processor, the access command stored in the first storage area in response to an interrupt signal output from the memory device; Reading, by the second processor, data from a nonvolatile memory device and writing the read data to a second storage area of the memory device according to the access command; And reading, by the first processor, the data stored in the second storage area in response to an interrupt signal output from the memory device.

In an embodiment, a semiconductor system may include a nonvolatile memory device; A first processor for generating an access instruction; A memory device including a first storage area for storing the access command output from the first processor, and a second storage area for storing data corresponding to the access command; And read the access command stored in the first storage area and read the data output from the first processor 20 and stored in the second storage area according to the read access command and write the data to the nonvolatile memory device. Or to write data read from the nonvolatile memory device to the second storage area as the data.

The second processor reads the access command in response to an interrupt signal output from the memory device. The first processor reads the data stored in the second storage device in response to an interrupt signal output from the memory device.

A semiconductor system including a memory device and a plurality of processors according to an embodiment of the present invention may use the memory device as a path for transferring commands, addresses, and data, thereby providing high speed between the memory device and the plurality of processors. It has the effect of processing data.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to specific forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another, for example, without departing from the scope of rights in accordance with the inventive concept, and the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a semiconductor system in accordance with an embodiment of the present invention. Referring to FIG. 1, the semiconductor system 10 includes a first processor 20, a memory device 30, a second processor 40, and a nonvolatile memory device 50.

The semiconductor system 10 may include a personal computer, a notebook, a netbook, an e-book, an e-book, a memory card, a smart card, a cellular phone, and a personal digital assistant. It may be an assitant, a portable multimedia player (PMP), or a digital TV.

The first processor 20 may generate a data packet 200 as shown in FIG. 5 as a host such as a CPU and transmit the generated data packet to the memory device 30. According to an embodiment, the first processor 20 may generate a plurality of data packets and sequentially transmit the generated data packets to the memory device 30.

The memory device 30 may be implemented as a multi-port memory device, and access commands and command data (for example, write data to be written to the nonvolatile memory device 50 or read data read from the nonvolatile memory device 50). ) Can be stored in a shared memory bank.

The second processor 40 may be implemented as an application-specific integrated circuit (ASIC) and may access the nonvolatile memory device 50 according to the access command.

For example, during a write operation, the second processor 40 may write command data stored in the shared memory bank to the nonvolatile memory device 50 according to an access command stored in the shared memory bank of the memory device 30. In addition, during a read operation, the second processor 40 reads data from the nonvolatile memory device 50 according to an access command stored in the shared memory bank of the memory device 30, and writes the read data to the shared memory bank. can do.

The nonvolatile memory device 50 may include a plurality of memory blocks 50-1 to 50-n. Each of the plurality of memory blocks 50-1 to 50-n may include a plurality of memory cells. Each of the plurality of memory blocks 50-1 to 50-n may be referred to as a way.

Each of the plurality of memory cells may be implemented as a non-volatile memory cell. The nonvolatile memory cell includes an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM (CRAM), a conductive bridging RAM (CBRAM), and a ferroelectric RAM (FeRAM). Phase Change RAM (PRAM), Resistive Memory (RRAM or ReRAM), Nanotube RRAM, Polymer RAM (PoRAM), Nano Floating Gate Memory (NFGM), Holo Graphics memory (holographic memory), molecular electronic memory device (Molecular Electronics Memory Device), or Insulator Resistance Change Memory (Insulator Resistance Change Memory). The nonvolatile memory cell may store one bit or a plurality of bits.

According to an embodiment, the second processor 40 and the nonvolatile memory device 50 may be implemented as one chip or one package (eg, a multi chip package). According to an embodiment, the memory device 30, the second processor 40, and the nonvolatile memory device 50 may be implemented in one package (eg, MCP).

The first processor 20 writes write data to the shared memory bank of the memory device 30 or reads data from the shared memory bank of the memory device 30 at the first data rate.

The second processor 40 reads the write data stored in the shared memory bank of the memory device 30 at the second data rate and reads the read data output from the nonvolatile memory device 50 from the shared memory bank of the memory device 30. Light on. The first data rate is higher than the second data rate.

FIG. 2 is a schematic block diagram of the semiconductor device shown in FIG. 1. Referring to FIG. 2, the memory device 30 may include a first port 31, a plurality of memory banks 33-1, 33-2, 33-3, and 33, which may be connected to the second processor 40. A data storage area 33 including -4), and a second port 35 that can be connected to the first processor 20.

Each of the first port 31 and the second port 35 means a controller or an interface capable of giving or receiving data according to a DRAM protocol.

Each of the plurality of memory banks 33-1, 33-2, 33-3, and 33-4 includes a plurality of volatile memory cells. For example, each of the plurality of volatile memory cells may be implemented as a DRAM.

The memory bank 33-1 is a second processor dedicated memory bank that can be accessed by the second processor 40 through the first port 31. Accordingly, the second processor 40 may read data stored in the memory bank 33-1 or write data in the memory bank 33-1 through the first port 31.

The memory banks 33-3 and 33-4 are memory banks dedicated to the first processor that can be accessed by the first processor 20 through the second port 35. Thus, the first processor 20 writes data to each of the memory banks 33-3 and 33-4 or writes to each of the memory banks 33-3 and 33-4 through the second port 35. You can read the stored data.

The memory bank 33-2 is accessed by the second processor 40 connected to the first port 31 or by the first processor 20 connected to the second port 35 depending on the access right. It can be a shared memory bank. Here, the access means a write operation or a read operation.

For example, when the second processor 40 has access to the shared memory bank 33-2, the second processor 40 can access each of the memory banks 33-1 and 33-2, but the second processor 40 can access the shared memory bank 33-2. 1 processor 20 cannot access shared memory bank 33-2. In addition, when the first processor 20 has access to the shared memory bank 33-2, the first processor 20 assigns each of the memory banks 33-2, 33-3, and 33-4. Although accessible, the second processor 40 may not access the shared memory bank 33-2.

An access circuit (eg, a read / write circuit) capable of accessing each of the memory banks 33-1 and 33-2 may be implemented between the first port 31 and the data storage region 33. In addition, an access circuit (eg, a read / write circuit) to access each memory bank 33-2, 33-3, and 33-4 is implemented between the second port 35 and the data storage region 33. Can be. According to an embodiment, each access circuit may be implemented as part of each port 31 and 35.

FIG. 3 shows a schematic memory map of the shared memory bank shown in FIG. 2. Referring to FIG. 3, the shared memory bank 33-2 includes a control block and a register block 140. The control block includes a queue manager area (or index storage area) 100, a command area 110, a command data area 120, and an instant data area 130.

The queue manager area 100 is an area for storing information for managing the command data area 120 and may store a start command index HEAD and an end command index TAIL among data packets. For example, the number of access commands may be determined according to the start command index HEAD and the end command index TAIL.

The command area 110 may store an instant command INS CMD and a plurality of access commands CMD1, CMD2, CMD3, CMD4, CMD5,...

The command data area 120 may store command data (eg, write data or read data) corresponding to each access command that may be stored in the command area 110.

For example, first command data corresponding to the first access command CMD1 is stored in the first command data storage area 120-1, and second command data corresponding to the second access command CMD2 is the second command. Third command data stored in the data storage area 120-2 and corresponding to the third access command CMD3 may be stored in the third command data storage area 120-3.

In this case, the access command CMD may include a write command, an address of a shared memory bank in which write data is stored, and an address of the nonvolatile memory device 50 in which the write data is to be stored. In addition, during a read operation, the access command CMD includes a read command, an address of a shared memory bank in which read data is to be stored, and an address of the nonvolatile memory device 50 in which the read data is stored.

According to an embodiment, the command data corresponding to the instant command INS CMD may be stored in the instant data area 130.

The register block 140 may store a message exchanged between the first processor 20 and the second processor 40.

As shown in FIG. 3, the register block 140 may include a plurality of registers 141 ˜ 145. The plurality of registers 141 ˜ 145 may include internal registers 141 ˜ 145 and reserved registers (Reversed). For example, register block 140 may be a size corresponding to one row size, such as N-KB (eg, N is a natural number, N = 2).

For example, when a specific row address output from the first processor 20 is input to the memory device 30, the specific memory area of the shared memory bank 33-2 is disabled and the internal registers 141-155 are disabled. It can be enabled.

The internal registers 141-145 may include a semaphore register 141, mailbox registers 142 and 143, and check registers 144 and 145. The internal registers 141 to 145 may solve a conflict situation that may occur when the first processor 20 and the second processor 40 simultaneously access the shared memory bank 33-2. Can be done.

The semaphore register 141 may store a bit indicating which port, for example, the first port 31 or the second port 35, has access to the shared memory bank 33-2.

For example, the value '1' of the semaphore register 141 indicates that the first processor 20 connected to the second port 35 has access to the shared memory bank 33-2. The value '0' of the semaphore register 141 indicates that the second processor 40 connected to the first port 31 has access to the shared memory bank 33-2. The reverse is also possible depending on the embodiment. The value of the semaphore register 141 may be written or changed only by the processor 20 or 40 having access to the shared memory bank 33-2.

Each mailbox register 142 and 143 may be used to store messages exchanged between the first processor 20 and the second processor 40.

For example, when the second processor 40 writes the message to the mailbox register 142 to transmit the message to the first processor 20, the first processor 20 writes the message. The message stored in the mailbox register 142 is read in response to the interrupt signal output from the memory device 30.

Conversely, if the first processor 20 writes the message to the mailboxBA 143 to send the message to the second processor 40, the second processor 40 Reads the message stored in the mailbox register 143 in response to the interrupt signal output from the memory device 30.

When a message is written to each mailbox register 142 and 143, an interrupt signal is generated by the memory device 30.

For example, when a message is written to the mailbox register 142, an interrupt signal is transmitted to the first processor 20 through the second port 35. Accordingly, the first processor 20 reads the message written to the mailbox register 142 in response to the interrupt signal, decodes the read message, and performs an operation corresponding to the decoding result.

In addition, when a message is written to the mailbox register 143, the interrupt signal is transmitted to the second processor 40 through the first port 31. Accordingly, the second processor 40 reads the message written to the mailbox register 143 in response to the interrupt signal, decodes the read message, and performs an operation corresponding to the decoding result.

The value of each check register 144 and 145 indicates whether the message written to each mailbox register 142 and 143 has been read by the partner processor. The value of each check register 144 and 145 can be automatically changed in accordance with the read / write command output to each mailbox register 142 and 143.

For example, when the second processor 40 outputs a write command to write a message to the mailbox register 142, the value of the check register 144 may be set to '1'. When the processor 20 outputs a read command to read the message stored in the mailbox register 142, the value of the check register 144 may be set to '0'.

Referring to FIGS. 1 to 3, a case where the access right to the shared memory bank 33-2 is transferred from the first processor 20 to the second processor 40 will be described below.

Since the value of the semaphor register 141 is initially set to '1', the first processor 20 uses the second port 35 to not only use the dedicated memory banks 33-3 and 33-4. The shared memory bank 33-2 can be accessed. In this case, the second processor 40 may access the dedicated memory bank 33-1 but cannot access the shared memory bank 33-2.

First, the first processor 20 checks the value of the semaphore register 141 (eg, '1') through the second port 35 to check the access right to the shared memory bank 33-2. Lead.

Second, the second processor 40 writes a message in the mailbox register 142 to request the change of the access right to the shared memory bank 33-2. At this time, the interrupt signal is activated to notify the first processor 20 that the message is written to the mailbox register 142.

Third, the first processor 20 reads the message written to the mailbox register 142 in response to the activated interrupt signal.

Fourth, in response to the message, the first processor 20 changes the value of the semaphore register 141 from '1' to '0' through the second port 35. The first processor 20 writes a message for notifying that the value of the semaphore register 141 has changed from '1' to '0' in the mailbox register (MailboxBA) 143. At this time, the interrupt activated by the memory device 30 is transmitted to the second processor 40.

Fifth, the second processor 40 reads a message written to the mailbox register 143 through the first port 31 in response to the activated interrupt signal.

Sixth, the second processor 40 reads the value of the semaphore register 141 through the first port 31 according to the message to confirm that the access right to the shared memory bank 33-2 has been changed. Accordingly, the second processor 40 may access the shared memory bank 33-2 through the first port 41.

As described above, a processor that does not have access to the shared memory bank 33-2 is a processor having access to the shared memory bank 33-2 using the register block 140. 33-2) may request to change access rights. In this case, a processor having access to the shared memory bank 33-2 may maintain or change the value of the semaphore register 141.

4 shows a schematic block diagram of the second processor shown in FIG. 1. Referring to FIG. 4, a second processor, such as an ASIC 40, may include a plurality of controllers 41 and 42, a processor 44, a ROM 45, and a RAM 46.

The first controller 41 refers to a controller or an interface capable of communicating with the first port 31 shown in FIG. 2.

The first controller 41 reads the access command stored in the command area 110 under the control of the processor 44 and reads the write data stored in the command data area 120 according to the read access command or reads the nonvolatile memory. The read data output from the device 50 may be written to the command data area 120. For example, the first controller 41 may refer to a controller or an interface capable of supporting (or using) a DRAM protocol.

The second controller 42 may refer to a controller or an interface capable of transmitting write data or receiving read data to the nonvolatile memory device 50 according to a data communication protocol of the nonvolatile memory device 50. According to an embodiment, the second controller 42 may be a NAND flash controller or an interface.

At boot time, processor 44 may load a program stored in ROM 45 into RAM 46 and execute the loaded program. The processor 44 may control the operation of each controller 41 and 42 according to the program.

5 illustrates a data packet according to an embodiment of the present invention. 1 and 5, the first processor 20 generates a data packet to use the shared memory bank 33-2 of the memory device 30 as a storage area for transmitting access commands and data. .

As illustrated in FIG. 5, the data packet 200 generated by the first processor 20 to perform a write operation or a read operation includes a plurality of information areas 210 to 26. The first information area 210 stores information about the command. The command may be a write command or a read command.

The second information area 220 stores a start command index, and the third information area 230 stores an end command index. Therefore, the information about the number of the plurality of access commands output from the first processor 20 is stored in the start command index and the end command index. Therefore, the memory system 10 may sequentially process a plurality of access commands.

The fourth information area 240 stores the address of the shared memory bank 33-2 in which command data is to be stored or stored, and the fifth information area 250 is stored or stored in the shared memory bank 33-2. Store the size of the data.

The sixth information area 260 indicates an address of the nonvolatile memory 50 in which write data is to be stored in a write operation or an address in which read data read from the nonvolatile memory 50 is stored in a read operation. The access command includes information stored in each information area 210, 240, 250, and 260.

FIG. 6 is a flowchart for describing a write operation of the semiconductor system illustrated in FIG. 1. A write operation of the semiconductor system 10 will be described with reference to FIGS. 1 to 6 as follows.

First, it is assumed that the first processor 20 has access to the shared memory bank 33-2. The first processor 20 writes the write data to the control block, for example, the first command data area 120-1 of the command data area 120 through the second port 35 (S10). The first processor 20 generates a data packet 200 for the write data and transmits the generated data packet to the memory device 30. The memory device 30 extracts an access command from the data packet 200 and writes it to the command area 110 of the control block (S20).

The first processor 20 writes the message to the mailbox register 413 through the second port 35 (S30). In this case, the memory device 30 transmits the activated interrupt signal to the second processor 40 through the first port 31.

The second processor 40, which does not have access to the shared memory bank 33-2, accesses the shared memory bank 33-2 from the first processor 20 in response to the activated interrupt signal. Perform the operation to take over.

The processor 44 of the second processor 40 having received the access right to the shared memory bank 33-2 reads the message stored in the mailbox register 413 (S50). The second processor 40 reads the access command stored in the command area 110 of the control block of the shared memory bank 33-2 in response to the read message (S60).

The second processor 40 decodes the access command and reads the write data stored in the first command data area 120-1 of the command data area 120 according to the decoding result (S70). The write data is written to the nonvolatile memory device 50 using the second controller 42 (S80).

After the write operation is completed, the controller 44 of the second processor 40 writes a message for indicating that the write operation is completed to the mailbox register 142 using the first port 31. (S90). The memory device 30 transmits the activated interrupt signal to the first processor 20. The first processor 20 performs a procedure for taking over access to the shared memory bank 33-2. The first processor 20 that has received the access right to the shared memory bank 33-2 reads a message stored in the mailbox register 142 (S100).

The order of progress of each step (S10, S20, S30, and S40) may be variously changed according to embodiments. For example, the data write operation may be performed in the order of S30, S40, S10, S20, and S50.

7A through 7F illustrate data processing processes of the semiconductor device illustrated in FIG. 1. A write operation according to an embodiment of the present invention will be described in more detail with reference to FIGS. 1 to 7F.

It is assumed that the first processor 20 has access to the shared memory bank 33-2, and the initial state of the shared memory bank 33-2 is empty as shown in FIG. 7A.

As shown in FIG. 7B, the first processor 20 writes one write data to the first command data area 120-1 of the command data block 120 (S10), and writes one data packet. The generated data packet is transmitted to the memory device 30. In this case, the start command index H and the end command index T may be set to one.

The memory device 30 decodes the received data packet, stores the start command index H and the end command index T in the queue manager area 100 according to the decoding result, and stores the first access command CMD1 in the command area. The data is stored in the second storage area 110-1 of 110 (S20).

The first processor 20 writes a message to the mailbox register 143 (S30). Therefore, the memory device 30 outputs the activated interrupt signal to the second processor 40 (S40). Accordingly, the second processor 40 performs an operation for taking over access to the shared memory bank 33-2 in response to the activated interrupt signal.

The second processor 40 having transferred the access right to the memory bank 33-2 reads and decodes the message written to the mailbox register 143 (S50).

According to the decoding result, the second processor 40 reads the first access command CMD1 stored in the second storage area 110-1 of the command area 110 (S60), and reads the read first access command ( According to the CMD1, the write data stored in the first command data area 120-1 is read (S70), and the read write data is written to the nonvolatile memory device 50 (S80).

When the write operation is finished, the second processor 40 writes a message to the mailbox register 142 (S90). In this case, the memory device 30 outputs the activated interrupt signal to the first processor 20. When the write operation is completed, the control block of the shared memory bank 33-2 may be empty as shown in FIG. 7C.

The first processor 20 which does not have access to the shared memory bank 33-2 performs an operation for taking over access to the shared memory bank 33-2 in response to the activated interrupt signal. .

The first processor 20 having received the access right to the shared memory bank 33-2 reads the message stored in the mailbox register 142 (S100).

As another example, as shown in FIG. 7D, the first processor 20 writes the first write data to the first command data storage area 120-1 and the second write data to the second command data storage area ( 120-2), a data packet including information about the first write data and the second write data is generated, and the generated data packet is transmitted to the memory device 30.

The memory device 30 extracts a start command index (H: 0x1) and an end command index (T: 0x2) from the received data packet, stores the extracted indexes in the queue manager area 100, and stores the extracted indexes in the first write data. The first access command CMD1 instructing the processing of the data is stored in the second area 110-1 of the command area 110, and the second access command CMD2 instructs the processing of the second write data. The data is stored in the third region 110-2 of 110.

As shown in FIG. 7E, the second processor 40 that receives the access right to the shared memory bank 33-2 may store the first access command stored in the second area 110-1 of the command area 110. The CMD1 is read, and the first write data stored in the first command data area 120-1 is written to the nonvolatile memory device 50 according to the read first access command CMD1. Therefore, only the second write data remains in the second command data area 120-2.

Subsequently, as shown in FIG. 7F, the first processor 20 having access to the shared memory bank 33-2 transmits the third write data to the third command data storage area 120-3. Write the fourth write data to the fourth command data storage area 120-4, write the fifth write data to the fifth command data storage area 120-5, and write the third write data to the third write data. A data packet including the fourth write data and the information on the fifth write data is generated and the generated data packet is transmitted to the memory device 30.

The memory device 30 extracts a start command index (H: 0x3) and an end command index (T: 0x5) from the received data packet, stores the extracted indexes in the queue manager area 100, and stores the extracted indexes in the third write data. The third access command CMD3 instructing the processing for the data is stored in the fourth area 110-3 of the command area 110, and the fourth access command CMD4 instructing the processing for the fourth write data is commanded. The fifth access command CMD5 stored in the fifth area 110-4 of the area 110 and instructing processing of the fifth write data is stored in the sixth area 110-5 of the command area 110. Save it.

The second processor 20 having access to the shared memory bank 33-2 accesses the shared memory bank 33-2 so that the second data can be accessed according to each access command CMD2, CMD3, CMD4, and CMD5. The third data, the fourth data, and the fifth data may be written to the nonvolatile memory device 50 in a predetermined order.

8 is a flowchart for describing a read operation of the semiconductor system illustrated in FIG. 1. The read operation of the semiconductor system 10 will be described in detail with reference to FIGS. 1 through 5 and 8. The first processor 20 having access to the shared memory bank 33-2 writes an access command to the command area 110 of the control block (S200).

In operation S210, the first processor 20 writes a message to the mailbox register 143. In this case, the memory device 30 transmits the activated interrupt signal to the second processor 40 (S220). Accordingly, the second processor 40 performs a procedure for taking over access to the shared memory bank 33-2 in response to the activated interrupt signal.

The second processor 40 having received the access right to the shared memory bank 33-2 reads the message to the mailbox register 143 (S230), and access command stored in the command area 110 according to the message. Is read (SS240).

The second processor 40 reads data from the nonvolatile memory device 50 according to the access command (S250), and reads the read data in the command data area of the shared memory bank 33-2 according to the access command. 120) (S260).

Thereafter, the second processor 40 writes a message to the mailbox register 142 (S270). At this time, the memory device 30 transmits the activated interrupt signal to the first processor 20). Accordingly, the first processor 20 performs a procedure for taking over access to the shared memory bank 33-2 in response to the activated interrupt signal.

The first processor 20 that has received access to the shared memory bank 33-2 reads a message stored in the mailbox register 142 (S280), and stores the message stored in the command data area 120 according to the message. The data is read (S290). Thus, the read operation of the semiconductor system 10 is terminated.

The memory device 30 according to an embodiment of the present disclosure may use the shared memory bank 33-2 as a transfer area of an access command and command data.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a block diagram of a semiconductor system in accordance with an embodiment of the present invention.

FIG. 2 is a schematic block diagram of the memory device shown in FIG. 1.

FIG. 3 shows a schematic memory map of the shared memory bank shown in FIG. 2.

4 shows a schematic block diagram of the second processor shown in FIG. 1.

5 illustrates a data packet according to an embodiment of the present invention.

FIG. 6 is a flowchart for describing a write operation of the semiconductor system illustrated in FIG. 1.

7A through 7F illustrate data processing processes of the memory device illustrated in FIG. 1.

8 is a flowchart for describing a read operation of the semiconductor system illustrated in FIG. 1.

Claims (9)

Nonvolatile memory devices; A memory device including a first storage area for storing an access command output from a first processor, and a second storage area for storing data corresponding to the access command; And Read the data output from the first processor and stored in the second storage area according to the read access command and write the data to the nonvolatile memory device according to the read access command; And a second processor for writing data read from a volatile memory device into the second storage area as the data. The semiconductor system of claim 1, wherein the memory device further comprises a third storage area for storing an index of the access command. The semiconductor system of claim 1, wherein the memory device further comprises a register block configured to store a message exchanged between the first processor and the second processor. Writing, by the first processor, write data corresponding to the access command to the second storage area of the memory device; Writing, by the first processor, the access command to a first storage area of the memory; Reading, by a second processor, the access command stored in the first storage area in response to an interrupt signal output from the memory device; And In response to the access command, the second processor reading the write data stored in the second storage area and writing the read write data to a nonvolatile memory device. The method of claim 4, further comprising performing a procedure for the second processor to take over access to the memory device. Writing, by the first processor, the access command to the first storage area of the memory device; Reading, by a second processor, the access command stored in the first storage area in response to an interrupt signal output from the memory device; Reading, by the second processor, data from a nonvolatile memory device and writing the read data to a second storage area of the memory device according to the access command; And And the first processor reading the data stored in the second storage area in response to an interrupt signal output from the memory device. Nonvolatile memory devices; A first processor for generating an access instruction; A memory device including a first storage area for storing the access command output from the first processor, and a second storage area for storing data corresponding to the access command; And Read the data output from the first processor and stored in the second storage area according to the read access command and write the data to the nonvolatile memory device according to the read access command; And a second processor for writing data read from a volatile memory device into the second storage area as the data. The semiconductor system of claim 7, wherein the second processor reads the access command in response to an interrupt signal output from the memory device. The semiconductor system of claim 7, wherein the first processor reads the data stored in the second storage area in response to an interrupt signal output from the memory device.

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