KR20110059491A - Image sensor driving circuit and method for detecting radiation - Google Patents

Abstract

PURPOSE: A driver circuit and a method of an image sensor detecting radiation are provided to double the low scan speed. CONSTITUTION: A scan driver(120) selects a row line. A column driver(130) reads out a photoelectric conversion signal from the pixels of the selected row line. According to a normal mode or a binning mode operation of the scan driver, the column driver includes an odd CDS(Correlated Differential Sampling) circuit and an even CDS circuit. The odd CDS circuit respectively reads out the photoelectric conversion signal of an odd column in the normal mode or the binning mode. The even CDS circuit respectively reads out the photoelectric conversion signal of an even column in the normal mode or the binning mode.

Description

Image Sensor Driving Circuit and Method for Detecting Radiation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and a method of an image sensor. The present invention relates to a normal mode for sequentially reading a signal in each column from 3-TR pixels of an image sensor for detecting radiation such as X-rays and obtaining an image. Binning mode, which reads signals for a plurality of neighboring pixels in a normal mode) and two columns by a charge summation method, supports a charge summation method in a binning mode, while reading speed It relates to a driving circuit and method of the image sensor that can improve the.

In general, a technique of irradiating an X-ray to an affected area and acquiring an image thereof is used to diagnose a patient's cancer or other affected condition. X-ray imaging techniques are widely used, such as a general radiography (GR) method for acquiring still images on a general analog film, and a computed radiography (CR) method for digitizing images by reading an X-ray irradiated onto an image plate with a predetermined reader. . In addition, in recent years, it was appeared DR (Digital adiography R) system that digitizes an image by detecting the X- ray directly using a semiconductor image sensor.

Recently, in the DR method, various radiation diagnostic devices using semiconductor image sensors have been developed and commercialized. Radiation diagnostic method using such a semiconductor image sensor is expected to be widely used for diagnosing the condition of breast cancer or other lesions due to its convenience.

Various methods have been attempted to read a photoelectric conversion signal from pixels in the operation of such a semiconductor image sensor. For example, there is a method of summing charges in a floating diffusion region in a shared pixel structure and a sparse readout method for reading sparse pixel signals. However, in the 3-TR pixel structure, as the pixel size increases, it is difficult to apply the charge summation method using the shared pixel structure as described above. In order to stably read a pixel signal with high sensitivity even at a low dose, a binning method that can adopt a charge summing method in a 3-TR pixel structure is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to sequentially read a signal in each column from 3-TR pixels of an image sensor for detecting an X-ray or the like and obtaining an image. Supports a normal mode and a binning mode in which signals for a plurality of neighboring pixels of two columns are read by a charge summation method, while the charge summation method is supported while the binning mode is read. To provide a driving circuit and method of an image sensor that can improve the speed.

First, to summarize the features of the present invention, the driving circuit of the image sensor according to an aspect of the present invention for achieving the above object is, from the scan driver to select a low line and the pixels of the row line selected by the scan driver And a column driver for reading the photoelectric conversion signal, wherein the column driver reads the photoelectric conversion signal from the odd column in the normal mode or the binning mode, respectively, according to the normal mode or the binning mode operation of the scan driver. The shipment includes an even CDS circuit and an even CDS circuit that reads photoelectric conversion signals from an even column in a normal mode or a binning mode, respectively, in the normal mode, as the scan driver sequentially selects a low line. And the odd CDS circuit and the even CDS circuit each convert a photoelectric conversion signal from a pixel of each row line of the corresponding column. Outputs sequentially, and in the binning mode, as the scan driver sequentially selects a plurality of row lines, the even CDS circuit stops operation, and the odd CDS circuit performs the pixels of the plurality of row lines of the corresponding column. And sequentially convert the photoelectric conversion signals corresponding to the photoelectric conversion signals corresponding to the photoelectric conversion signals corresponding to the pixels of the plurality of row lines of the adjacent even column by a charge summing method.

The driving circuit of the image sensor outputs the photoelectric conversion signal to the even CDS circuit of the corresponding column in the normal mode, and adjacent the photoelectric conversion signals corresponding to the pixels of the plurality of low lines of the even column in the binning mode. It includes a multiplexer for input to the odd CDS circuit.

The driving circuit of the image sensor includes a plurality of column output lines for outputting photoelectric conversion signals corresponding to pixels of an odd row line and an even row line for each column.

In the binning mode, the number of the plurality of row lines selected by the scan driver is two.

Each pixel outputting the photoelectric conversion signal may include a first transistor configured to reset the output of the photodiode according to a reset signal; A second transistor for generating a current corresponding to the output of the photodiode; And a third transistor for outputting the output of the second transistor to a column output line according to a selection signal.

In the normal mode, the odd CDS circuit and the even CDS circuit may include a first capacitor connected between a first input switch and a second input terminal of an amplifier having a first input terminal connected to a reference voltage, the second input terminal and the When the first switch and the second switch connected in parallel with the second capacitor are turned on by using a second capacitor connected between the output terminals of the amplifier, the photoelectric conversion signal from the pixel is sampled through the output terminal of the amplifier. Output

The pixel and the first capacitor are reset when the first switch is turned on and the second switch is turned off.

In the binning mode, the odd CDS circuit includes: each capacitor connected between each of a plurality of switches and a second input terminal of an amplifier having a first input terminal connected to a reference voltage, and the output terminal of the second input terminal and the amplifier; When the plurality of switches and the second switch connected in parallel with the second capacitor are turned on by using a second capacitor connected between them, corresponding to the pixels of the plurality of low lines through the output terminal of the amplifier. The photoelectric conversion signals of the odd column and the adjacent even column are sampled and output by the charge summation method.

When the plurality of switches are turned on and the second switch is turned off, the corresponding pixels and the respective capacitors are reset.

Each pixel outputting the photoelectric conversion signal generates an electrical signal with respect to radiation including incident X-rays.

According to another aspect of the present invention, a method of driving an image sensor using a scan driver for selecting a row line and a column driver for reading a photoelectric conversion signal from pixels of a row line selected by the scan driver, The column driver may be configured to read the photoelectric conversion signal from the odd column in the normal mode or the binning mode, respectively, according to the normal mode or the binning mode operation of the scan driver. In the normal mode, as the scan driver sequentially selects a low line using an even CDS circuit that reads a photoelectric conversion signal in a normal mode or a binning mode, the corresponding column in the odd CDS circuit and the even CDS circuit. Sequentially outputting photoelectric conversion signals from the pixels of each row line of the circuits; And in the binning mode, as the scan driver sequentially selects a plurality of row lines, the even CDS circuit stops operation and corresponds to pixels of the plurality of row lines of the corresponding column in the odd CDS circuit. And sequentially outputting the photoelectric conversion signals and the photoelectric conversion signals corresponding to the pixels of the plurality of row lines of the adjacent even column by a charge summation method.

According to a driving circuit and method of an image sensor according to the present invention, a normal mode for sequentially reading a signal in each column from 3-TR pixels of an image sensor for detecting radiation such as X-rays and obtaining an image normal mode) and a binning mode for reading signals for a plurality of neighboring pixels of two columns by a charge summation method, and in a binning mode, a binning mode for summing charges of 2 * 2 pixels may be added. While supporting the method, the read speed, that is, the row scan speed, can be doubled.

In addition, the driving circuit and method of the image sensor according to the present invention includes a CDS, a sigma-delta (Σ-Δ) ADC, in which the output of the pixel array uses a switched capacitor method and a charge transfer method. Or a cyclic ADC structure.

In addition, although the driving circuit and the method of the image sensor according to the present invention consist of two column output lines, an additional output line may be utilized as a metal for satisfying minimum metal coverage in pixel design. The addition of output lines allows pixel structures to be implemented without affecting the fill-factor.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of an image sensor 100 according to an embodiment of the present invention.

Referring to FIG. 1, the image sensor 100 includes a pixel array 110, a scan driver 120, and a column driver 130. Photoelectric conversion pixels are formed in the pixel array 110 in the form of a two-dimensional array, and the scan driver 120 and the column driver 130 operate as driving circuits for reading the photoelectric conversion signals detected by the pixel array 110. do. The scan driver 120 sequentially selects row lines in a row direction to activate pixels formed in the selected row line to sense light incident from the outside. The column driver 130 reads the photoelectric conversion signal in each column from the pixels of the corresponding row line selected by the scan driver 120. Here, each pixel of the pixel array 110 that outputs a photoelectric conversion signal may be photoelectrically converted to radiation including incident X-rays to generate a corresponding electrical signal. However, the present invention is not limited thereto, and the image sensor 100 may be used to acquire another image by detecting another radiation, ultraviolet ray, laser, or the like as necessary.

In particular, the scan driver 120 and the column driver 130 operate slightly differently according to a normal mode or a binning mode. For example, in the normal mode, as the scan driver 120 sequentially selects the row lines one by one, the odd CDS circuit of the odd column and the even CDS circuit of the even column are respectively selected for each column of the corresponding column. The photoelectric conversion signals from the pixels of the low line can be sequentially output. On the other hand, in the binning mode, as the scan driver 120 sequentially selects a plurality of row lines (for example, two row lines), the even CDS circuit stops operation, and the odd CDS circuit of the odd CDS circuit is selected. Photoelectric conversion signals corresponding to the pixels of the plurality of row lines (for example, two row lines) and the plurality of row lines of the adjacent even columns (for example, through a multiplexer on the even column side). For example, the photoelectric conversion signals corresponding to the pixels of the 2 row lines may be summed by the charge sum method and sequentially output.

Hereinafter, the normal mode operation and the binning mode operation of the driving circuits of the image sensor 100 according to an exemplary embodiment of the present invention will be described in detail.

2 is a block diagram of a scan driver 120 according to an embodiment of the present invention. Referring to FIG. 2, the scan driver 120 according to an embodiment of the present invention may include D-flip flops D-FF, multiplexers MUX provided at an even side, and other logic circuits XOR, Buffers, etc.).

In the normal mode, as shown in FIG. 3, the binning control signal Ext_BIN is in a logic low state, and the D-flip flops D-FF operating by receiving the start pulse Ext_STT and the clock signal Ext_CLK are operated. Signals SEL_1 and RST_1 for sequentially selecting the row lines of the pixel array 110 one by one in the logic circuit operating according to the reset control signal Ext_RST and the selection control signal Ext_SEL as the sequentially activated signals are output. , SEL_2, RST_2, ..) At this time, the multiplexers MUX select and output the output of the D-flip flop on the even side according to the logic low state of the binning control signal Ext_BIN, so that the row lines are sequentially selected. , RST_1, SEL_2, RST_2, ...) are generated. Here, the selection signals SEL_1, SEL_2, .. are sequentially activated in synchronization with the selection control signal Ext_SEL, so that the detection signals of the photo diodes PD of the pixels of the row line are output. The reset signals RST_1, RST_2, .. are sequentially activated in synchronization with the reset control signal Ext_RST, thereby controlling to reset the output of the photodiodes of the pixels of the corresponding row line (see FIG. 6).

In the binning mode, as shown in FIG. 4, the binning control signal Ext_BIN is in a logic high state, and the D-flip flops D-FF operating by receiving the start pulse Ext_STT and the clock signal Ext_CLK are operated. As a result of sequentially outputting the active signal, a plurality of row lines (for example, two row lines) of the pixel array 110 may be removed from a logic circuit operating according to the reset control signal Ext_RST and the selection control signal Ext_SEL. Signals SEL_1, RST_1, SEL_2, RST_2, .. for sequential selection are output. At this time, the multiplexers MUX selects and outputs the output of the D-flip flop on the odd side according to the logic high state of the binning control signal Ext_BIN, thereby sequentially selecting the two row lines. (SEL_1, RST_1, SEL_2, RST_2, ...) are generated. That is, the selection signals SEL_1, SEL_2, .. to output the detection signals of the photo diodes PD of the corresponding row lines are pulses of the selection control signal Ext_SEL whenever the clock signal Ext_CLK is active. By width, the select signals for the two lines are active at the same time. In addition, the reset signals RST_1, RST_2, .. which reset the outputs of the photo diodes PD of the corresponding low line may be pulse widths of the selection control signal Ext_SEL at each active time of the clock signal Ext_CLK. The select signals for the two lines are active at the same time.

As a result, when the scan driver 120 uses the clock signal Ext_CLK having the same period as the normal mode in the binning mode, the scan driver 120 may scan the low line at twice the speed in the binning mode than in the normal mode.

5 is a block diagram of a column driver 130 according to an embodiment of the present invention. Referring to FIG. 5, the column driver 130 according to an exemplary embodiment of the present invention may include an odd CDS circuit 131 and an even reading of a photoelectric conversion signal from an odd column in a normal mode or a binning mode, respectively. (even) an even CDS circuit 132 for respectively reading the photoelectric conversion signal from the column in the normal mode or the binning mode, and for outputting the photoelectric conversion signals of the adjacent even column to the odd CDS circuit 131 in the beaming mode. A multiplexer 133. In addition, the column driver 130 includes AD converters for converting the analog signal from the CDS circuits 131 and 132 into a digital signal, and an output control circuit for latching and outputting the digital signal from the AD converters. (138).

For example, in the normal mode, as the scan driver 120 sequentially selects the row lines, the odd CDS circuit 131 and the even CDS circuit 132 each have a photoelectric conversion signal from the pixels of each row line of the corresponding column. Will output sequentially.

Further, in the binning mode, as the scan driver 120 sequentially selects a plurality of row lines (for example, two row lines), the even CDS circuit 132 stops operating, and the odd CDS circuit 131 Photoelectric conversion signals corresponding to pixels of a plurality of row lines (eg, 2 row lines) of the corresponding column and pixels of a plurality of row lines (eg, 2 row lines) of an adjacent even column The converted photoelectric conversion signals are summed by a charge summing method and sequentially output (see FIGS. 8 to 11).

In such a binning mode, the photoelectric conversion signals of adjacent even columns should be sent to the odd CDS circuit 131. For this purpose, the multiplexer 133 may transmit a plurality of even columns of the even column according to the logic high state of the binning control signal Ext_BIN. The photoelectric conversion signals corresponding to the pixels of the row line (for example, two row lines) are selected to be input to the neighboring odd CDS circuit 131 and output. In the normal mode, the binning control signal Ext_BIN of the logic low state is input to the multiplexer 133, thereby selecting the output photoelectric conversion signal to the even CDS circuit 132 of the corresponding column.

The analog signal from the CDS circuits 131 and 132 is converted into a digital signal by the AD converters, and then sequentially controlled by the write control signal Ext_write and the static random access (SRAM) of the output control circuit 138. And the like are stored in the latch circuit. In each mode, digital signals from the AD converters may be stored in corresponding positions in the latch circuit, such as SRAM.

Meanwhile, data stored in the SRAM and data stored in the SRAM at the same time may be output to the outside through a low voltage differential signaling (LVDS) method. For example, the D-flip flops D-FF of the output control circuit 138 that operate by receiving the start pulse Ext_STT and the clock signal Ext_CLK are sequentially active one by one or two depending on the normal or binning mode. As the signal is outputted, the signal may be read from the corresponding position of the SRAM in each mode and output to the outside in the LVDS method. For example, under the control of the binning control signal Ext_BIN, the multiplexer (MUX) and the NAND logic of the output control circuit 138 are separated from each position of the SRAM in which the signal of each column from the AD converters in the normal mode is stored. The SRAM is controlled to be read, and in the binning mode, the SRAM is controlled to be read only at the corresponding position (only at the odd position) of the stored SRAM.

6 shows a pixel array 110 and column output lines in accordance with one embodiment of the present invention.

Referring to FIG. 6, each pixel for outputting photoelectric conversion signals arranged in a two-dimensional array form to the pixel array 110 includes a photodiode PD and three MOSFET-type transistors T1, T2, and T3. Each column includes a plurality of column output lines (eg, two column output lines) for outputting photoelectric conversion signals corresponding to pixels of an odd row line and an even row line, respectively.

For example, referring to the timing diagram of FIG. 7, the first transistor T1 resets the output of the photodiode PD to the VDD voltage according to the reset signal φ _RX . The second transistor T2 generates a current corresponding to the output of the photodiode PD, and the third transistor T3 generates (output / even) the output of the second transistor T2 according to the selection signal φ _SEL . ) To the column output line. Here, the reset signal φ _RX represents any one of the reset signals RST1, RST2,... In FIG. 2, and the selection signal φ _SEL represents the selection signals SEL1, SEL2,. .) Any one.

In particular, as described above, a switch is included between two column output lines for outputting photoelectric conversion signals corresponding to pixels of an odd row line and an even row line for each column, and between the two column output lines. Is switched on / off according to the inversion signal Ext_Binb of the binning control signal Ext_Bin. That is, in the normal mode, since the inverted signal Ext_Binb of the binning control signal Ext_Bin is in a high logic state, the corresponding switch is turned on so that the two column output lines are connected (short). The output signal of the pixel (V _{col1 _ odd} / V _{col2 _ odd} ) and the pixel signal (V _{col1 _ even} / V _{col2 _ even} ) of the _even row line are alternately output, thereby eliminating an output error. In addition, in the binning mode, since the inverted signal Ext_Binb of the binning control signal Ext_Bin is in a low logic state, the corresponding switch is turned off to open the two column output lines. The signal V _{col1 _ odd} of the pixel of the line and the signal V _{col1 _ even} of the pixel of the even row line are output as separate column output lines.

8 is a CDS circuit diagram illustrating a normal mode operation according to an embodiment of the present invention.

In the normal mode, the odd CDS circuit 131 and the even CDS circuit 132 are each an amplifier AMP, a first capacitor C1, a second capacitor C2, and a selection signal φ _SEL , as shown in FIG. 8. The photoelectric conversion signal V _{col1 _ odd} / V _{col1 _} from the pixel by using a switch whose turn on / off is controlled in accordance with the switch, and a switch whose turn on / off is controlled in accordance with the sampling signal φ ₁ . _even ) (or V _{col2_odd} / V _{col2_even} ) is sampled and output.

The first capacitor C1 includes a first input terminal (eg, + input terminal) and a second input terminal (eg, − input terminal) of the amplifier AMP connected to the reference voltage V _ref . It is connected between the switches (switches under the control of the selection signal φ _SEL ). The second capacitor C2 is connected between the second input terminal (for example, − input terminal) of the amplifier AMP and the output terminal of the amplifier AMP. The second switch (a switch under the control of the sampling signal φ ₁ ) is connected in parallel with the second capacitor C2.

As shown in the timing diagram of FIG. 11, when the selection signal φ _SEL and the sampling signal φ ₁ are in a logic high state, the first switch (switch under the control of the selection signal φ _SEL ) and the second switch (sampling signal) (switch under control of φ ₁ ) is turned on, and the photoelectric conversion signal from the pixel can be sampled and output through the output terminal of the amplifier AMP. When only the selection signal φ _SEL is in a logic high state, the first switch (switch under control of the selection signal φ _SEL ) is turned on and the second switch (switch under control of the sampling signal φ ₁ ) is turned on. In this case, the pixel and the first capacitor C1 are reset. According to the correlated differential sampling (CDS) operation of repeating the reset and data sampling, the charges collected in the first capacitor C1 during the data sampling are relatively compared to the charges collected in the first capacitor C1 during the reset. The photoelectric conversion signal may be output.

9 is a diagram of the odd CDS circuit 131 for explaining the binning mode operation according to an embodiment of the present invention. 10 is a diagram of an even CDS circuit 132 for explaining a binning mode operation according to an embodiment of the present invention.

In the binning mode, the odd CDS circuit 131 includes, as shown in FIG. 9, an amplifier AMP, a plurality of switches whose turn on / off is controlled according to the second selection signal φ _{SEL _ bin} , A plurality of pixels (eg, 2) may be used by using a switch whose turn-on / off is controlled according to a plurality of capacitors C1, a second capacitor C2, and a sampling signal φ ₁ respectively connected to the plurality of switches. The photoelectric conversion signals V _{col1 _ odd} , V _{col1 _ even} , V _{col2 _ odd} and V _{col2 _ even} from the * 2 pixels are sampled and output by the charge summing method.

Each of the plurality of capacitors C1 includes a plurality of capacitors C1 and a second input terminal (eg, − input terminal) of the amplifier AMP having a first input terminal (eg, + input terminal) connected to the reference voltage V _ref . Are connected between each of the switches (switches whose turn on / off is controlled in accordance with the second selection signal φ _{SEL _ bin} ). The second capacitor C2 is connected between the second input terminal (for example, − input terminal) of the amplifier AMP and the output terminal of the amplifier AMP. The second switch (a switch under the control of the sampling signal φ ₁ ) is connected in parallel with the second capacitor C2.

In the binning mode, the second selection signal φ _{SEL _ bin} is a logical AND signal of the selection signal φ _SEL in the normal mode and the binning control signal Ext_Bin, and the binning control signal Ext_Bin in the binning mode. ) Is a logic high state, in which case the second selection signal φ _{SEL_bin} is a signal having a logic state in the same manner as the selection signal φ _SEL in the normal mode.

In consideration of this, referring to the timing diagram of FIG. 11, when the second selection signal φ _{SEL _ bin} and the sampling signal φ ₁ are in a logic high state, a plurality of switches (the second selection signal φ _{SEL _ bin} ) And the second switch (the switch under the control of the sampling signal φ ₁ ) are turned on, respectively, through the output terminal of the amplifier AMP. The photoelectric conversion signals V _{col1 _ odd} , V _{col1 _ even} , V _{col2 _ odd} , and V _{col2_even} from the pixels (eg, 2 * 2 pixels) may be sampled and output by a charge summing method. That is, two photoelectric conversion signals V _{col2 _ odd} and V _{col2 _ even} in two row lines of the adjacent even column received through the multiplexer 133 of FIG. 5 and two photoelectric conversion signals of the corresponding odd column. (V _{col1 _ odd} , V _{col1_even} ) are added, sampled, and output in a plurality of capacitors C1 in a charge summing manner. When only the second selection signal φ _{SEL _ bin} is in a logic high state, only a plurality of switches (switches whose turn on / off is controlled according to the second selection signal φ _{SEL _ bin} ) is turned on. The second switch (the switch under the control of the sampling signal φ ₁ ) is turned off, and at this time, the pixels and the plurality of capacitors C1 are reset. The reset and data sampling are performed once for each line selection period (Row Time) of the scan driver 120.

As shown in FIG. 10, in the binning mode, the even CDS circuit 132 is turned on / off according to the amplifier AMP, the first capacitor C1, and the third select signal φ _{SEL _ binb} . The first switch, the second capacitor (C2) is controlled, and operates according to the switch is turned on / off according to the sampling signal (φ ₁ ). At this time, the even CDS circuit 132 in the binning mode operates similarly to FIG. 8, but since the third select signal φ _{SEL _ binb} is kept low, sampling the photoelectric conversion signal from V _{col2 _ odd} . The operation will stop. At this time, the other switches (dummy switches connected to V _{col1 _ odd} , V _{col1 _ even} , V _{col2 _ even} ) that receive the ground voltage VSS instead of the third selection signal φ _{SEL _ binb} may also be used. Turn off to stop the operation.

In the binning mode, the third selection signal φ _{SEL _ binb} is a logical AND signal between the selection signal φ _SEL in the normal mode and the inversion signal Ext_Binb of the binning control signal Ext_Bin. In the mode, since the inverted signal Ext_Binb of the binning control signal Ext_Bin is in a logic low state, the third selection signal φ _{SEL _ binb} remains low. In the normal mode, the third selection signal φ _{SEL _ binb} becomes a signal having a logic state in the same manner as the selection signal φ _SEL .

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is an overall configuration diagram of an image sensor according to an embodiment of the present invention.

2 is a block diagram of a scan driver according to an embodiment of the present invention.

3 is a timing diagram illustrating a normal mode operation of a scan driver according to an embodiment of the present invention.

4 is a timing diagram illustrating a binning mode operation of a scan driver according to an embodiment of the present invention.

5 is a block diagram of a column driver according to an embodiment of the present invention.

6 shows a pixel array and column output lines in accordance with one embodiment of the present invention.

7 is a timing diagram illustrating signal reading of a pixel according to an exemplary embodiment of the present invention.

8 is a CDS circuit diagram illustrating a normal mode operation according to an embodiment of the present invention.

9 is an odd CDS circuit diagram illustrating a binning mode operation according to an embodiment of the present invention.

10 is an even CDS circuit diagram for describing a binning mode operation according to an exemplary embodiment of the present invention.

11 is a timing diagram illustrating the operation of a CDS circuit according to an embodiment of the present invention.

Claims (12)

A scan driver for selecting a row line and a column driver for reading a photoelectric conversion signal from pixels of the row line selected by the scan driver; The column driver may be configured to read the photoelectric conversion signal from the odd column in the normal mode or the binning mode, respectively, according to the normal mode or the binning mode operation of the scan driver. An even CDS circuit for reading the photoelectric conversion signal in a normal mode or a binning mode, respectively, In the normal mode, as the scan driver sequentially selects the row lines, the odd CDS circuit and the even CDS circuit sequentially output the photoelectric conversion signals from the pixels of each row line of the corresponding column, In the binning mode, as the scan driver sequentially selects a plurality of row lines, the even CDS circuit stops operating, and the odd CDS circuit is configured to photoelectric corresponding to pixels of the plurality of row lines of the corresponding column. And the photoelectric conversion signals corresponding to the pixels of the plurality of row lines of the adjacent even column are sequentially added to each other by a charge summing method. The method of claim 1, Outputting the photoelectric conversion signal to an even CDS circuit of a corresponding column in the normal mode, A multiplexer for inputting photoelectric conversion signals corresponding to the pixels of the plurality of row lines of the even column in the binning mode to a neighboring odd CDS circuit in the binning mode. The driving circuit of the image sensor comprising a. The method of claim 1, 2 column output lines for outputting photoelectric conversion signals corresponding to pixels of odd row line and even row line for each column The drive circuit of the image sensor comprising a. The method of claim 3, wherein And a switch coupled between the two column output lines, the switch turned on in the normal mode and off in the binning mode. The method of claim 1, In the binning mode, the number of rows of the plurality of row lines selected by the scan driver is two. The method of claim 1, Each pixel for outputting the photoelectric conversion signal, A first transistor for resetting the output of the photodiode according to the reset signal; A second transistor for generating a current corresponding to the output of the photodiode; And A third transistor for outputting the output of the second transistor to a column output line according to a selection signal It is a 3-TR structure consisting of a drive circuit of the image sensor. The method of claim 1, In the normal mode, the odd CDS circuit and the even CDS circuit, By using a first capacitor connected between a second input terminal of the amplifier and a first switch of which the first input terminal is connected to the reference voltage, and a second capacitor connected between the second input terminal and the output terminal of the amplifier, And a photoelectric conversion signal from the pixel is output through the output terminal of the amplifier when the first switch and the second switch connected in parallel with the second capacitor are turned on. 8. The driving circuit of claim 7, wherein the pixel and the first capacitor are reset when the first switch is turned on and the second switch is turned off. The method of claim 1, In the binning mode, the odd CDS circuit is, Each capacitor connected between each of the plurality of switches and a second input terminal of the amplifier having a first input terminal coupled to a reference voltage; By using the second capacitor connected between the second input terminal and the output terminal of the amplifier, when the plurality of switches and the second switch connected in parallel with the second capacitor is turned on, through the output terminal of the amplifier, And driving the photoelectric conversion signals of the corresponding odd column and the adjacent even column corresponding to the pixels of the plurality of row lines by charge summation. The driving circuit of claim 9, wherein the pixels and the capacitor are reset when the plurality of switches are turned on and the second switch is turned off. The method of claim 1, Each pixel for outputting the photoelectric conversion signal, A drive circuit for an image sensor, characterized in that it generates an electrical signal for radiation including incident X-rays. A method of driving an image sensor using a column driver that reads a photoelectric conversion signal from pixels of a line, The column driver may be configured to read the photoelectric conversion signal from the odd column in the normal mode or the binning mode, respectively, according to the normal mode or the binning mode operation of the scan driver. By using Even CDS circuit which reads photoelectric conversion signal in normal mode or binning mode, In the normal mode, sequentially outputting photoelectric conversion signals from pixels of each row line of the corresponding column in the odd CDS circuit and the even CDS circuit as the scan driver sequentially selects the row lines; And In the binning mode, as the scan driver sequentially selects a plurality of row lines, the even CDS circuit stops operating, and the photoelectric corresponding to the pixels of the plurality of row lines of the corresponding column in the odd CDS circuit is stopped. Sequentially converting the converted signals and the photoelectric conversion signals corresponding to the pixels of the plurality of row lines of the adjacent even column by a charge sum method to sequentially output the converted signals. Method of driving an image sensor comprising a.

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