KR20110058325A - Silicon carbide based semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A silicon carbide based semiconductor device and manufacturing method thereof are provided to use aluminium oxide with a high k value and to use silicon nitride as a middle layer, thereby increasing a breakdown field and reliability by having a stable structure against high temperature processing. CONSTITUTION: A silicon dioxide layer(12) is nitrified on a silicon carbide substrate(11). An aluminium oxide layer(13) is formed on the silicon dioxide layer. A silicon nitride layer is formed between the silicon dioxide layer and the aluminium oxide layer. The silicon dioxide layer and the aluminium oxide layer are formed on the silicon carbide substrate. The silicon carbide substrate is annealed. The annealing is rapid thermal annealing.

Description

Silicon carbide based semiconductor device and manufacturing method {SILICON CARBIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method, and more particularly, to a silicon carbide (SiC) -based semiconductor device and a manufacturing method excellent in high voltage and high output characteristics.

 As the development of the information society accelerates, the current silicon-based semiconductor technology cannot sufficiently support the energy, industrial electronics, telecommunications, optoelectronic or extreme electronic fields, and silicon is showing its physical limitations. Therefore, in order to solve the problems of silicon-based semiconductor technology, research on new semiconductor materials having a wide band-gap has been actively conducted. Among other materials, silicon carbide (SiC) is actively developing it as a next generation power device suitable for high voltage, high power and high frequency applications.

Silicon carbide is produced by the strong covalent bond between carbon and silicon, Group 4 elements, and has been used for a long time as an abrasive material and a cutting material because of its excellent mechanical properties. In addition, Si and GaAs have excellent electrical properties such as high breakdown voltage (5 × 10 ⁶ V / cm), high thermal conductivity (4.9 W / cm · K) and high saturation electron drift velocity. It has been applied as a high temperature, high voltage electronic device that is difficult to implement.

Silicon carbide-based semiconductor devices have a 10-fold permissible electric field strength and a four-times operating temperature, compared to general silicon-based semiconductor devices, so that they can be operated at high power and high temperature. It can be lowered to about 3, which greatly saves energy. Therefore, it is widely applied to power control in power generation and transmission and distribution fields as well as high speed trains, power controllers of electric vehicles, and high frequency amplifiers of mobile communication base stations, thereby reducing the size of these operating systems and reducing power loss. Currently, silicon carbide has Field Effect Transistors (FETs), Light Emitting Diodes (LEDs), Pressure Sensors, Hetero-junction Bipolar Transistors (HBTs) and Schottky Barrier Diodes. Application to diodes and the like has been studied.

In addition, one of the biggest advantages of silicon carbide is that it can form a natural oxide film such as silicon dioxide (SiO ₂ ), which is a metal-oxide-semiconductor field effect transistor (MOSFET) capable of fast switching. ) Is likely to apply. However, silicon dioxide based silicon dioxide gates have problems of high interface-trap density and insufficient stability between silicon dioxide and silicon carbide under high temperature and high electric fields.

Therefore, research has been conducted to replace the gate insulator, and an insulator such as aluminum oxide (Al ₂ O ₃ ) having a large dielectric constant (or high-k dielectrics) is an alternative gate insulator. Proposed. However, even when aluminum oxide is replaced with an insulator, a large leakage current flows due to a small band offset between the conduction band and the valence band between the oxide and silicon carbide.

An object of the present invention to solve the above problems is to insert a relatively thin thermal-nitrided silicon dioxide buffer layer between aluminum oxide and silicon carbide to increase the difference between the conduction band and the valence band. This improves the electrical properties of the aluminum oxide dielectric monolayer.

In addition, another object of the present invention is to use silicon nitride as an intermediate layer to maintain a stable structure for high temperature heat treatment, thereby reducing the interface trap density, increasing the breakdown field and reliability, suitable for high voltage, high power and high frequency applications The present invention provides a semiconductor device.

A silicon carbide-based semiconductor device according to an embodiment of the present invention includes a silicon carbide substrate, a silicon nitride treated silicon dioxide layer formed on the silicon carbide substrate, and an aluminum oxide layer which is an insulator formed on the silicon dioxide layer. The silicon carbide substrate on which the silicon dioxide layer and the aluminum oxide layer are formed is annealed. The silicon nitride layer may further include a silicon nitride layer formed between the silicon dioxide layer and the aluminum oxide layer. The silicon dioxide layer may be formed to a thickness of 20 to 25nm, the silicon nitride layer may be formed to a thickness of 10nm.

In the silicon carbide-based semiconductor device manufacturing method according to an embodiment of the present invention, forming a nitrided silicon dioxide layer on a silicon carbide substrate, forming an aluminum oxide layer as an insulator on the silicon dioxide layer, And annealing the silicon carbide substrate on which the silicon dioxide layer and the aluminum oxide layer are formed. The method may further include forming a silicon nitride layer on the silicon dioxide layer, wherein the aluminum oxide layer may be formed on the silicon nitride layer. The annealing may be RTA treated at 1000 ° C. for 2 minutes. In addition, the silicon dioxide layer may be formed with a thickness of 20 to 25nm, the silicon nitride layer may be formed with a thickness of 10nm, the step of forming the silicon nitride layer is the silicon nitride layer by an inductively coupled plasma chemical vapor deposition method Can be formed.

According to the present invention, a silicon carbide-based semiconductor device and a manufacturing method use aluminum oxide having a high κ value as an oxide film and silicon nitride as an intermediate layer, thereby maintaining a stable structure for high temperature heat treatment, thereby reducing the interface trap density. And increase the breakdown field and reliability.

In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1 is a cross-sectional view showing a cross section of a silicon carbide semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1, a silicon carbide-based semiconductor device according to an embodiment of the present invention may be a silicon carbide (SiC) substrate 11, a nitrided silicon dioxide layer 12 (SiO ₂ ), and an aluminum oxide layer 13. , Al ₂ O ₃ ). In addition, the silicon carbide substrate 11 on which the silicon dioxide layer 12 and the aluminum oxide layer 13 are formed is annealed. According to an embodiment of the present invention, the annealing is performed for RTA (Rapid Thermal Annealing) at 1000 ° C. for 2 minutes. The RTA can be carried out in a nitrogen atmosphere.

The silicon carbide (SiC) constituting the silicon carbide substrate 11 has been reported many crystal polymorphisms according to the lamination order of the closest packed surface, the only silicon carbide having a zincblend structure having a cubic crystal phase beta This is called silicon carbide (β-SiC) and the rest of the polymorphism is called alpha silicon carbide (α-SiC).

The substrate 11 is an N-type, 8 ° off, and a wafer made of a 10 μm thick epilayer doped with nitrogen (1-4) × 10 ¹⁶ cm ⁻³ is used. Can be. As the material of the substrate 11, 4H-SiC, 6H-SiC, 3C-SiC, Si, GaN and GaAs may be used. In one embodiment of the present invention, 4H silicon carbide having excellent electron mobility and the like may be used. It is used as the board | substrate 11.

The silicon dioxide layer 12 is formed on the silicon carbide substrate 11. In order to increase the difference between the conduction band and the valence band, an aluminum oxide dielectric single layer is inserted by inserting a relatively thin thermal-nitrided silicon dioxide layer between the silicon carbide layer 11 and the aluminum oxide layer 13. It is possible to improve the electrical properties of the layer.

The silicon dioxide layer 12 is a step of immersing the substrate in hydrofluoric acid (HF) for 2 minutes to clean the wafer, and then the silicon dioxide layer treated by nitriding in a 10% nitrous oxide (N ₂ O) atmosphere at 1175 ° C. It can be grown on the wafer. According to an embodiment of the present invention, the silicon dioxide layer 12 may be grown to a thickness of 20 to 25 nm. In silicon carbide-based semiconductor devices using nitrided silicon dioxide, nitrogen atoms are bonded to silicon and carbon at the interface to suppress activation of traps. In addition, the nitrogen at the interface serves to reduce the amount of carbon at the interface by vaporizing by bonding with carbon.

The aluminum oxide layer 13 is formed on the silicon dioxide layer 12. The aluminum oxide layer 13 may be deposited by an atomic layer deposition (ALD) system, and according to an embodiment of the present invention, the aluminum oxide layer 13 may be deposited to 15 nm. The ALD process can be heated at 370 ° C. under ultraviolet light, using TriMethyl-Aluminium (TMA) and water as a precursor.

The aluminum oxide layer 13 has a large dielectric constant, or high-k dielectrics value. Silicon carbide gates based on silicon carbide have a high interfacial-trap density between silicon dioxide and silicon carbide under high temperature, high electric fields, and have the problem of being unstable. Therefore, a dielectric such as aluminum oxide having a large dielectric constant is used as the oxide.

2 is a cross-sectional view showing a cross section of a silicon carbide semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2, a silicon carbide-based semiconductor device according to an embodiment of the present invention may be a silicon carbide (SiC) substrate 21, a nitrided silicon dioxide layer 22 (SiO ₂ ), a silicon nitride layer 23, SiN) and an aluminum oxide layer 24 (Al ₂ O ₃ ). In addition, the silicon carbide substrate 21 on which the silicon dioxide layer 22, the silicon nitride layer 23, and the aluminum oxide layer 24 are formed is annealed. According to an embodiment of the present invention, the annealing is performed for RTA (Rapid Thermal Annealing) at 1000 ° C. for 2 minutes. The RTA can be carried out in a nitrogen atmosphere.

The substrate 21 is an N-type wafer, which is 8 ° off, and is made of a 10 μm thick epilayer doped with nitrogen (1-4) × 10 ¹⁶ cm ⁻³ . ) Can be used. As the material of the substrate 21, 4H-SiC, 6H-SiC, 3C-SiC, Si, GaN and GaAs may be used. In one embodiment of the present invention, 4H silicon carbide having excellent electron mobility and the like may be used as a substrate. Use as (21).

The silicon dioxide layer 22 is formed on the silicon carbide substrate 21. In order to increase the difference between the conduction band and the valence band, an aluminum oxide dielectric single layer is inserted by inserting a relatively thin thermal-nitrided silicon dioxide buffer layer between the silicon carbide layer 21 and the aluminum oxide layer 24. It is possible to improve the electrical properties of the layer.

The silicon dioxide layer 22 is a process of immersing the substrate in hydrofluoric acid (HF) for 2 minutes to clean the wafer, and then the silicon dioxide layer subjected to nitriding treatment in a 10% nitrous oxide (N ₂ O) atmosphere at 1175 ° C. It can be grown on the wafer. According to one embodiment of the present invention, the silicon dioxide layer 22 may be grown to a thickness of 20 to 25 nm. In silicon carbide-based semiconductor devices using nitrided silicon dioxide, nitrogen atoms are bonded to silicon and carbon at the interface to suppress activation of traps. In addition, the nitrogen at the interface serves to reduce the amount of carbon at the interface by vaporizing by bonding with carbon. Therefore, in order to obtain the effect of the nitrogen using nitrided silicon dioxide, the reactions must be continuously made even after a heat treatment process such as annealing.

The silicon nitride layer 23 is formed on the silicon dioxide layer 22. The silicon nitride layer 23 may be deposited by Inductively Coupled Plasma (ICP) Chemical Vapor Deposition (CVD), which is evaluated by a technology matured in a high-power and / or high-frequency device manufacturing process. According to an embodiment of the present invention, the silicon nitride layer 23 may be deposited to a thickness of 10 nm. Silicon nitride has good thermal stability and a moderately high -k value (up to 5-7).

The oxide to be deposited after the silicon nitride layer 23 is formed must undergo complex heat treatment and processes to use a high quality stacked gate dielectric as part of a silicon carbide MOS based device. One such process is the Rapid Thermal Annealing (RTA) process, which is used in manufacturing processes to form ohmic contacts of small resistance on silicon carbide. At present, a silicon carbide MOS-based device fabrication process requires a post annealing process at high temperature (1000 ° C., 2 minutes).

During the post annealing process, high-k films are affected both structurally and electrically, especially in the interfacial layer. This effect is observed in silicon-based high-k gate systems such as aluminum oxide, hafnium oxide (HfO ₂ ). In order to minimize structural changes during this heat treatment process, a reaction barrier layer (RBL) may be inserted between the aluminum oxide layer 24 and the silicon dioxide layer 22. According to one embodiment of the present invention, the reaction barrier layer may be a silicon nitride layer.

The aluminum oxide layer 24 is formed on the silicon nitride layer 23. The aluminum oxide layer 24 may be deposited by an atomic layer deposition (ALD) system, and according to an embodiment of the present invention, the aluminum oxide layer 24 may be deposited to 15 nm. The ALD process can be heated at 370 ° C. under ultraviolet light, using TriMethyl-Aluminium (TMA) and water as a precursor.

The aluminum oxide layer 24 has a large dielectric constant, or high-k dielectrics value. Silicon carbide gates based on silicon carbide have a high interfacial-trap density between silicon dioxide and silicon carbide under high temperature, high electric fields, and have the problem of being unstable. Therefore, a dielectric such as aluminum oxide having a large dielectric constant is used as the oxide.

3 is a flowchart illustrating a method of manufacturing a silicon carbide semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3, in another method of manufacturing a silicon carbide-based semiconductor device, a method of forming a nitrided silicon dioxide layer on a silicon carbide substrate (S31) may be performed on the silicon dioxide layer. Forming an aluminum oxide layer as an insulator (S32), and annealing the silicon carbide substrate on which the silicon dioxide layer and the aluminum oxide layer are formed (S33).

In the step (S31) of forming a nitrided silicon dioxide layer on the silicon carbide substrate, the silicon carbide substrate is N-type, 8 ° off, and nitrogen is (1-4) x 10 ¹⁶ cm ^-3 . Wafers of doped 10 μm thick epilayers may be used. The silicon carbide substrate may be made of 4H-SiC, 6H-SiC, 3C-SiC, Si, GaN, and GaAs. In an embodiment of the present invention, 4H silicon carbide having excellent electron mobility and the like may be used as the substrate. use.

The silicon dioxide layer is formed on the silicon carbide substrate. To increase the difference between the conduction band and the valence band, by inserting a relatively thin thermal-nitrided silicon dioxide layer between the silicon carbide layer and the aluminum oxide layer, the electrical properties of the aluminum oxide dielectric monolayer are improved. can do.

The silicon dioxide layer is a step of immersing the substrate in hydrofluoric acid (HF) for 2 minutes to wash the wafer, the silicon dioxide layer treated with a nitrided silicon dioxide in a 10% nitrous oxide (N ₂ O) atmosphere at 1175 ℃ on the wafer Can grow on. According to an embodiment of the present invention, the silicon dioxide layer may be grown to a thickness of 20 to 25 nm. In silicon carbide-based semiconductor devices using nitrided silicon dioxide, nitrogen atoms are bonded to silicon and carbon at the interface to suppress activation of traps. In addition, the nitrogen at the interface serves to reduce the amount of carbon at the interface by vaporizing by bonding with carbon.

In the step (S32) of forming an aluminum oxide layer as an insulator on the silicon dioxide layer, the aluminum oxide layer is formed on the silicon dioxide layer. The aluminum oxide layer may be deposited by an atomic layer deposition (ALD) system, and according to an embodiment of the present invention, the aluminum oxide layer may be deposited up to 15 nm. The ALD process can be heated at 370 ° C. under ultraviolet light, using TriMethyl-Aluminium (TMA) and water as a precursor.

The aluminum oxide layer has a large dielectric constant, or high-k dielectrics value. Silicon carbide gates based on silicon carbide have a high interfacial-trap density between silicon dioxide and silicon carbide under high temperature, high electric fields, and have the problem of being unstable. Therefore, a dielectric such as aluminum oxide having a large dielectric constant is used as the oxide.

In the step (S33) of annealing the silicon carbide substrate on which the silicon dioxide layer and the aluminum oxide layer are formed, Rapid Thermal Annealing (RTA) is performed at 1000 ° C. for 2 minutes. The RTA can be carried out in a nitrogen atmosphere.

4 is a flowchart illustrating a method of manufacturing a silicon carbide semiconductor device according to an embodiment of the present invention.

As shown in FIG. 4, in another method of manufacturing a silicon carbide-based semiconductor device, a method of forming a nitrided silicon dioxide layer on a silicon carbide substrate (S41) is performed on the silicon dioxide layer. Forming a silicon nitride layer (S42), forming an aluminum oxide layer as an insulator on the silicon nitride layer (S43), and annealing the silicon carbide substrate on which the silicon dioxide layer, the silicon nitride layer, and the aluminum oxide layer are formed. A step S44 is included.

In the step (S41) of forming a nitrided silicon dioxide layer on the silicon carbide substrate, the silicon carbide substrate is N-type, 8 ° off, and nitrogen is (1-4) x 10 ¹⁶ cm ^-3 . Wafers of doped 10 μm thick epilayers may be used. The silicon carbide substrate may be made of 4H-SiC, 6H-SiC, 3C-SiC, Si, GaN, and GaAs. In an embodiment of the present invention, 4H silicon carbide having excellent electron mobility and the like may be used as the substrate. use.

The silicon dioxide layer is formed on the silicon carbide substrate. To increase the difference between the conduction band and the valence band, by inserting a relatively thin thermal-nitrided silicon dioxide layer between the silicon carbide layer and the aluminum oxide layer, the electrical properties of the aluminum oxide dielectric monolayer are improved. can do.

The silicon dioxide layer is a step of immersing the substrate in hydrofluoric acid (HF) for 2 minutes to wash the wafer, the silicon dioxide layer treated with a nitrided silicon dioxide in a 10% nitrous oxide (N ₂ O) atmosphere at 1175 ℃ on the wafer Can grow on. According to an embodiment of the present invention, the silicon dioxide layer may be grown to a thickness of 20 to 25 nm. In silicon carbide-based semiconductor devices using nitrided silicon dioxide, nitrogen atoms are bonded to silicon and carbon at the interface to suppress activation of traps. In addition, the nitrogen at the interface serves to reduce the amount of carbon at the interface by vaporizing by bonding with carbon. Therefore, in order to obtain the effect of the nitrogen using nitrided silicon dioxide, it is necessary to allow the reactions to occur continuously even after heat treatment such as annealing.

In the step of forming a silicon nitride layer on the silicon dioxide layer (S42), the silicon nitride layer is formed on the silicon dioxide layer. The silicon nitride layer may be deposited by Inductively Coupled Plasma (ICP) Chemical Vapor Deposition (CVD), which is evaluated by a technology matured in a high power and / or high frequency device manufacturing process. According to an embodiment of the present invention, the silicon nitride layer may be deposited to a thickness of 10 nm. Silicon nitride has good thermal stability and a moderately high -k value (up to 5-7).

The oxide to be deposited after the silicon nitride layer formation has to undergo complex heat treatment and processes to use a high quality stacked gate dielectric as part of a silicon carbide MOS based device. One such process is the Rapid Thermal Annealing (RTA) process, which is used in manufacturing processes to form ohmic contacts of small resistance on silicon carbide. At present, a silicon carbide MOS-based device fabrication process requires a post annealing process at high temperature (1000 ° C., 2 minutes).

During the post annealing process, high-k films are affected both structurally and electrically, especially in the interfacial layer. This effect is observed in silicon-based high-k gate systems such as aluminum oxide, hafnium oxide (HfO ₂ ). To minimize structural changes during this heat treatment process, a reaction barrier layer (RBL) may be interposed between the aluminum oxide layer 24 and the silicon dioxide layer. According to an embodiment of the present invention, the reaction barrier layer may be a silicon nitride layer.

In the step (S43) of forming an aluminum oxide layer as an insulator on the silicon nitride layer, the aluminum oxide layer is formed on the silicon dioxide layer. The aluminum oxide layer may be deposited by an atomic layer deposition (ALD) system, and according to an embodiment of the present invention, the aluminum oxide layer may be deposited up to 15 nm. The ALD process can be heated at 370 ° C. under ultraviolet light, using TriMethyl-Aluminium (TMA) and water as a precursor.

The aluminum oxide layer has a large dielectric constant, or high-k dielectrics value. Silicon carbide gates based on silicon carbide have a high interfacial-trap density between silicon dioxide and silicon carbide under high temperature, high electric fields, and have the problem of being unstable. Therefore, a dielectric such as aluminum oxide having a large dielectric constant is used as the oxide.

In annealing the silicon carbide substrate on which the silicon dioxide layer, the silicon nitride layer, and the aluminum oxide layer are formed (S44), according to an embodiment of the present invention, Rapid Thermal Annealing (RTA) is performed at 1000 ° C. for 2 minutes. do. The RTA can be carried out in a nitrogen atmosphere.

5 to 9 and Table 1 show thermal stability of structural and electrical performance of aluminum oxide / silicon nitride-RBL / silicon dioxide stacked gate dielectrics subjected to RTA treatment at 1000 ° C. for 2 minutes.

For comparative experiments, a sample without silicon nitride-RBL is inserted into the ALD system. After growing aluminum oxide, one set of samples is subjected to RTA in a nitrogen atmosphere at 1000 ° C. for 2 minutes, and the other samples are not RTA treated.

Electrical parameters such as flat band voltage shift (ΔV _FB ) and interface trap density (D _it ) are used to evaluate the performance of this gate after post annealing treatment.

To evaluate the interface state between the aluminum oxide layer and silicon carbide, a gate electrode is formed on the upper surface of the aluminum oxide layer using nickel (work function = 4.6 eV), and a lower electrode is formed on the back surface of the silicon carbide substrate using aluminum. do. By forming the gate electrode and the lower electrode, a metal oxide semiconductor capacitor (MOS) was fabricated, and electrical characteristics thereof were evaluated.

The area A of the gate electrode obtained by the said process is 1.3 * 10 <^-3> cm <^-2> . D _it can be measured by hi-lo CV (Capacitance-Voltage, CV) method. The measurement can be made with a computer controlled Keithely 590 CV analyzer / 595 Quasistatic CV meter, which has a DC sweep rate of 0.1 V / s at room temperature and a superimposed 1 MHz. It operates with a small amplitude AC voltage of 15㎷. The gate current I _g of the MOS capacitor as a function of the forward gate-voltage sweep V _g (ramping rate = 0.3 V / s) was measured using a semiconductor parameter analyzer (HP-4156).

I _g -V _g measurements are converted into current density J, and electric field E. The E value is calculated by E = (V _G -V _FB ) / T _OX , where T _OX represents the physical thickness of the oxide. The yield electric field of the dielectric, E _B, is defined as the electric field inducing J = 10 ⁻⁶ A / cm 2. In this way, a time zero dielectric breakdown (TZDB) reliability test was performed with 30 capacitors per sample.

In order to confirm the physical thickness and morphology of the oxide, a high-resolution transmission electron microscope (HR-TEM) such as FEI's F30 model was used. The composition of the laminated films was analyzed using an Auger Electron Spectroscope (AES) such as Perkin-Elmer 660.

FIG. 5 is a diagram illustrating a capacity-voltage (C-V) relationship according to whether annealing is performed at high frequency (1 MHz) and whether silicon nitride-RBL is inserted.

In order to determine the flat band voltage shift (ΔV _FB ) from the high frequency CV curve measured in FIG. 5, the V _FB of the samples was extrapolated from the 1 / C ² -V _g plot. The ideal flatband voltages for the samples are up to 0.72V and their respective values are shown in Table 1.

As shown in Table 1, the calculated ΔV _FB for samples that were as-deposited without the insertion of silicon nitride-RBL The value is one order lower than when silicon nitride-RBL is inserted. Compared with the case of the insertion of silicon nitride-RBL for the case without heat treatment, the laminated dielectric with the insertion of silicon nitride-RBL has a larger negative ΔV _FB Value, indicating a greater amount of effective charge. This difference is mainly influenced by the use of the silicon nitride layer deposited by ICP-CVD in the present invention, where the silicon nitride layer deposited is known to accumulate a positive charge. In Figure 1 and Table 1, in the case of the annealed (annealed), if it is not inserted into the silicon nitride -RBL is of larger amount compared with the case where the inserted ΔV _FB You can see that it has a value. That is, when silicon nitride-RBL is inserted between aluminum oxide and silicon dioxide, ΔV _FB The value is a smaller positive value.

Figure 6 is a chart showing the distribution of D _it as a function of the energy trapped under the E _C (conduction bandedge) of the dielectric.

As shown in FIG. 6, the size of D _it for as-deposited samples does not vary depending on whether silicon nitride-RBL is inserted. However, the D _it for the annealed sample is higher when the silicon nitride-RBL is not inserted than when it is inserted. This indicates that for samples without silicon nitride-RBL, negative charges are likely to be generated at the interface and / or bulk dielectric. It is difficult to conclude whether these effective charges in the system are actually affected by negatively charged defect states, or only by the charge compensation effect. However, it can be concluded that the resulting negative charge comes from charges located at the interface and / or bulk oxides. This conclusion is based on a broad hysteresis curve, large negative effective oxide charge (Q _eff ) and large D _it when CV measurements are made with forward and reverse bias. All negative Q _eff and D _it can be significantly reduced during the RTA process by inserting silicon nitride-RBL between aluminum oxide and silicon dioxide.

FIG. 7 is a graph showing the relationship between J-E, that is, an electric field (E) and a current density (J), depending on whether annealing and silicon nitride-RBL are inserted.

As shown in FIG. 7 (a), the shapes of JE curves for stacked dielectrics of annealed aluminum oxide depending on whether silicon nitride-RBL is inserted are entirely different. This indicates that the mechanism of current transfer through the oxide is different in different samples. Because without the insert of the silicon nitride -RBL D _it of the annealed samples is greater than D _it of the other samples, it can be trapped and / or the tunneling of the inserted electronic, and this point is a low dielectric breakdown electric field of the JE E curve _B ( breakdown field). When the electric field corresponding to J = 10 ⁻⁶ A / cm 2 is set to the breakdown electric field E _B , the E _B increases considerably by inserting silicon nitride-RBL. Similar results can be seen in the TZBD reliability statistics of FIG. 7B.

8 is a diagram illustrating HR-TEM images of samples according to whether silicon nitride-RBL is inserted and annealed.

As shown in Figure 8, when the silicon nitride-RBL is inserted, there is no difference between the samples according to the annealing (Fig. 8 (a) and 8 (b)). This indicates that during the RTA process, silicon nitride-RBL inhibits the mixing of aluminum oxide and silicon dioxide.

In FIG. 8 (c), partial crystallization at the top of the oxide and at the aluminum oxide-silicon dioxide interface can be confirmed for the sample without silicon nitride-RBL inserted and as-deposited.

In FIG. 8 (d), partial crystallization after the RTA process extends near the silicon carbide-silicon dioxide interface. These results suggest that partial crystallization may consist of aluminum clusters, which are formed near the aluminum oxide-silicon dioxide interface by diffusion of aluminum towards the silicon carbide-silicon dioxide interface during the RTA process.

The formed aluminum cluster is thermally diffused into the nitrided silicon dioxide layer after the heat treatment process such as annealing, and reaches the interface between the nitrided silicon dioxide layer and the silicon carbide. This diffused aluminum cluster prevents nitrogen from binding to silicon and carbon, preventing the trap from being activated and hindering the role of reducing the amount of carbon at the interface.

In silicon systems, partially crystallized aluminum clusters can be formed by two mechanisms. The first is formed from the direct interaction between aluminum and silicon at high temperatures in an oxygen-deficient atmosphere. The second is that partially crystallized in the aluminum cluster by the interaction between the available electrons in the Al ^{3 +} and the substrate formed from trimethylaluminum in ALD source.

Two in the second mechanism, by inhibiting the direct interaction between the electrons from the substrate using an intermediate layer such as Al ^{+ 3,} and the silicon dioxide it is possible to prevent the formation of clusters of aluminum. Therefore, partially crystallized aluminum clusters can be formed using an external ALD process to which initial surface conditions including impurities such as carbon, hydrogen, oxygen and nitrogen atoms are applied during the sample delivery and / or deposition process. By inserting -RBL silicon nitride between the silicon dioxide and aluminum oxide, interaction between the oxide and Al ^{3 +} may be significantly inhibited according to whether annealed.

FIG. 9 is a graph showing Auger Electron Spectroscopy (AES) depth profiles of samples, respectively, with and without silicon nitride-RBL insertion.

As in Figs. 9 (c) and 9 (f), the data calculated from the AES curves (Figs. 9 (a), 9 (b), 9 (d) and 9 (e)) are sputtered. In stacked dielectrics with and without silicon nitride-RBL as a function of time, the ratio of [Al], the actual concentration of aluminum to [Al] + [O], the sum of the concentrations of aluminum and oxygen, Indicates.

In FIG. 9 (c), aluminum is significantly reduced in silicon dioxide after the RTA process, in that the concentration of aluminum at the silicon dioxide and / or silicon dioxide-silicon carbide interface for the annealed sample without silicon nitride-RBL is significantly increased. You can see that it blends inside.

However, in FIG. 9 (f), it can be seen that there is no difference in the case of samples in which silicon nitride-RBL is inserted according to annealing. From this, it can be seen that diffusion of aluminum into silicon dioxide is inhibited by silicon nitride-RBL.

However, in the case of annealed samples depending on whether silicon nitride-RBL is inserted, structural temperature stability and electrical characteristics of the samples are mainly improved by two causes. First, when silicon nitride-RBL is inserted between aluminum oxide and silicon dioxide on silicon carbide, the interfacial reaction between aluminum oxide and silicon dioxide is suppressed. From this point of view, aluminum is less likely to diffuse into the silicon dioxide. Secondly, the high dielectric breakdown field is increased by the high dielectric constants of thermally stable aluminum oxide and silicon nitride-RBL when compared to the annealed sample without the silicon nitride-RBL inserted.

The silicon carbide semiconductor device and manufacturing method according to the present invention are stable to high temperature heat treatment by using aluminum oxide having a high κ value as an oxide film and inserting a silicon nitride reaction barrier layer between aluminum oxide and silicon dioxide on silicon carbide. The structure can be maintained, which can significantly improve the interface trap density and dielectric breakdown field of the annealed aluminum oxide stacked gate dielectric. Accordingly, the silicon carbide semiconductor device and manufacturing method according to the present invention provide a semiconductor power device suitable for high voltage, high power and high frequency applications.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by those equivalent to the claims.

1 is a cross-sectional view showing a cross section of a silicon carbide semiconductor device according to an embodiment of the present invention;

2 is a cross-sectional view showing a cross section of a silicon carbide semiconductor device according to an embodiment of the present invention;

3 is a flowchart illustrating a method of manufacturing a silicon carbide semiconductor device according to an embodiment of the present invention;

4 is a flowchart illustrating a method of manufacturing a silicon carbide semiconductor device according to an embodiment of the present invention;

FIG. 5 is a diagram showing a capacity-voltage (C-V) relationship according to whether annealing is performed at high frequency (1 MHz) and whether silicon nitride-RBL is inserted;

6 is a diagram showing the distribution of D _it as a function of the energy trapped in the bottom of the dielectric E _C (conduction bandedge);

7 is a diagram showing a J-E relationship depending on whether annealing and silicon nitride-RBL is inserted;

8 is a diagram showing HR-TEM images of samples depending on whether silicon nitride-RBL is inserted and annealed;

9 is a chart showing the AES depth profile of samples, respectively, with and without silicon nitride-RBL insertion and annealing.

Claims (10)

Silicon carbide substrates; A nitrided silicon dioxide layer formed on the silicon carbide substrate; And An aluminum oxide layer which is an insulator formed on the silicon dioxide layer, And the silicon carbide substrate on which the silicon dioxide layer and the aluminum oxide layer are formed is annealed. The method of claim 1, Silicon carbide-based semiconductor device further comprises a silicon nitride layer formed between the silicon dioxide layer and the aluminum oxide layer. The method of claim 1, The silicon dioxide-based semiconductor device, characterized in that the silicon dioxide layer is formed to a thickness of 20 to 25nm. 3. The method of claim 2, The silicon nitride layer is a silicon carbide-based semiconductor device, characterized in that formed to a thickness of 10nm. Forming a nitrided silicon dioxide layer on the silicon carbide substrate; Forming an aluminum oxide layer, which is an insulator, on the silicon dioxide layer; And And annealing the silicon carbide substrate having the silicon dioxide layer and the aluminum oxide layer formed thereon. The method of claim 5, Further comprising forming a silicon nitride layer on the silicon dioxide layer, The aluminum oxide layer is formed on the silicon nitride layer, characterized in that the silicon carbide-based semiconductor device manufacturing method. The method of claim 5, The annealing step is a silicon carbide-based semiconductor device manufacturing method characterized in that the RTA treatment for 2 minutes at 1000 ℃. The method of claim 5, The silicon dioxide-based semiconductor device manufacturing method, characterized in that formed to a thickness of 20 to 25nm. The method of claim 6, The silicon nitride layer is a silicon carbide-based semiconductor device manufacturing method, characterized in that formed to a thickness of 10nm. The method of claim 6, The forming of the silicon nitride layer may include forming the silicon nitride layer by inductively coupled plasma chemical vapor deposition.

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