KR20110047501A - Layout pattern of sense amplifier - Google Patents

Abstract

PURPOSE: A layout pattern of a sense amplifier is provided to reduce the width of a sense amp by arranging two transistors in each row. CONSTITUTION: In a layout pattern of a sense amplifier, two transistors are arranged in each row. One transistor is arranged in the last row. The transistor includes a PMOS transistor and an NMOS transistor which are symmetrically arranged.

Description

Sense amplifier layout structure {LAYOUT PATTERN OF SENSE AMPLIFIER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a sense amplifier layout structure.

Another direction of high performance and low power consumption of semiconductor memory devices is development of next-generation memory devices that do not require a refresh operation, unlike semiconductor memory devices such as volatile DRAMs. One example of such a next generation memory device is a phase change random access memory (PCRAM) using a phase change material.

Phase change material refers to a material such as chalcogenide, whose resistance changes due to a change in phase with a temperature change. Generally, germanium (Ge), antimony (Sb) and antimony and Materials such as Ge _x Sb _y Te _z (hereinafter 'GST'), an alloy of tellurium (Te) are used.

Phase change materials can be usefully used in semiconductor memory devices because of the property that a phase can quickly change into two states, an amorphous state or a crystalline state, depending on temperature.

In addition, since the phase change material becomes a high resistance state in the amorphous state and a low resistance state in the crystallization state, the case of the amorphous state is defined as 'RESET' or logic '1', and the phase conversion material is in a crystallization state. Is defined as 'SET' or logic '0', or vice versa, which can be applied to a semiconductor memory device.

On the other hand, in the case of a nonvolatile memory such as a PCRAM, the current change according to the characteristics of the cell is amplified and exported as data. Accordingly, a larger number of sense amplifiers are required at a smaller cell pitch compared to DRAM.

1 is a layout diagram illustrating a layout structure of a sense amplifier according to the prior art.

As shown in FIG. 1, the layout structure of the sense amplifier is arranged side by side (m0, m1, ...) from left to right, and an under layer, that is, a part which cannot be connected to the gate, is In order to solve the connection between each other, metal layers were used in the B and C regions. In addition, in order to reduce mismatch between each other, they are arranged in a symmetrical layout structure.

However, in the related art, when the length of the cell pitch 'A' is reduced due to shrinking of the semiconductor device, the desired core unit cell pitch is formed. There is a problem in that a sense amplifier cannot be arranged in the. In addition, there is a problem in that the wiring efficiency of the block is also reduced by using a metal layer for the connection with each other.

 The present invention has been proposed to solve the above-described problems of the prior art, and an object thereof is to provide a sense amplifier layout structure capable of solving the width problem of the sense amplifier caused by the reduction of the core unit cell pitch. .

Another object is to provide a sense amplifier layout structure that can ensure the wiring efficiency of the block.

The sense amplifier layout structure of the present invention for achieving the above object is characterized in that in the sense amplifier including a certain transistor in the circuit, two transistors per column and one transistor in the last column.

In particular, the transistor includes transistors of PMOS and NMOS, and the transistors of PMOS and NMOS are arranged symmetrically.

In addition, the sense amplifier is applied to the non-volatile memory, in particular characterized in that applied to the phase change memory.

In addition, the sense amplifier may include repeatedly arranged in an array, and in the sense amplifier repeatedly arranged in the array, adjacent sense amplifiers may be configured to share a common signal.

In addition, the connection between the transistors and the connection between the transistor and the common signal may be characterized by using a gate.

The sense amplifier layout structure according to the embodiment of the present invention described above has the effect of reducing the width of the sense amplifier by arranging two transistors in each column.

In addition, by using a gate, which is a lower layer, for connecting the transistors and connecting the signals, the utilization of metal wiring is minimized, thereby maximizing block wiring efficiency.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

A semiconductor memory is largely composed of a bank, and a cell array divided by a block address in a bank and a sense amplifier array for selecting and amplifying data in a unit cell array unit. A sense amplifier array exists, and a sense amplifier amplifies and latches data. The present invention can be applied to DRAM and non-volatile memory, especially in PCRAM (Phase Change RAM) that uses the resistance change by the phase change (a current change is sensed by sensing the difference in the resistance characteristics of the cell). The sense amplifier layout structure and the layout structure of the sense amplifier array will be described.

2 is a layout diagram illustrating a sense amplifier layout structure according to an embodiment of the present invention.

As shown in FIG. 2, the sense amplifier includes transistors m0 and m3 for precharging operation, transistors m1, m2, m4 and m5 for sensing amplification operation, transistors m6 receiving a reference voltage, and an input signal. And a transistor m7 for enabling operation. At this time, m0 to m3 are PMOS transistors, and m4 to m8 are NMOS transistors.

First, m0 and m3, which are transistors for precharging operation, are disposed at the top, and m1 and m2, which are transistors for the sense amplification operation, are disposed below. Therefore, in the PMOS transistors, four transistors are not arranged side by side, but two transistors are arranged in two.

Then, the transistors m4 and m5 for the sense amplification operation are disposed on the upper side, and the transistor m6 that receives the reference voltage and the transistor m7 that receives the input signal are disposed below. Therefore, NMOS transistors are also arranged in two rows of two transistors instead of four transistors.

Finally, m8, a transistor for enable operation, is disposed at the bottom end.

As described above, by arranging two transistors in each column, the cell pitch 'A' may be reduced to half the width of FIG. 1.

On the other hand, PMOS transistors and NMOS transistors are arranged symmetrically to minimize mismatch during transistor operation. Accordingly, the transistors m1, m2, m4, and m5 for the sense amplification operation of the PMOS and NMOS are symmetrically connected in consideration of the symmetry of the circuit characteristics, and the connection between each transistor is connected to the gate, which is a lower layer. .

In addition, m0 and m3, which are transistors for precharging operation, and m8, which is a transistor for enable operation, are connected to SEN2 through a lower layer, that is, a gate, and m6, which is a reference voltage, is connected to VSREF through a gate.

As described above, the performance of the sense amplifier can be maximized by symmetrically connecting the transistors to minimize mismatch, and minimizing the use of metal wiring by connecting the transistors and the connection between the transistors and the signal to the lower layer of the gate. Therefore, the block wiring efficiency can be maximized, and metal wiring can be replaced with power in the future.

3 is a layout diagram illustrating an array pattern of a sense amplifier according to an embodiment of the present invention.

As shown in FIG. 3, adjacent sense amplifiers are arranged to share a common signal with each other, so that two sense amplifiers are paired to form a pitched layout structure.

In particular, in the repeated arrangement of the sense amplifiers, the common signals (Common Signal) VSREF and SEN2 signals are not disposed one by one in each sense amplifier, it is possible to minimize the area by arranging to share with each other adjacent sense amplifiers. Therefore, the number of sense amplifiers per MAT can be maximized. In addition, this can minimize process errors during layer patterning.

Although the embodiment of the present invention shows the four sense amplifiers are arranged in an array, this is for convenience of description and is not limited thereto and may be repeatedly arranged.

As such, although the technical idea of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a layout diagram illustrating a layout structure of a sense amp player according to the prior art;

2 is a layout for explaining a sense amplifier layout structure according to an embodiment of the present invention;

3 is a layout diagram illustrating an array pattern of a sense amplifier according to an embodiment of the present invention.

Claims (8)

In a sense amplifier comprising a certain transistor in the circuit, A sense amplifier layout structure in which two transistors are arranged in one column, and one transistor is arranged in the last column. The method of claim 1, Wherein said transistor comprises transistors of PMOS and NMOS. The method of claim 2, A sense amplifier layout structure wherein transistors of the PMOS and NMOS are arranged symmetrically. The method of claim 1, And the sense amplifier is applied to a nonvolatile memory. The method of claim 1, And a sense amplifier layout structure applied to a phase change memory. The method of claim 1, And the sense amplifier is repeatedly arranged in an array. The method of claim 6, In the sense amplifier repeatedly arranged in the array, A sense amplifier layout structure in which adjacent sense amplifiers share a common signal. The method according to claim 1 or 7, A sense amplifier layout structure wherein a connection between the transistors and a connection between the transistor and the common signal use a gate.

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