KR20110047144A - Solid state memory with reduced number of partially filled pages - Google Patents

Abstract

PURPOSE: A solid state memory is provided to reduce the number of a page of which a part is filled by including an internal buffer. CONSTITUTION: In a solid state memory, a program instruction of 80h during a first period is received from an LU1. A state S51 is operated. A target is switched into T_PP_LUN_DataWait. The LU1 is switched into L_PP_WaitForData. Data is programmed into the page of a first logic device LU1. The state machine is switched into an idle state of S50. The interleaved instruction 11h of LU1 is executed. A target is switched to a T PP IlvWait. The LU1 is switched to an L PP Ilv Wait. An LU2 is maintained in an L idle state.

Description

Solid state memory with reduced number of partially filled pages {SOLID STATE MEMORY WITH REDUCED NUMBER OF PARTIALLY FILLED PAGES}

The present invention relates, for example, to solid state memory organic to a target, each target comprising one or more logic units (LUNs), each logic unit comprising one or more blocks, and Each block contains one or more pages. Such a device is, for example, a NAND flash memory device designed according to the Open NAND Flash Interface Specification (ONFI).

Such a device is known from US Patent Publication US2008 / 0183949 which describes a method for programming flash memory. Programming in this context is understood by those skilled in the art as writing or storing bits in flash memory cells. Data programming on flash memory is done by programming data one page at a time. If not enough data is provided to program the entire page at the end of the data stream, then the programmed page will only be partially filled at the end of the data stream. If the programmed data stream continues later, there will be a partially filled page between the other fully filled pages. This can be considered insufficient. A better solution is to reread the partially filled data page, complete this data with the data provided for later writing, and then program the entire data page into flash memory. Partially filled pages are reduced at the expense of additional read and programming cycles.

US patent publication US2006 / 0136656 describes a block as the minimum erasable unit of flash memory. This explains the problem of partially filled pages that cannot be easily deleted because the minimum erasable unit is a block rather than a page. Thus, the flash memory is unnecessarily damaged.

The impact of a partially filled page also occurs when a switching operation between two logic devices is performed. When switching from the first logic device to the second logic device is executed, the data remaining in the input buffer is programmed into the first logic device and then switching to the second logic device is performed. If later data is programmed into the first logical device, a new page is used to program the data, so that a partially used page is created in this logical device.

According to the Open NAND Flash Interface Specification (ONFI), writing data to a NAND flash device is done by issuing a PROGRAM PAGE command to the target along with the corresponding logical unit (LUN), block address and page address. Later data of the entire memory page, usually many kilobytes, is written to the page register of the selected logical device. Once the entire page is written to the page register, the logic device begins to program data into that memory array. During programming, the logic device is in use and the next page can be written to the page register of the logic device after programming of the first page is finished. After the entire page is written to the page register and the page program is started, another logical device of the target is selected and used. The ONFI specification also offers the possibility to program partial pages, but this involves additional program counts and reduces the reachable bandwidth.

The following programming statement is defined according to the ONFI specification.

PAGE PROGRAM: Data is written to the data register and programming begins after the data phase is finished.

PAGE CACHE PROGRAM: Data is written to the data register and after the data phase is finished, the contents of the data register are copied to the cache register and programming begins.

PAGE PROGRAM INTERLEAVED: Data is written to multiple data registers of one LUN and programming begins when the last data register is filled.

The known page program flow is used to write the entire data page to the page register of the NAND device and to start programming for the memory array. Each processing procedure causes multiple state switching of the target state machine and the logic device state machine. The state switching of the state machine according to the processing procedure is shown below:

Processing procedure target  condition sequence LUN  condition sequence

T_Idle L_Idle command 80h

Write to NAND device-> T_Cmd_Decode

-> T_PP_Execute

-> T_PP_AddrWait

LUN-, Block- and T_PP_AddrWait L_Idle

Page-Address-> T_PP_Addr->

NAND device-> T_PP_LUN_Execute L_Idle_TargetRequesst

Record-> T_PP_LUN_DataWait-> L_PP_Execute

-> L_PP_Addr

-> L_PP_WaitForData

T_PP_LUN_DataWait full data page

Write to NAND device-> T_PP_LUN_DataPass L_PP_WaitForData

-> T_PP_LUN_DataWait-> L_PP_AcceptData

-> L_PP_WaitForData

NAND T_PP_LUN_DataWait command 10h

Write to device-> T_PP_Cmd_Pass-> L_PP_WaitForData

-> T_Idle-> L_PP_Prog

-> L_PP_ProgWait

-> L_PP_Sts

-> L_Idle

Interleaved operation allows multiple blocks of the same type to issue multiple instructions of the same logical device. Known interleaved page program flows are used to write an entire page of data into a number of independent page registers of a logic device and to begin programming for the memory array when all registers are filled.

Processing procedure target  condition sequence LUN  condition sequence

T_Idle L_Idle command 80h

Write to NAND device-> T_Cmd_Decode

-> T_PP_Execute

-> T_PP_AddrWait

LUN-, Block- and Page- T_PP_AddrWait L_Idle

NAND-> T_PP_Addr->

Write to device-> T_PP_LUN_Execute L_Idle_TargetRequesst

-> T_PP_LUN_DataWait-> L_PP_Execute

-> L_PP_Addr

-> L_PP_WaitForData

T_PP_LUN_DataWait full data page

Write to NAND device-> T_PP_LUN_DataPass L_PP_WaitForData

-> T_PP_LUN_DataWait-> L_PP_AcceptData

-> L_PP_WaitForData

Command 11h NAND T_PP_LUN_DataWait

Write to device-> T_PP_Cmd_Pass-> L_PP_WaitForData

-> T_PP_IlvWait-> L_PP_Ilv

-> L_PP_Ilv_Wait

NAND T_PP_IlvWait command 80h *

Write to device-> T_PP_AddrWait L_PP_Ilv_Wait

LUN-, Block- and T_PP_AddrWait

Page-Address-> T_PP_Addr L_PP_Ilv_Wait

Write to NAND device-> T_PP_LUN_Execure-> L_PP_Addr

->T_PP_LUN_DataWait-> L_PP_WaitForData

T_PP_LUN_DataWait full data page

Write to NAND device-> T_PP_LUN_DataPass L_PP_WaitForData

-> T_PP_LUN_DataWait-> L_PP_AcceptData

-> L_PP_WaitForData

T_PP_LUN_DataWait command 10h

Write to NAND device-> T_PP_Cmd_Pass L_PP_WaitForData

-> T_Idle-> L_PP_Prog

-> L_PP_ProgWait

-> L_PP_Sts

-> L_Idle

The address period for the program operation of the state 'T_PP_IlvWait' is assumed to have an interleaved block address different from that issued in the previous program operation.

If data from two independent sources is written to an independent LUN of the target, then one of the processes described above is first issued to the first LUN for the first independent source and terminates the write process. 2 Issued to the second LUN to write data from independent sources to the second LUN.

When independent concurrency streams must be written to a flash device, it is advantageous to write several streams to multiple logical devices. File management is made easier by this regular method and the overall bandwidth of the logical unit is guaranteed for the recording of incoming data streams. When the data in a stream reaches a block of size smaller than the page size, when the entire page of one logical device is about to be programmed, it caches the data in each stream in a cache arranged outside the flash device and writes it to the NAND flash device. You need to record. Depending on the amount of streams and logic devices, much cache memory is needed outside the memory device, while the available page registers inside the device remain unused.

It is an object of the present invention to provide a solid state memory and a method for operating a solid state memory that can reduce the problem of partially filled pages. It is another object of the present invention to reduce the need for external cache memory and to provide a method for operating solid state memory and solid state memory using internal page registers when multiple incoming data streams are programmed in a flash device.

In order to use the page register of the logical unit as an input buffer for the corresponding incoming data stream, even though the page on the other logical unit cannot yet be completely filled, the operational logic unit must switch according to the characteristics of the current incoming stream. The ONFI specification does not solve this problem and does not provide a dedicated mechanism.

According to the invention, a solid state memory for storing at least one incoming data stream has a number of logic devices in one target. Each logic device has at least one page for programming data in memory. Solid state memory includes an internal buffer memory, sometimes referred to as a page register, to store the incoming data stream temporarily before the incoming data is programmed into at least one page. In addition, the internal buffer memory holds data that has not yet been programmed when switching operations between different logic devices are executed. This has the advantage that the remaining data that is not yet sufficient to completely fill the page when switching from the first logic device to the second logic device does not need to be programmed and is held in the page register. Later, as more data is provided for this logical device, this data is appended to the rest of the data and the remaining data and the new data are programmed to the previous page together. This improves the overall bitrate for programming a particular logic device because programming only a partial page is omitted. Since the programming of full and partial pages is required at about the same time, less programming cycles are required to program a specific amount of data when considering only programming the entire page when possible. In addition, the problem of pages in a solid state memory device in which data is only partially filled in the solid state memory device is eliminated. Solid state memory is used more efficiently.

Preferably, the solid state memory is organized into groups of targets, where each target includes at least one logic device. Each logical unit is equipped with a page register to temporarily store incoming data programmed into that logical unit. Each logic device also includes at least one block. Erasing the memory is done in blocks. Data stored on one page is programmed at a time.

Preferably, each logic device in the solid state memory has an internal buffer for temporarily storing the incoming data stream before the data is programmed into the page. The size of the internal buffer is the size of at least one page plus the maximum allowable input bitrate plus the size of the data received during the programming period of the page. therefore:

Size _{internalBuffer} ≥Size _Page + Time _{PageProgramCycle} * Bitrate _InputData

This has the advantage that during programming of the page data for programming the next page can be received in an internal buffer. If the bit rate of the input data is large enough, for example, an internal buffer of size two pages may receive data of the entire page to be programmed during the programming period of the other page. Thus, the overall latency is reduced and the bit rate of the solid state memory is further improved.

Preferably, the storage device is a NAND flash device, which operates according to the Open NAND Flash Interface (ONFI) specification. The ONFI specification omits partially programmed pages when switching between multiple logic devices is performed, and does not know a specific algorithm for partial page programming, which reduces the number of programming times and hence the programming bitrate. The proposed memory device has the advantage that this essentially complies with the ONFI specification and at the same time omits partial pages. The device according to the invention is a departure from the known implementation of the ONFI standard. Program instructions of the ONFI standard are still used. Any deviation from the implementation rules, as known in the art, is not a denial of the ONFI standard. Thus, a device according to the invention can be considered to be in accordance with the ONFI standard. In addition, the number of programming is reduced because the entire page is programmed each time. In addition, the present invention operates in a page-oriented manner, in particular as a central storage device for capturing measurement data of a research environment for capturing some measurement data in a parallel state or similar environment, in particular in a parallel state. It relates to a solid state storage device, for example applicable to streaming applications, for streaming of several video sources.

Preferably, the solid state memory is part of a video capturing camera system having one or more cameras. The data emitted by the camera is provided to a solid state memory device. Preferably, the solid state memory stores data streams captured by several cameras in various logic devices. Preferably, the camera system is provided for 3D video capturing. In this case several video streams are formed, at least one of which is a high data rate. This video data stream must be stored in parallel in real time. Solid state memory provides several advantages to the camera system as described above. Storing data streams from multiple cameras in multiple logical devices provides an easy file structure and has the advantage of data being organized according to hierarchical memory structures. Thus, in particular the use of a camera system with more than one camera is necessary for 3D capture, for example, so that multiple data streams must be stored simultaneously. In addition, the data stream output by the camera usually has a high data rate. With a high resolution camera (HD), the data stream of one camera reaches, for example, 2 Gbit / s. The solid state storage according to the present invention is of particular advantage because the input data rate of the storage device is not unnecessarily reduced by writing and reading partially filled pages. Because switching between multiple logic devices is done regularly in this system and the problem of pages that are not written or only partially written in one cycle often occurs, data streams from multiple cameras are stored in multiple logic devices. There are many advantages in having a system. In addition to 3D capture, multidimensional capture is also focused in the film industry. The invention is also for the purpose of capturing scenes of a multidimensional environment in real time.

Preferably, a method for operating a solid state storage device comprising at least one logic device is realized. Each logic device includes at least one page and a page being programmed at one time. In the method according to the invention, at least one incoming data stream is input sequentially into the solid state memory. Data is temporarily stored in an internal buffer, a page register. The internal buffer is, for example, the buffer as described above and is allocated to the logical unit. The checking step is executed as to whether or not one whole page contains enough data to be programmed. If the internal buffer contains enough data for one full page to be programmed, at least one full page is programmed. Sufficient data for one full page may be slightly more data than needed for one full page, but may also be enough data to fill several full pages. If the switching operation is executed between several logic devices, the unprogrammed data of the internal buffer of the currently operating logic device is retained in the internal buffer. Switching between logic devices is performed. This has the advantage that the remaining data that does not fill the entire page prior to switching from the first logical device to the second logical device does not need to be programmed, but is held in an internal buffer and still retained after the end of the switching. Later, when more data is provided to this logical device, this data is added to the rest of the data and the remaining data and the new data are programmed together in a full page. This reduces the overall programming time because programming of the partial page requires nearly the same processing time as programming the previous page. Therefore, programming only the whole page improves the programming bandwidth. In addition, the problem of partially filled pages during one programming period in a solid state memory device is eliminated. Solid state memory is used more efficiently.

Advantageously, this method is used to store input data streams captured by different cameras in different logic devices. Storing data streams from multiple cameras in multiple logical devices has the advantage of providing an easy file structure and organizing data according to hierarchical memory structures. Thus, in particular using a camera system with more than one camera is necessary for 3D capture, for example, so that multiple data streams must be stored simultaneously. In addition, the data stream output by the camera usually has a high data rate. With high resolution cameras (HD), the data stream of one camera reaches, for example, 2 Gbit / s. The provided solid state storage is particularly desirable for such systems because the input data rate of the storage is not unnecessarily reduced by reading and writing partial pages. Since switching between multiple logic devices is done regularly in this system and sometimes problems with partial pages occur, there are advantages in systems with multiple cameras where data streams from multiple cameras are stored in multiple logical devices. In addition to 3D capture, multidimensional capture is also concentrated in the film industry. The invention is also dedicated to scene capture of multidimensional environments in real time.

Preferably, this method operates according to the Open NAND Flash Interface (ONFI) specification. Advantageously, the target is set to the state T_PP_I1v_Wait using the page program interleaved command 11h when the data of one logical device is received in the data register and then the switch of the logical device is executed. Using this command, the logical device is set to the state L_PP_Ilv_Wait. Subsequently, the target is held at T_PP_Ilv_Wait and the logical unit is held at state L_PP_I1v_Wait until the LUN's data register is filled with the previous page. These data are then programmed into the page using instructions 10h or 15h. To prevent the target from deleting data from the page register of the addressed logical device, after programming the entire page to the logical device using instructions 10h or 15h, set the target to state T_PP_LUN_DataWait and set the logical device to state L_PP_WaitForData. .

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the present invention, the invention is explained in more detail below in the following description with reference to the drawings. It is to be understood that the invention is not limited to these exemplary embodiments only and that specific features may be combined and / or modified as appropriate without departing from the scope of the invention.

1 is a diagram illustrating a hierarchical structure of a solid state memory device.
2 is a diagram illustrating a method for operating a solid state memory device in accordance with the present invention.
3 is a view showing a state diagram of a target according to the present invention.
4 is a diagram illustrating a state diagram of a logic device according to the present invention.
5 is a state diagram of a solid state memory including one target and two logic devices in accordance with the present invention.

1 shows the structure of a NAND flash memory, which is operated by an ONFI specification command set in accordance with the present invention. NAND flash memory is organicized as a target. The target includes one or more logical units (LOGICAL UNIT 0, LOGICAL UNIT 1, ..., LOGICAL UNIT L), and each logical unit (LOGICAL UNIT 0, LOGICAL UNIT 1, ..., LOGICAL UNIT L) It includes a plurality of blocks (BLOCK 0, BLOCK 1, ..., BLOCK M), and the blocks (BLOCK 0, BLOCK1, ..., ..., BLOCK M) contain a plurality of pages (PAGE 0, PAGE 1, ..., PAGE N). Pages (PAGE 0, PAGE 1, ..., PAGE N) are usually read or write units. This means that the page contains the minimum number of data that can be read or written in one step. Blocks BLOCK 0, BLOCK1, ..., ..., BLOCK M are typically erase units. This means that the block contains the minimum number of data that can be erased in one step. Logical units (LOGICAL UNIT 0, LOGICAL UNIT 1, ..., LOGICAL UNIT L) are units of operation that operate independently. Each logical unit (LOGICAL UNIT 0, LOGICAL UNIT 1, ..., LOGICAL UNIT L) includes a page register (PAGE REGISTER) to temporarily store the data being written or read. Each logical unit also includes control units CU_LU_0, CU_LU_1, ..., CU_LU_L for operating the logical units LOGICAL UNIT 0, LOGICAL UNIT 1, ..., LOGICAL UNIT L. The target TARGET also includes a target control device CU_TRG for controlling the device at the target level.

2 shows a program flow of a device according to the invention. In step S1, it is checked whether the incoming data is valid.

If the incoming data is valid (YES), the page program instruction 80h is written to the target in step S2. In step S3, the LUN-, block-, page- and column addresses are written to the page register of the NAND flash target. In step S4, the next data word is written to the NAND flash target. Next, in step S5, it is checked whether the entire page is valid in the page register of the flash target.

If the entire page is valid (YES), in step S8 the data is stored in each page of the target using the page program 10h or page cache program 15h instruction. In step S9, the page- and block-address are incremented. Next, another page program instruction 80h is written to the target in step S10. In step S11, the LUN-, block-, page- and column addresses are written to the page register of the NAND flash target.

Step 6 is executed (NO) when the whole page is not valid at all in step S5. Step 6 is also executed after step S11. In step S6 it is checked whether there are remaining valid bytes. If there are remaining valid bytes (YES), the method proceeds to step S4. If there are no remaining valid bytes (NO), the interleaved instruction 11h is written to the NAND in step 7 and the method proceeds to step S1.

If no incoming data is valid at step S1 (NO), it is checked at step S12 whether recording has reached the end. If the recording does not reach the end (NO), the method proceeds to step S1 further. When the end of writing is reached (YES), the method checks in step S13 whether an unfinished page remains in the register.

If there is a page not finished in the register (YES), the page program 80h instruction is written to the NAND target in step S14 and the LUN-, block-, page- and column addresses are written to the NAND flash device in step S15. The method then proceeds to step S8 further.

If the page not completed in step S13 remains in the register (NO), the method proceeds to storing data in each page of the target using the page program 10h or page cache program 15h instruction in step S16. Next, the method starts again with step S1.

Note that storing data in a page of a logical device using a page program instruction or a cache page program instruction requires two cycles. In the first period, both the page program and the cache page program are initialized using the 80h instruction. In a second period, the 10h instruction is issued for the page program and the 15h instruction is issued for the cache page program.

3 shows a target state diagram in accordance with the present invention. Target state diagrams according to the invention which are considered individually correspond to target state diagrams according to the ONFI standard. The initial state is T_Idle. When the command is received, the target decodes the received command in the state T_Cmd_Decode. If the decrypted instruction is a page program 80h instruction, the target switches to the state T_PP_Execute. Next, the target sets tLastCmd to 80h. If R / B # is cleared to zero, tbStatus78hReq is set to TRUE. In addition, all LUNs are requested to clear the page register. Next, in the state T_PP_AddrWait, the target waits for an address period. After the address period is received, the received address period is stored in the state T_PP_Addr. If another address period is requested, the target switches back to T_PP_Addr to receive the next address period. If no other address period is needed, the target switches to state T_PP_LUN_Execute. The LUN indicated by the received row address is selected and the target issues the program to the LUN. The target then waits for a data word or command cycle received from the host in state T_PP_LUN_DataWait and sends the data word to the LUN selected in state T_PP_LUN_DataPass. When the command is received at T_PP_LUN_DataWait, the target switches to the state T_PP_Cmd_Pass. Next, a command is sent to each LUN. If the instruction is an 11h instruction, the target switches to state T_PP_IlvWait to wait for the next instruction to be issued. If this command is page program 80h, the next byte is written to the LUN according to the method described above. On the other hand, if the instruction is a 10h or 15h instruction, the target returns to the initial state T_Idle.

4 illustrates a logic device state diagram in accordance with the present invention. The logical unit state diagram according to the invention, which is considered separately, corresponds to the logic unit state diagram according to the ONFI standard. The initial state is L_Idle. After the target request has been received for this LUN, the LUN switches to the state L_Idle_TargetRequest to wait for commands issued by the target. If the target indicates a program request, the LUN switches to L_PP_Execute and then to L_PP_Addr to record the address received by the target. In addition, the correct page register is selected based on the interleaved address and the cloum of the page register is selected according to the received column address. The LUN then receives data delivered by the target in states L_PP_WaitForData and L_PP_AcceptData. If the LUN receives an 11h command, the LUN switches to the state L_PP_IlvWait until the target requests another program command for this LUN. When a LUN receives a 10h or 15h command in state L_PP_WaitForData, the LUN switches to state L_PP_Prog, L_PP_ProgWait, and L_PP_Sts and programs each data on each page.

To illustrate the method in more detail, FIG. 5 shows a state diagram of a solid state memory including one target and two logic devices according to the present invention. Thus, an acceptable combination of logical devices LU1, LU2 corresponding to the target state is shown. The method of the invention is also applicable to at least one target comprising two or more logic devices. For simplicity, only the state in which the page program instruction or page cache program instruction or interleaved instruction 11h of the first period 80h or the second period 10h / 15h is issued is shown. In order to switch from the first state to the second state of the target and each LUN, the state switch according to FIGS. 3 and 4 between the first and second states must also be executed. The status switch is implemented as described in the ONFI specification.

In initial state S50, the target is in idle state T_Idle. LUNs are also in idle state L_Idle. When the page program command of the first period 80h is received from LU1, the state S51 is activated. Thus, the target is switched to T_PP_LUN_DataWait and LU1 is switched to L_PP_WaitForData. LU2 does not change its state. Thus, LU1 is now ready to receive data. After receiving data at LU1, it is checked whether page program 10h or page cache program 15h of the second period has been issued. In this case, the data is programmed into the page of the first logical device LU1 and the state machine is switched back to the idle state S50. When the interleaved command 11h of LU1 is issued, the target is switched to T_PP_IlvWait and LU1 is switched to L_PP_Ilv_Wait. LU2 stays in the L_idle state. This corresponds to S52 of FIG. 5. Thus, another page program command 80h of the first period may be issued for logical device LU1 or LU2. When the page program command 80h is issued for LU1, the state machine switches back to state S51. When the page program command 80h is issued for LU2, the state machine switches to S53. In order to issue the page program 80h instruction of the first period to the second logical device, the interleaved 11h instruction previously issued to the first logical device forms part of the characteristics of the present invention. Thus, state transitions are indicated by bold arrows. At this time, the target is waiting for new data or a new command from the host in state T_PP_LUN_DataWait, LU1 is waiting in state L_PP_IlvWait, and LU2 is waiting for data received in state L_PP_WaitForData. In succession, LU1 is not reset to the idle state until it switches to the state where LU2 is waiting for data. Thus, when switching from LU1 to LU2 according to the method, the data of the page register from LU1 is not lost, which is one of the advantages of the present invention.

Since the state S53 is reached after the instruction of the first period is issued to LU2, the page program instruction 10h, the page cache program instruction 15h, or the interleaved instruction 11h of the second cycle dedicated to LU2 in the state S53 are acceptable. Issuing a page program command 10h or page cache program command 15h dedicated to LU2 results in the T_Idle state of the target and the L_Idle state of LU2. This corresponds to state S54 of FIG. 5. From state S54, the page program 80h or page cache program 80h instruction of the first period is issued to LU1 or LU2. When the 80h command is issued to LU1, the state machine switches to state S51. If an 80h instruction is issued to LU2, the state machine switches to S53.

If the interleaved 11h command is issued to LU2 in state S53, the target switches to T_PP_IlvWait and LU2 switches to L_PP_Ilvwait. Since LU1 is kept in L_PP_IlvWait, the state machine is in state S59 and is ready to receive the next request of the first cycle for LU1 or LU2. When an 80h command is issued to LU1, the state machine switches to state S57 to wait for a command to LU1. From the state S59 reached after receiving the interleaved instruction for LU2, the state machine switches from the state machine waiting for the page program instruction 10h, the page cache program instruction 15h of the second cycle, or the interleaved instruction 11h. Is part of. The known scheme is to receive the page program command 80h of the first period in state S59 when the interleaved command 11h has reached state S59 for LU2. The state machine switches back to state S53 to wait for a command to LU2 as already described above.

If a command is issued correspondingly to other logic devices, states S55, S56, S57 and S58 and their state switching correspond to states S51, S52, S53 and S54 and their state switching. Therefore, detailed description is omitted.

Therefore, the program flow according to the present invention uses the interleaved page program 11h to bring the target and the LUN into a state in which the additional data T_PP_IlvWait and L_PP_IlvWait respectively correspond. This is the case in states S52, S56 and S59 according to FIG. According to the present invention, a small data block of less than one page in size is written to the page register of the first logic device, switched to another logic device, and switched back to the first logic device and then to the page register of the first logic device. Writing continues, and then it becomes possible to program the complete page into the first logical device.

The program flow for writing data from multiple data sources to multiple LUNs is as follows:

Processing procedure target  condition sequence LUN  condition sequence

T_Idle L_Idle command 80h

Write to NAND device-> T_Cmd_Decode

-> T_PP_Execute

-> T_PP_AddrWait

LUN-, Block- and Page- T_PP_AddrWait L_Idle

NAND-> T_PP_Addr->

Write to device-> T_PP_LUN_Execute L_Idle_Target

-> T_PP_LUN_DataWait Requesst

-> L_PP_Execute

-> L_PP_Addr

Data Page Size T_PP_LUN_DataWait-> L_PP_WaitForData

Less than data block-> T_PP_LUN_DataPass

-> T_PP_LUN_DataWait L_PP_WaitForData

Record-> L_PP_AcceptData

-> L_PP_WaitForData

Command 11h NAND T_PP_LUN_DataWait

Write to device-> T_PP_Cmd_Pass

-> T_PP_IlvWait-> L_PP_WaitForData

-> L_PP_Ilv

-> L_PP_Ilv_Wait

[.. Write data to another logical device ..]

NAND command 80h * T_PP_IlvWait L_PP_Ilv_Wait

Write to device-> T_PP_AddrWait

LUN-, Block- and T_PP_AddrWait L_PP_Ilv_Wait

Pages- and rows-> T_PP_Addr-> L_PP_Addr

NAND-> T_PP_LUN_Execure-> L_PP_WaitForData

Write to device-> T_PP_LUN_DataWait

T_PP_LUN_DataWait L_PP_WaitForData

Write to NAND device-> T_PP_LUN_DataPass-> L_PP_AcceptData

Previous page-> T_PP_LUN_DataWait-> L_PP_WaitForData

Until recorded

Command 10h T_PP_LUN_DataWait L_PP_WaitForData

Write to NAND device-> T_PP_Cmd_Pass-> L_PP_Prog

-> T_Idle-> L_PP_ProgWait

-> L_PP_Sts

-> L_Idle

The address period for the page program operation of state T_PP_IlvWait has the same interleaved block address as issued in the previous page program operation, but the column address is incremented to place another data block in the correct position in the page register. .

Claims (10)

A solid state memory for storing at least one incoming data stream, the solid state memory having a plurality of logical units Logical_Unit_0, Logical_Unit_1, ..., Logical_Unit_L, each logical unit (Logical_Unit_0, Logical_Unit_1, ..., Logical_Unit_L) is a solid state memory having at least one page (Page0, Page1, ..., PageN),
Each logical unit Logical_Unit_0, Logical_Unit_1, ..., Logical_Unit_L has an internal buffer for temporarily storing the incoming data stream before the incoming data is programmed into at least one page (Page0, Page1, ..., PageN). And a memory (Page_Register), wherein the internal buffer memory (Page_Register) holds data that has not yet been programmed when a switching operation to a different logical device is executed. 2. The solid state memory of claim 1 wherein each logical device includes at least one block that is a minimum erasable unit of the memory, and each block includes at least one page that is a minimum programmable unit of the memory. The solid state of claim 1 or 2, wherein at least one of the internal buffers of the logic device has a minimum size for storing the entire page and data received during the programming period of the page at the highest acceptable input bitrate. Memory. 4. The solid state memory of claim 1, wherein the storage device is a NAND flash device operating according to an open NAND flash interface specification. A camera system comprising one or more cameras, wherein the camera system comprises a solid state memory according to any of the preceding claims. 6. The camera system of claim 5, wherein the data stream comprising at least two cameras and captured by different cameras is stored in different logic devices. A method for programming at least one data stream into a solid state memory, the solid state memory comprising at least one logic device, each logic device including at least one page, and wherein the pages are programmed at one time. :
Sequentially inputting at least one incoming data stream into the solid state memory;
Storing data associated with the logical device in an internal buffer included in the logical device;
Checking whether the buffer contains data for at least one full page being programmed;
If the checking step is positive, programming at least one page; And
If a switching operation is performed between different logic devices, retaining data not yet programmed in the internal buffer memory.
How to include. The method of claim 7, wherein
Storing the input data stream captured by a camera system with different cameras in different logic devices
How to include more. The method according to claim 7 or 8,
Setting a target to a state T_PP_Ilv_Wait and a logical device to a state L_PP_Ilv_Wait using the Page Program Interleaved command 11h after receiving the data in the data register;
Maintaining the target in state T_PP_Ilv_Wait and maintaining the logical device in state L_PP_Ilv_Wait until the data register of the LUN is filled with full pages; And
Programming the data into a page using the instructions 10h or 15h
The method further comprises the state and instructions according to the ONFI standard. The method according to any one of claims 7 to 9,
Set the target to state T_PP_LUN_DataWait and program the logic device after programming the entire page into the logic device using the instructions 10h or 15h to prevent the target from deleting data from the page register of the addressed logic device. Setting to L_PP_WaitForData, wherein the status and instructions comply with the ONFI standard.

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