KR20110046985A - Cap-less memory device - Google Patents

Abstract

PURPOSE: A capacitance less memory device and a method thereof are provided to improve a kind effect by using a strained silicon as a silicon body. CONSTITUTION: In a capacitance less memory device and a method thereof, 2V gate voltage is supplied to a gate electrode. A ground voltage is provided in a source region. 1.5V and 4V are applied to a drain region. A first bit is performed. The gate voltage of -1.5V is applied to a gate electrode unit. A ground voltage is provided in a source region. 1.5V and 4V are applied to a drain region. A second bit is performed.

Description

Capacitor-less memory device and driving method thereof {Cap-less memory device}

The present invention relates to a capacitorless memory device and a driving method thereof, and to a memory device and a driving method thereof, which may not form a separate capacitor for charge storage.

In general, a memory device refers to a device that stores and stores certain information and can be taken out at a necessary time. One example of such a memory device is a DRAM (Dynamic Random Access Memory) device. DRAM integrates a plurality of unit cells composed of one transistor and one capacitor. That is, one bit of information is stored in the capacitor of the unit cell on the basis of charging or not.

Recently, many unit cells are integrated in the same area to store more information and secure price competitiveness. As such, in order to integrate a larger number of unit cells in the same area, an integrated area (ie, size) of transistors and capacitors constituting the unit cell must be reduced. However, there is a disadvantage in that the area of the transistor and the capacitor cannot be reduced indefinitely.

If the area of the capacitor is reduced, the capacitance is reduced accordingly. Therefore, in order to keep the capacitor constant, the height of the capacitor must be increased. That is, for example, when the DRAM design rule is 60 nm, the height of the capacitor is about 1.6 mu m. If the DRAM design rule is reduced to 40nm, the height of the capacitor is increased to about 2.0㎛. As such, when the height of the capacitor is increased, a problem occurs that smooth patterning becomes difficult because the aspect ratio is large when forming a hole for manufacturing a capacitor having a cylinder structure. In addition, as the spacing between adjacent capacitors decreases, and the height of the capacitors increases, there is a problem that the adjacent capacitors are electrically connected due to the collapse of the capacitors. Therefore, when the DRAM design rule is reduced to 40 nm or less, it is difficult to apply a capacitor having a cylinder structure.

Recently, studies on device types that can eliminate and replace capacitors of DRAM devices, which cause many problems according to the reduction of design rules, are being actively conducted. For example, there is a capless memory device (ie, a capacitorless memory device) in which a unit cell is manufactured using one transistor. In the case of a capacitorless memory device, a charge is charged to a silicon body of a transistor instead of a conventional capacitor.

In such a capacitor-free memory device, when a voltage greater than the gate is applied to the drain of a transistor, impact ionization occurs due to a strong electric field of the drain, and electrons are forced out to the drain, but the hole is a silicon body (that is, a silicon layer below the transistor). Accumulate). The accumulation of these holes causes the threshold voltage to change, which in turn causes the drain current to change (ie, referred to as the kink effect). At this time, the drain current change is read to determine whether bit information is stored in the cell.

In such a capacitorless memory device, holes are accumulated in a silicon body (a single crystal silicon layer) in which source and drain regions are formed. At this time, the silicon body has a disadvantage of low mobility, and due to this disadvantage the kink effect is reduced.

Accordingly, one technical problem of the present invention is to use a strained silicon as a silicon body to improve a kink effect through mobility improvement, and to drive a capacitor-free memory device capable of multi-bit driving by changing a voltage applied to a memory device and driving thereof. Provide a method.

A semiconductor layer formed by depositing strained silicon on a bottom insulating layer formed on a semiconductor substrate according to an embodiment of the present invention, a gate insulating film and a gate electrode formed on the semiconductor layer, and the A method of driving a capacitorless memory device in which a channel is formed in a semiconductor layer and source and drain regions are formed in both semiconductor layers of the channel, wherein a gate voltage and a back bias voltage are applied to the gate electrode and the semiconductor substrate, respectively. A method of driving a capacitorless memory device using a voltage having a first polarity as a gate voltage and using a voltage having a second polarity different from the first polarity and having a large absolute value as the back bias voltage.

When a positive voltage is used as the gate voltage, a negative voltage whose absolute value is greater than a positive voltage of the gate voltage is used as the back bias voltage, and when a negative voltage is used as the gate voltage, It is possible to use a positive voltage greater than the negative voltage absolute value of the gate voltage as the back bias voltage.

When a positive voltage is used as the gate voltage, holes are accumulated in a channel region adjacent to the bottom insulating layer, and when a negative voltage is used as the gate voltage, holes are accumulated in a channel region adjacent to the gate insulating layer. It is possible.

When using 1 to 3 V as the gate voltage, it is possible to use -15 to -25 V as the back bias voltage.

When using -0.5 to -2V as the gate voltage, it is possible to use 5 to 25V as the back bias voltage.

Multi-bit driving may be performed by applying voltages having different polarities to the gate voltage and the back bias voltage, and varying the voltage levels of the gate voltage and the back bias voltage.

Provide ground power to the source region to write data of '1', apply a write voltage greater than a kink voltage to the drain region, apply an erase voltage to the drain region for data erasing, and read data. It is possible to apply a read voltage between the kink voltage and the erase voltage to the drain region.

In addition, a capacitorless memory device, comprising: a gate electrode portion including a semiconductor substrate receiving a back bias voltage, a gate electrode receiving a gate voltage, and a gate insulating film positioned between the gate electrode and the semiconductor substrate; Located between the bottom insulating layer located and the bottom insulating layer and the gate electrode portion, when a positive voltage is used as the back bias voltage, holes are accumulated in the region adjacent to the gate electrode portion, and the positive voltage is used as the gate voltage. When using a voltage, a capacitor-free memory device includes a channel in which holes are accumulated in a region adjacent to the bottom insulating layer and includes a channel made of strained silicon and source and drain regions connected to channels on both sides of the channel.

It is possible that the absolute value of the voltage used as the gate voltage is smaller than the absolute value of the back via voltage.

Multi-bit driving may be performed by applying voltages having different polarities to the gate voltage and the back bias voltage, and varying the voltage levels of the gate voltage and the back bias voltage.

As described above, in one embodiment of the present invention, the use of strained silicon as the semiconductor layer may improve electron mobility, thereby increasing the kink effect. In addition, the gate voltage and the back bias voltage may be applied to the gate electrode and the semiconductor substrate of the device, respectively, and the voltage polarity may be changed between the plurality of bits in a single cell. In addition, the multi-level driving may be performed by changing the voltage level applied to the gate electrode and the semiconductor substrate.

With reference to the accompanying drawings will be described an embodiment of the present invention in more detail. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as being on or above another part, each part is not just above or directly above another part but also another part between each part and another part. This includes cases.

1 is a cross-sectional view of a capacitorless memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a capacitorless memory device according to the present exemplary embodiment may include a semiconductor substrate 110 to be used as a lower gate, a bottom insulating layer 120 disposed on the semiconductor substrate 110, and a bottom insulating layer. The semiconductor layer 130 in which holes are stored and channels are formed, the gate electrode portion 140 formed on a portion of the semiconductor layer 130, and the semiconductor layer 130 at both sides of the gate electrode portion 140, respectively. Source and drain regions 150 and 160 formed are included.

Here, when the gate electrode portion 140 is used as the front gate, holes are stored in the region of the semiconductor layer 130 adjacent to the bottom insulating layer 120, and when the semiconductor substrate 110 is used as the back gate, the gate electrode portion The holes are stored in the region of the semiconductor layer 130 adjacent to the 140.

The source and drain regions under the interlayer insulating layer 170 may be formed through the interlayer insulating layer 170 formed on the semiconductor layer 130 including the gate electrode part 140 and a portion of the interlayer insulating layer 170. First and second wiring parts 180 and 190 directly connected to 150 and 160 are further provided. The first wiring unit 180 is connected to the source region 150 through the first contact plug, and the second wiring unit 190 is connected to the drain region 160 through the second contact plug. In this case, the first and second contact plugs may include a contact hole exposing a portion of the lower source and drain regions 150 and 160 by removing a portion of the interlayer insulating layer 180, and a conductive material filled in the contact hole. Include. As described above, the capacitorless memory device of the present exemplary embodiment may directly connect the wiring portion and the source and drain regions 150 and 160 without using a capacitor.

As the semiconductor substrate 110, a single element semiconductor substrate or a compound semiconductor substrate may be used. Of course, the semiconductor substrate 110 may be doped with a predetermined impurity.

It is possible to use a silicon oxide film layer or a silicon nitride film layer as the bottom insulating layer 120. In this embodiment, a silicon oxide film is used as the bottom insulating layer. In this case, the silicon oxide film may be manufactured by oxidizing a part of the semiconductor substrate 110. Of course, the present invention is not limited thereto, and the bottom insulating layer 120 may be manufactured by ion implantation. In the present embodiment, when the semiconductor substrate 110 is used as a back gate, the bottom insulating layer 120 may serve as a gate insulating film. Therefore, when operating as a back gate, it is effective to apply the voltage applied to the back gate, that is, the semiconductor substrate 110, to be relatively larger than the voltage applied to the front gate.

The gate electrode part 140 is provided on the gate insulating layer 141 formed in the upper partial region of the semiconductor layer 130, the gate electrode 142 formed on the gate insulating layer 141, and at least on the side surface of the gate electrode 142. The spacer 143 is provided. In this case, the gate insulating layer 141 may be manufactured in a single layer or multiple layers. Of course, in this embodiment, a silicon oxide film is used as the gate insulating film 141. Of course, the present invention is not limited thereto, and an insulating film having a high dielectric constant may be used as the gate insulating film 141.

The gate electrode 142 may be manufactured in a single layer or multiple layers, and although not shown in the present embodiment, a polysilicon layer doped with impurities (for example, N type or P type) with the gate electrode 142 and formed thereon It may also include a metal layer. If necessary, a portion of the gate electrode 142 may protrude into the semiconductor layer 130. The above-described gate electrode unit 140 controls a channel formed in the semiconductor layer 130 according to a voltage applied through a word line (or a gate line; not shown). Accordingly, the shape of the gate electrode 140 is not limited to the above description, and various shapes for the channel control are possible.

The source and drain regions 150 and 160 are formed by implanting impurity ions into the semiconductor layer 130 at both sides of the gate electrode 140. Here, N type or P type ions can be used as impurity ions. In the present embodiment, the source and drain regions 150 and 160 are formed by implanting N-type impurities. Here, during the ion implantation, lightly doped drain (LDD) ion implantation may be performed. Of course, the present invention is not limited thereto, and the semiconductor layer 130 corresponding to the source region 150 and the drain region 160 on both sides of the gate electrode unit 140 is not formed, but instead, a separate junction layer (not shown) is formed. Source and drain regions 150 and 160 may also be formed. The source and drain regions 150 and 160 described above move electrons along a channel formed in the semiconductor layer 130 according to an applied voltage or store holes in the semiconductor layer 130 under the gate electrode part 140. . Accordingly, the shape of the source and drain regions 150 and 160 is not limited to the above description, and various shapes for moving electrons to the channel are possible.

In the semiconductor layer 130 according to the present exemplary embodiment, charge is stored adjacent to an electrode portion forming region where the source and drain regions 150 and 160 are formed, and either one of an upper surface or a lower surface thereof. It has a channel region 135 in which a channel to move is formed. In this case, as described above, the region of the semiconductor layer 130 below the gate electrode portion 140 becomes the channel region 135, and both sides of the gate electrode portion 140, that is, both sides of the channel region 135, form the electrode portion. It becomes a formation area. The channel region 135 is a region that operates as a channel of the memory device.

In this embodiment, it is effective to use strained silicon as the semiconductor layer 130. Of course, the present invention is not limited thereto, and a silicon germanium layer may be used as the semiconductor layer 130. In addition, a relaxed silicon germanium layer may be used and a strained silicon germanium layer may be used. In addition, a stress relaxed silicon layer may also be used.

A silicon substrate is used as the semiconductor substrate. In order to fabricate a structure in which the semiconductor substrate 110, the bottom insulating layer 120, and the semiconductor layer 130 are stacked in this manner, a first silicon substrate is first prepared, and a strained silicon layer is formed thereon. Next, a second silicon substrate having an oxide film formed on its surface is prepared. Subsequently, the two substrates are bonded such that the strained silicon layer of the first silicon substrate and the oxide region of the second silicon substrate are in close contact with each other. A portion of the first silicon substrate on the strained silicon layer is then cleaved. Through this, a modified SOI-type material can be manufactured. The buffer layer may also be formed before the formation of the strained silicon layer, without being limited thereto. This may facilitate the formation of strained silicon.

In this embodiment, strained silicon is used as the semiconductor layer 130.

2 is an experimental result of measuring the electron mobility of the capacitorless memory device of the present embodiment.

Line A of FIG. 2 is a case where strained silicon is used as a semiconductor layer, and line B is a case where unstrained silicon is used. As shown in FIG. 2, it can be seen that the electron mobility in the case of A using strained silicon as the semiconductor layer of the capacitorless memory device of the present embodiment is higher. Due to the improved mobility, the kink effect can be further increased.

Hereinafter, an operation of a capacitorless memory device using strained silicon as the semiconductor layer will be described.

3 is a conceptual diagram illustrating an operation of a capacitorless memory device according to an exemplary embodiment. 4 and 5 are conceptual cross-sectional views for describing an operation of a capacitorless memory device according to example embodiments.

4A is a conceptual cross-sectional view for explaining a write operation, and FIG. 4B is a conceptual cross-sectional view for explaining a read operation of an element to which data of " 1 " is written, and FIG. ) Is a conceptual cross-sectional view for explaining the erase operation, and FIG. 5B is a conceptual cross-sectional view for explaining a read operation of an element to which " 0 " data (i.e., erase data) is written.

The voltage current in a unit cell of a typical memory device converges as the current increases constantly as the voltage increases, as illustrated by the N1 graph shown in FIG. 3. However, in the capacitorless memory device described in the present embodiment, when the voltage increases as illustrated by the N2 graph of FIG. 3, the current increases again.

This is because charges (that is, holes) are accumulated in the semiconductor layer 130, that is, the channel region 135 under the gate electrode part 140. In the case where charge is accumulated in the channel region 135, the current flow is different from the initial flow even when the voltage is reduced as shown in the N3 graph of FIG. 3.

Therefore, in the capacitorless memory device according to the present exemplary embodiment, the current flow changes according to whether or not holes are accumulated in the semiconductor layer 130, and the information written in the device is determined using the current flow difference.

In this case, a write voltage equal to or greater than a voltage causing a kink effect is provided to the drain region 160 to write data corresponding to "1" to the device, and the drain region 160 to erase with data corresponding to "0" to the device. To the erase voltage. Then, a read voltage between the kink voltage and the erase voltage is applied to determine the data written to the device.

For example, as shown in FIG. 4 and FIG. 5, a case in which a voltage of 4 V is used as the write voltage, a voltage of −1 V is used as the erase voltage, and 1.5 V is used as the read voltage is as follows. .

First, to perform a write operation, as shown in FIG. 4A, a voltage of 2 V is applied to the gate electrode unit 140, a ground voltage GND is provided to the source region 150, and a drain region 160 is provided. 4V). In this case, as shown in FIG. 4A, holes are stacked in the semiconductor layer 130.

Subsequently, to perform an erase operation, as shown in FIG. 5A, a voltage of 2 V is applied to the gate electrode part 140, a ground voltage GND is provided to the source region 150, and a drain region ( 160) was applied to -1V. In this case, as shown in FIG. 5A, holes do not accumulate in the semiconductor layer 130.

In order to perform the read operation, as shown in FIGS. 4B and 5B, a voltage of 2V is applied to the gate electrode 140, and a ground voltage GND is applied to the source region 150. And 1.5V was applied to the drain region 160. At this time, when a hole is trapped in the semiconductor layer 130 (that is, when "1" data is written) as shown in FIG. 4B, the current in the state where the "1" data shown in FIG. 2 is written. Will flow. On the other hand, when holes are not trapped in the semiconductor layer 130 as shown in FIG. 5B (that is, when "0" data is written), the "0" data shown in FIG. 3 is written. Current will flow. At this time, it can be seen that the current flow in the state where the "1" data is written is greater. This is because when a hole is trapped in the semiconductor layer 130 as described above, a change occurs in the threshold voltage of the device and more current flows.

In addition, the capacitorless memory device according to the present embodiment may implement a plurality of bits in a single cell.

6 is a conceptual cross-sectional view illustrating a multi-bit operation of a capacitorless memory device according to an exemplary embodiment. 7 is a graph illustrating an I-V curve of a front gate operation according to an embodiment, and FIGS. 8 and 9 are graphs of experimental results for explaining the effect of the front gate operation according to an embodiment. FIG. 10 is a graph illustrating an I-V curve of a back gate operation according to an embodiment, and FIGS. 11 and 12 are graphs of experimental results for explaining an effect of a back gate operation according to an embodiment.

The capacitorless memory device of the present exemplary embodiment may perform a plurality of bit operations by changing the gate voltage VG and the back bias voltage VB. That is, one bit operation may be performed by applying a positive voltage to the gate electrode unit 140 and applying a negative voltage as a back bias applied to the semiconductor substrate 110. On the contrary, another bit operation may be performed by applying a negative voltage to the gate electrode 140 and applying a positive voltage to the back bias of the semiconductor substrate 110.

As shown in FIG. 6A, a gate voltage VG of 2V is applied to the gate electrode unit 140, and a ground voltage GND is provided to the source region 150 as the source voltage VS. In the state where -20V is provided as the back bias, 1.5V and 4V are respectively applied to the drain region 160 as the drain voltage VD to perform the operation of the first bit. In this case, providing 1.5V to the drain region 160 is for performing a read operation, and providing 4V is for performing a write operation.

In addition, as shown in FIG. 6B, a gate voltage VG of −1.5 V is applied to the gate electrode unit 140, a ground voltage GND is provided to the source region 150, and a back bias is provided. In the state where 20V is provided as (VB), 1.5V and 4V are respectively applied to the drain region 160 as the drain voltage VD, thereby performing the operation of the second bit.

That is, a first bit operation is performed by applying a voltage having a different polarity from the bias voltage as a gate voltage of the gate electrode, and a gate voltage and a bias having a different polarity than the first bit operation are applied to the gate electrode and the semiconductor substrate. The voltage may be applied to perform the operation of the second bit. Here, it is preferable that the absolute value of the bias voltage is larger than the absolute value of the gate voltage in the above-described bit operation.

Of course, the capacitorless memory device according to the present embodiment may also perform multi-level operation. It is possible to operate at various levels according to the gate voltage and the bias voltage applied in each bit operation mentioned above. This will be described in detail with reference to the accompanying drawings.

Prior to this, the principle of the multi-bit operation will be described.

First, when a positive voltage is applied to the gate electrode 140, the front gate cell is operated. At this time, a positive voltage is applied to the gate electrode part 140 and a negative voltage is applied to the semiconductor substrate 110, so that the semiconductor substrate 110 is adjacent to the semiconductor substrate 110 in the channel region 135 under the gate electrode part 140. Holes are accumulated in the region, that is, in the region of the semiconductor layer 130 connected to the bottom insulating layer 120. Then, a channel is formed in the region of the semiconductor layer 130 connected to the gate insulating film 141 (see FIG. 6A).

On the contrary, when a positive voltage is applied to the semiconductor substrate 100, the operation is performed with the back gate cell. That is, a positive voltage is applied to the semiconductor substrate 100 and a negative voltage is applied to the gate electrode portion 140, so that a channel is formed in an area of the channel region 135 adjacent to the semiconductor substrate 110. Holes are accumulated in an area adjacent to the gate electrode part 140 (see FIG. 6B).

In this case, a thin gate insulating layer 141 is disposed between the gate electrode 142 of the gate electrode unit 140 and the semiconductor layer 130. However, a bottom insulating layer 120 thicker than the gate insulating layer 141 is formed between the semiconductor substrate 110 and the semiconductor layer 130.

Therefore, the strength of the voltage applied to the semiconductor substrate 110, that is, the back bias, must be greater than the strength of the voltage applied to the gate electrode 140.

In this embodiment, the gate voltage VG of 1 to 3 V is applied to the gate electrode part through various experiments, and at this time, applying -15 to -25 V as the back bias voltage VB effectively operates as the front gate cell. . At this time, the multi-level operation may be performed according to the gate voltage VG applied.

This will be described with reference to the graph of FIG. 7. In the graph of FIG. 7, the dotted lines (ie, D1, D2, and D3) represent a comparative example using silicon that is not strained into the semiconductor layer 130, and the solid lines C1, C2 and C3 are strained into the semiconductor layer 130. This is the case of the embodiment using de silicon. The results of lines C1 and D1 are graphs of results when 1 V is used as the gate voltage VG, and the results of lines C2 and D2 are graphs of results of 2 V used as the gate voltage VG. The result of the line is a result graph when 3V is used as the gate voltage VG. At this time, -20 V was applied to all of the back bias voltages VB.

As shown in the graph of FIG. 7, a strained silicon layer is used as the semiconductor layer 130, a voltage of 1 to 3 V is used as the gate voltage VG, and a -20 V range is used as the back bias voltage VB. In this case, it can be seen that the IV curve as mentioned in FIG. In FIG. 7, it can be seen that the current difference flowing by the curves C1, C2, and C3 of the present embodiment is greater than the current difference flowing by the curves D1, D2, and D3 of the comparative example. This enables multilevel operation.

In addition, by applying the gate voltage and the back bias voltage in the above voltage range, the memory margin and the memory margin difference may be increased to implement multi-level operation.

That is, the E and G lines of FIGS. 8 and 9 are the experimental results of the present embodiment using the strained silicon as the semiconductor layer 130, and the F and H lines compared with the non-strained silicon as the semiconductor layer 130. Yes.

As shown in the result of FIG. 8, in the capacitorless memory device according to the present exemplary embodiment, even though -20 V is used as the back bias voltage VB and the gate voltage is varied from 1 V to 3 V, the memory margin is improved compared to the comparative example. It can be seen. In addition, as shown in the result of FIG. 9, it can be seen that in the capacitorless memory device according to the present exemplary embodiment, the memory margin difference when the gate bias range is changed is also improved as compared with the comparative example. That is, as in FIG. 9, the memory margin difference between the gate bias voltage of 1.7V and 1.0V was about 23 mA in the comparative example, but was 45.2 mA in this embodiment. Such a large memory margin difference facilitates the implementation of multiple levels.

In this embodiment, the gate voltage VG of -0.5 to -2V is applied to the gate electrode part through various experiments, and at this time, adding 5 to 25V as the back bias voltage VB effectively operates as the back gate cell. can do. Through this, it is possible to operate with a plurality of bits together with the front gate cell.

In addition, multi-level implementation may be possible according to the back bias voltage (VB) range.

This will be described with reference to the graph of FIG. 10. In the graph of FIG. 10, the solid lines I1, I2, I3, and I4 are examples of an experimental example using strained silicon as the semiconductor layer 130, and the dotted lines (ie, J1, J2, J3, and J4) represent the semiconductor layer 130. This is the case with non-strained silicon. The I1 and J1 lines are the result graphs when 5 V is used as the back bias (VB), and the I2 and J2 lines are the result graphs when 10 V is used as the back bias (VB), and I3 and J3. The result of the line is a result graph when 15 V is used as the back bias VB, and the result of the line I4 and J4 is a result graph when 20 V is used as the back bias VB. At this time, −1.5 V was applied to all of the gate voltages VG.

As shown in the graph of FIG. 10, a strained silicon layer is used as the semiconductor layer 130, a voltage of −1.5 V is used as the gate voltage VG, and a range of 5 V to 20 V is used as the back bias voltage VB. In this case, it can be seen that the IV curve as mentioned in FIG. In FIG. 10, it can be seen that the current difference flowing by the curves I1, I2, I3, and I4 of the present embodiment is greater than the current difference flowing by the curves J1, J2, J3, and J4 of the comparative example. This enables multilevel operation.

In addition, by applying the back bias voltage (VB) and the gate voltage (VG) in the above voltage range, it is possible to effectively implement a multi-level operation by increasing the memory margin and memory margin difference.

That is, the K and M lines of FIGS. 11 and 12 are experimental results of the present embodiment using the strained silicon as the semiconductor layer 130, and the L and N lines compared with the non-strained silicon as the semiconductor layer 130. FIG. Yes.

As shown in the result of FIG. 11, in the capacitorless memory device according to the present exemplary embodiment, even if the back bias voltage VB is changed from 5V to 20V, the memory margin is improved as compared with the comparative example. In addition, as shown in the result of FIG. 12, in the capacitorless memory device according to the present exemplary embodiment, the memory margin difference when the back bias voltage VB is changed is also improved as compared with the comparative example. That is, as shown in FIG. 12, in the comparative example, the memory margin difference between the 10 V and 5 V of the back bias voltage VB was 26.9 ms, but was 52.8 ms in this embodiment. Such a large memory margin difference facilitates the implementation of multiple levels.

In addition, it can be seen that the capacitorless memory device of this embodiment has a good data retention capability in both the front gate operation and the back gate operation.

Fig. 13 is a graph measuring the retention capability in the front gate operation of this embodiment, and Fig. 14 is a graph measuring the retention capability in the back gate operation.

13 and 14, the retention characteristics after recording '1' in the interval between 350 and 650 milliseconds were examined first. Then, the erase operation was performed between 650 milliseconds and 700 milliseconds, and the retention characteristics after recording '0' between 700 milliseconds and 1000 milliseconds were examined. In addition, the lines of FIG. 13, that is, P1, P2, P3, and P4 are the result values of applying 3V, 2.33V, 1.67V, and 1V as the gate voltage VG, respectively. Lines Q1, Q2, and Q3 in FIG. 14 are values obtained by applying 20V, 15V, and 10V to the back bias voltage VB, respectively.

Referring to the two graphs, first, as shown in FIGS. 13 and 14, the front gate and back gate operations are performed, thereby enabling a plurality of bits to be driven. In addition, multi-level driving is possible according to voltage values of the gate voltage VG and the back bias voltage VB as shown in the graphs of FIGS. 13 and 14. In addition, it can be seen that the data retention capability is excellent in the operation between '1' and '0' of the memory device.

Although the invention has been described with reference to the accompanying drawings and the preferred embodiments described above, the invention is not limited thereto, but is defined by the claims that follow. Accordingly, one of ordinary skill in the art may variously modify and modify the present invention without departing from the spirit of the following claims.

1 is a cross-sectional view of a capacitorless memory device according to an embodiment of the present invention.

2 is an experimental result of measuring the electron mobility of the capacitorless memory device of the present embodiment.

3 is a conceptual diagram illustrating an operation of a capacitorless memory device according to an exemplary embodiment.

4 and 5 are conceptual cross-sectional views for describing an operation of a capacitorless memory device according to example embodiments.

6 is a conceptual cross-sectional view illustrating a multi-bit operation of a capacitorless memory device according to an exemplary embodiment.

7 is a graph illustrating an I-V curve of a front gate operation according to an embodiment.

8 and 9 are graphs of experimental results for explaining the effect of the front gate operation according to an embodiment.

10 is a graph illustrating an I-V curve of a back gate operation according to an embodiment.

11 and 12 are graphs of experimental results for explaining an effect of a back gate operation, according to an exemplary embodiment.

Fig. 13 is a graph measuring the retention capability in the front gate operation of this embodiment.

14 is a graph measuring retention capability in backgate operation.

<Explanation of symbols for the main parts of the drawings>

110: semiconductor substrate 120: insulating layer

130: semiconductor layer 140: gate electrode portion

150: source region 160: drain region

Claims (11)

A semiconductor layer formed by depositing strained silicon on a bottom insulating layer formed on a semiconductor substrate, a gate insulating film and a gate electrode formed on the semiconductor layer, and a channel is formed in the semiconductor layer below the gate electrode; A method of driving a capacitorless memory device in which source and drain regions are formed in both semiconductor layers of the channel, Applying a gate voltage and a back bias voltage to the gate electrode and the semiconductor substrate, respectively, And a voltage having a first polarity as the gate voltage and a voltage having a second polarity different from the first polarity and having a large absolute value as the back bias voltage. The method according to claim 1, When a positive voltage is used as the gate voltage, a negative voltage whose absolute value is greater than the positive voltage of the gate voltage is used as the back bias voltage, And using a negative voltage as the gate voltage, and using a positive voltage greater than an absolute value of the negative voltage of the gate voltage as the back bias voltage. The method according to claim 2, When a positive voltage is used as the gate voltage, holes are accumulated in the channel region adjacent to the bottom insulating layer. And when a negative voltage is used as the gate voltage, holes are accumulated in a channel region adjacent to the gate insulating layer. The method according to claim 2, And using -15 to -25V as the back bias voltage when using 1 to 3V as the gate voltage. The method according to claim 2, And using 5 to 25 volts as the back bias voltage when using -0.5 to -2 volts as the gate voltage. The method according to claim 1, Multi-bit driving is performed by applying voltages having different polarities to the gate voltage and the back bias voltage, And a voltage level of the gate voltage and the back bias voltage is varied to perform multi-level driving. The method according to claim 1, Provide a ground power source to the source region to write data of '1', apply a write voltage greater than a kink voltage to the drain region, Applying an erase voltage to the drain region to erase data; And applying a read voltage between the kink voltage and the erase voltage to the drain region for data reading. In a capacitorless memory device, A semiconductor substrate receiving a back bias voltage; A gate electrode part including a gate electrode to which a gate voltage is applied, and a gate insulating layer positioned between the gate electrode and the semiconductor substrate; A bottom insulating layer on the semiconductor substrate; Located between the bottom insulating layer and the gate electrode portion, when a positive voltage is used as the back bias voltage, holes are accumulated in an area adjacent to the gate electrode portion, and when a positive voltage is used as the gate voltage. A channel made of strained silicon and having holes accumulated in an area adjacent to the bottom insulating layer; And And a source and a drain region connected to the channel at both sides of the channel. The method according to claim 8, And a semiconductor layer made of strained silicon is formed between the bottom insulating layer and the gate electrode, and the channel, source and drain regions are formed in the semiconductor layer. The method according to claim 8, And an absolute value of the voltage used as the gate voltage is smaller than an absolute value of the back bias voltage. The method according to claim 8, And a multi-bit driving by applying voltages having different polarities to the gate voltage and the back bias voltage, and performing multi-level driving by varying voltage levels of the gate voltage and the back bias voltage.

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