KR20110038335A - Drive control apparatus of pdp using phase-shift - Google Patents

Abstract

PURPOSE: A driving control device of a plasma display panel using a phase shift method is provided to generate a first switching signal in a phase shift method, thereby controlling first switching. CONSTITUTION: A PWM controller(100) generates first and second pulse signals. The first and second pulse signals include opposite phases respectively. A clock generating unit(200) generates a clock signal. The clock signal includes a clock corresponding to dead time. A maintenance circuit unit(300) outputs a first phase signal and a second phase signal. The second phase signal comprises the reversed phase of the first phase signal. A signal shifter(400) outputs the first and second shift signals. A signal generating unit(500) generates first and second signals. A signal transfer unit converts the first and second signals into first and second switching signals.

Description

DRIVE CONTROL APPARATUS OF PDP USING PHASE-SHIFT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control apparatus for a plasma display panel that can be applied to a plasma display panel (PDP) TV. Particularly, in a plasma display panel, a primary switching for converting an input DC voltage into a pulsed voltage is performed. The present invention relates to a driving control apparatus for a plasma display panel using a phase shift method capable of controlling primary switching by generating a primary switching signal for the phase shift method.

Recently, the displays that are attracting attention are liquid crystal displays (LCDs) and plasma display panels (PDPs), which have advantages of thin thickness and easy implementation of large screens. Also with respect to panels, there is a demand for lighter and thinner and lower cost.

In general, a plasma display panel TV includes a primary switching circuit, a transformer, and a rectifier to generate multi-voltage (Vm), direct current (DC) sustain voltage (Vs), and address voltage (Va) such as 15 V, 5 V, and standby voltage. A power supply unit including a power supply (SMPS), a sustain driving circuit composed of a secondary switching circuit for supplying a panel voltage (Vyx) required for driving the panel, other driving circuit portions composed of switches for forming a waveform, and an X buffer unit ( And a Y buffer unit (scan buffer unit), an image board, and a plasma display panel.

In this way, in order to reduce the cost and light weight of the plasma display panel TV, the plasma display panel TV includes a voltage generation circuit unit for generating a direct current (DC) sustain voltage (Vs) and an address voltage (Va) of the power supply unit, and a sustain driving circuit. When implementing an integrated circuit that integrates into one circuit, a control device capable of controlling the integrated circuit is required.

However, there is a problem that there is no suitable control device capable of controlling the voltage generation circuit section and the integrated circuit integrating the sustain driving circuit into one circuit.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and its object is to phase shift a primary switching signal for primary switching for converting an input DC voltage into a pulsed voltage in a plasma display panel. Drive control apparatus for a plasma display panel using a phase shift method capable of controlling primary switching by generating using the method

The first technical aspect of the present invention for achieving the above object of the present invention is the first and second pulses, which are synchronized with a predetermined synchronization signal and made up of consecutive pulses that are out of phase with each other using a phase shift. A PWM controller generating a signal; A clock generator configured to generate a clock signal having a clock corresponding to a dead time repeated between the first and second pulse signals; A holding circuit unit for outputting a first phase signal having a predetermined level of a D-input signal and a second phase signal having an inverse phase of the first phase signal when the clock signal is input; A signal shifter for outputting first and second shift signals by shifting each of the first and second phase signals by a predetermined shift time; A signal generator configured to generate first and second signals according to the first and second phase signals and the first and second shift signals; A signal transfer unit converting the first signal and the second signal into first and second switching signals; And first and second switches connected in series to the input DC voltage terminals and alternately switching to each other according to the first and second switching signals, thereby converting the input DC voltages into pulsed voltages. A drive control apparatus for a plasma display panel using a phase shift method including a primary switching circuit unit having a.

In addition, the first technical aspect of the present invention, the second first to fourth switching signal for generating the panel voltage and the sustain voltage, the synchronization signal synchronized with the first to fourth switching signal, the predetermined sustain enable A logic board unit for generating a signal and a D-input signal; A PWM control unit for generating first and second pulse signals composed of pulses which are opposite in phase to each other by using a phase shift by using the synchronization signal; A clock generator configured to generate a clock signal having a clock corresponding to a dead time repeated between the first and second pulse signals; A holding circuit unit for outputting a first phase signal having a level of the D-input signal and a second phase signal having an inverse phase of the first phase signal when the clock signal is input; A signal shifter for outputting first and second shift signals by shifting each of the first and second phase signals by a predetermined shift time; A signal generator configured to generate first and second signals according to the first and second phase signals and the first and second shift signals; A signal transfer unit converting the first signal and the second signal into first and second switching signals; And first and second switches connected in series to the input DC voltage terminals and alternately switching to each other according to the first and second switching signals, thereby converting the input DC voltages into pulsed voltages. A drive control apparatus for a plasma display panel using a phase shift method including a primary switching circuit portion having a structure is proposed.

In the first and second technical aspects of the present invention, a drive control apparatus for a plasma display panel of the present invention includes a primary coil receiving a pulsed voltage from the primary switching circuit and a pulse type of the primary coil. A resonance transformer unit having a secondary coil for converting a voltage into an alternating voltage; Secondary first and second switches connected in series between a sustain voltage terminal and a ground with respect to a first connection node connected to one end of the secondary coil of the resonant transformer part and the other ends of the secondary coil of the resonant transformer part. Secondary third and fourth switches connected in series between the sustain voltage terminal and the ground with respect to the second connection node, and using the AC voltage from the resonant transformer unit of the secondary first to fourth switches A secondary switching / sustain circuit section for generating a panel voltage through a switching operation; And a sustain capacitor for forming a sustain voltage according to the operation of the secondary switching / sustain circuit.

The PWM control unit may include a pulse generation unit generating a pulse signal synchronized with the synchronization signal; A reference signal generator for generating a triangular waveform reference signal using the synchronization signal; A first comparison unit comparing the feedback voltage with a preset reference voltage and outputting a difference signal; A second comparison unit comparing the difference signal with a reference signal to detect a pulse shift time; A pulse shifter for generating a first pulse signal by shifting the pulse signal by the pulse shift time; And an inverter configured to invert the first pulse signal to generate a second pulse signal.

The clock generation unit may include a NOR gate configured to generate a logic signal by performing an NOR operation on the first and second pulse signals from the PWM controller.

The holding circuit unit includes a clock terminal for receiving a clock signal from the clock generator, an input terminal for receiving the D-input signal, and first and second outputs for outputting the first phase signal and the second phase signal. It is characterized by consisting of a de-flip flop including a terminal.

The D-input signal is characterized in that it consists of a plurality of continuous pulses having a period not longer than the period of the synchronization signal.

The signal shifter may include a first resistor connected to a first output terminal of the sustain circuit unit, and a first capacitor connected between the first resistor and ground to shift the first phase signal by a predetermined shift time so as to shift the first phase signal. A first signal shifter for outputting one shift signal; And a second resistor connected to the second output terminal of the sustain circuit unit, and a second capacitor connected between the second resistor and the ground to shift the second phase signal from the sustain circuit unit by a predetermined shift time. And a second signal shifter for outputting two shift signals.

The signal generator may include a first NOR gate configured to perform an NOR operation on the first phase signal, the first shift signal, and a predetermined sustain enable signal to output the first signal; And a second NOR generation unit generating a second signal by performing an NOR operation on the second phase signal, the second shift signal, and the predetermined sustain enable signal.

The sustain enable signal has a high level corresponding to sustain disable for a predetermined time, and has a low level corresponding to sustain enable after a predetermined time.

The signal transmission unit is coupled to the primary coil receiving the first and second signals from the first and second noah gate, and the primary coil and the first and second signals from the primary coil And a transformer including a secondary coil for converting the primary first and second switching signals, wherein the transformer is configured to transmit the primary first and second switching signals to the primary first through the secondary coil. It is characterized by supplying to the 1st and 2nd switch.

According to the present invention, in the plasma display panel, the primary switching signal can be controlled by generating a primary switching signal for primary switching for converting an input DC voltage into a pulsed voltage by using a phase shift method. It works.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is not limited to the embodiments described, and the embodiments of the present invention are used to assist in understanding the technical spirit of the present invention. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

1 is a circuit block diagram of a drive control apparatus for a plasma display panel according to the present invention.

Referring to FIG. 1, a driving control apparatus for a plasma display panel according to an embodiment of the present invention may include first and second pulses which are synchronized with a preset synchronization signal Sync, and which are composed of pulses which are opposite in phase to each other using a phase shift. Clock generating clock signal (SCLK) having a clock corresponding to the dead time repeated between the PWM control unit 100 for generating pulse signals (SP1, SP2) and the first and second pulse signals (SP1, SP2) When the generation unit 200 and the clock signal SCKL are input, a first phase signal SQ1 having a predetermined level of the D-input signal SDI, and an inverse phase of the first phase signal SQ1 are determined. The holding circuit unit 300 for outputting the second phase signal SQ2 having the first and second phase signals SQ1 and SQ2 is shifted by a predetermined shift time TD to thereby first and second shift signals. And a first shift signal according to the signal shifter 400 and the first phase signal SQ1 and the first shift signal. And a signal generator 500 for generating a second signal according to the second phase signal SQ2 and the second shift signal, and the first signal SR and the second signal SF. The signal transmission unit 600 converting the first and second switching signals SS11 and SS12 and the input DC voltage VPFC terminal are connected in series to each other, and the first and second switching signals SS11 are connected in series. And a primary switching circuit part 10 having primary first and second switches S11 and S12 that switch alternately with each other according to SS12 to convert an input DC voltage VPFC into a pulsed voltage. Can be.

On the other hand, the driving control apparatus of the plasma display panel of the present invention, the second first to fourth switching signals (SS21-SS24) and the first to fourth switching signals (SS21-SS24) for generating the panel voltage and the sustain voltage ) May include a logic board unit 50 for generating a synchronization signal Sync, a preset sustain enable signal SSE, and a D-input signal SDI. Alternatively, the driving control apparatus of the plasma display panel of the present invention may be applied to the plasma display panel including the logic board unit 50.

In addition, the driving control apparatus of the plasma display panel according to the present invention includes a primary coil receiving the pulsed voltage from the primary switching circuit unit 10 and two for converting the pulsed voltage of the primary coil into an alternating voltage. It may include a resonant transformer portion 20 having a difference coil.

In this case, the resonant transformer 20 includes a resonant inductor Lr and a resonant capacitor Cr connected in series with the primary coil. here. The resonant inductor Lr and the resonant capacitor Cr, together with the capacitor of the panel at P, cause resonance in synchronization with the synchronization signal Sync, thereby contributing to the potential change of the PDS panel, which is required by the PDS panel. The formation of the driving voltage Vyx is influenced.

The driving control apparatus of the plasma display panel of the present invention is connected in series between the sustain voltage (Vs) terminal and the ground with respect to the first connection node (N1) connected to one end of the secondary coil of the resonant transformer unit (20). Between the secondary first and second switches S21 and S22 and the second connection node N2 connected to the other end of the secondary coil of the resonant transformer unit 29 between the sustain voltage Vs terminal and the ground. Secondary third and fourth switches S23 and S24 connected in series, and using the AC voltage from the resonant transformer unit 20 of the secondary first to fourth switches S21 to S24. It may include a secondary switching / sustain circuit unit 30 for generating a panel voltage (Vyx) through a switching operation.

In addition, the driving control apparatus of the plasma display panel of the present invention may include a sustain capacitor Co for forming a sustain voltage according to the operation of the secondary switching / sustain circuit unit 30.

In this case, the secondary first to fourth switching signals SS21 to SS24, which may be provided by the logic board unit 50, are coupled to the synchronization signals Sync together with the primary switching signals S11 and S12. Therefore, the resonance is caused by the resonance inductor Lr, the resonance capacitor Cr and the capacitor of the PDP panel, and the secondary switches S21-S24 and the primary switches S11 and S12 are synchronized with each other. It operates in synchronization with.

In addition, the present invention may include a feedback circuit unit 60 for detecting the feedback voltage VFB from the voltage of the sustain capacitor Co.

2 is a circuit configuration diagram of the PWM control unit of the present invention.

Referring to FIG. 2, the PWM controller 100 may include a pulse generator 110 generating a pulse signal synchronized with the synchronization signal Sync, and a reference signal having a triangular waveform by using the synchronization signal Sync. A reference signal generator 120 generating SREF, a first comparator 130 comparing the feedback voltage VFB with a predetermined reference voltage Vref, and outputting a difference signal F / B; A second comparator 140 for detecting a pulse shift time TS by comparing the difference signal F / B with a reference signal SREF; and the pulse signal SP by the pulse shift time TS. May include a pulse shifter 150 for generating a first pulse signal SP1 by shifting the pulse shifter, and an inverter 160 for generating a second pulse signal SP2 by inverting the first pulse signal SP1. .

In addition, referring to FIG. 1, the clock generation unit 200 generates the clock signal SCLK by performing an NOR operation on the first and second pulse signals SP1 and SP2 from the PWM controller 100. It may be made of a NOR gate.

)를 포함하는 디-플립플롭으로 이루어질 수 있다.The holding circuit unit 300 may include a clock terminal CLK for receiving the clock signal SCKL from the clock generator 200, an input terminal D for receiving the D-input signal SDI, and First and second output terminals Q, which output the first phase signal SQ1 and the second phase signal SQ2,

It may be made of a de-flip flop containing a).

Here, the D-input signal SDI may be provided by the logic board unit 50 and may include a plurality of continuous pulses having a period not longer than the period of the synchronization signal Sync.

)에 연결된 제2 저항과, 이 제2 저항과 접지 사이에 연결된 제2 커패시터로 이루어져, 상기 유지회로부(300)로부터의 제2 위상 신호(SQ2)를 기설정된 시프트 시간(TD) 만큼 시프트시켜 상기 제2 시프트 신호(SD2)를 출력하는 제2 신호 시프터(420)를 포함할 수 있다.The signal shifter 400 includes a first resistor connected to the first output terminal Q of the sustain circuit unit 300, and a first capacitor connected between the first resistor and the ground, and the first phase signal ( A first signal shifter 410 for outputting the first shift signal SD1 by shifting SQ1 by a predetermined shift time TD, and a second output terminal of the sustain circuit unit 300;

And a second capacitor connected between the second resistor and ground, and shifting the second phase signal SQ2 from the holding circuit unit 300 by a predetermined shift time TD. The second signal shifter 420 may output a second shift signal SD2.

The signal generator 500 outputs the first signal SR by performing an NOR operation on the first phase signal SQ1, the first shift signal, and a predetermined sustain enable signal SSE. Generating a second signal SF by performing an NOR operation on a NOR gate 510, the second phase signal SQ2, the second shift signal, and a predetermined sustain enable signal SSE. 2 may include a NOR generation unit 520.

The sustain enable signal SSE may be provided from the logic board unit 50 and has a high level corresponding to sustain disable for a preset time, and then corresponds to a low signal for sustain enable after a preset time. It can be set to have a level.

The signal transmitter 600 is electromagnetically coupled to the primary coil receiving the first and second signals SR and SF from the first and second Noah gates 510 and 520, and the primary coil. The first and second signals SR and SF from the primary coil may be formed of a transformer including a secondary coil that converts the first and second switching signals SS11 and SS12.

Accordingly, the transformer may supply the primary first and second switching signals SS11 and SS12 to the primary first and second switches S11 and S12 through the secondary coil.

3 is an important signal timing chart of the drive control apparatus of the plasma display panel of the present invention. In FIG. 3, SS21, SS22, SS23, and SS24 are provided by the logic board unit 50 to control the secondary first to fourth switches S21-S24 of the secondary switching / sustain circuit unit 30. Difference first through fourth switching signals.

Sync is a synchronization signal provided by the logic board unit 50 and synchronized with the secondary first to fourth switching signals SS21 to SS24. In the SREF, a triangular waveform input to the second comparator 140 of the PWM controller 100 is a reference signal. TS is a pulse shift time detected by the second comparator 140. SP is a pulse signal generated by the pulse generator 110. SP1 and SP2 are first and second pulse signals output from the pulse shifter 150 and the inverter 160 in synchronization with the synchronization signal Sync provided from the logic board unit 50.

SCLK is a clock signal output from the clock generator 200. SSE is a sustain enable signal that may be provided by the logic board unit 50. SDI may be provided by the logic board unit 50 and is a D-input signal input to the holding circuit unit 300. SQ1 and SQ2 are first and second first phase signals output from the holding circuit unit 300. SD1 and SD2 are first and second shift signals output from the signal shifter 400. SR and SF are first and second signals output from the signal generator 500. Vyx is a panel voltage applied to both ends of the panel.

Hereinafter, the operation and effects of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIGS. 1 to 3, a driving control apparatus for a plasma display panel according to the present invention will be described first. Referring to FIG. The first and second pulse signals SP1 and SP2 which are synchronized with the set synchronization signal Sync and which are in phase with each other and are successively generated are output to the clock generator 200 by using a phase shift. .

The clock generation unit 200 detects a dead time repeatedly present between the first and second pulse signals SP1 and SP2 and includes a clock corresponding to the detected dead time. The clock signal SCLK is generated and output to the sustain circuit unit 300.

When the clock signal SCKL is input, the holding circuit unit 300 has a first phase signal SQ1 having a level of a predetermined D-input signal SDI and an inverse phase of the first phase signal SQ1. A second phase signal SQ2 having a generated is generated and output to the signal shifter 400 and the signal generator 500, respectively.

In this case, the signal shifter 400 generates the first and second shift signals SD1 and SD2 by shifting each of the first and second phase signals SQ1 and SQ2 by a predetermined shift time TD. Output to unit 500.

The signal generator 500 generates a first signal SR according to the first phase signal SQ1 and the first shift signal, and generates the first signal SR to the second phase signal SQ2 and the second shift signal. Accordingly, the second signal SF is generated and output to the signal transmitter 600.

The signal transmission unit 600 converts the first signal SR and the second signal SF into first and second switching signals SS11 and SS12 and supplies them to the primary switching circuit unit 10. do.

Meanwhile, when the driving control apparatus of the plasma display panel includes the logic board unit 50, the logic board unit 50 is configured to generate a preset sync signal, a panel voltage, and a sustain voltage. The first to fourth switching signals SS21 to SS24 synchronized with the synchronization signal Sync, a preset sustain enable signal SSE, and a D-input signal SDI may be provided.

As shown in FIG. 3, the sustain enable signal SSE has a high level corresponding to sustain disable for a predetermined time after driving, and a low level corresponding to sustain enable after a predetermined time. It can be set to have. The D-input signal SDI is required to generate a first phase signal SQ1 together with the clock signal SCKL, and has a plurality of continuous pulses having a period not longer than a period of the synchronization signal Sync. It may be made of.

In the primary switching circuit unit 10, the primary first and second switches S11 and S12 connected in series to an input DC voltage VPFC terminal are connected to the primary first and second switching signals SS11, Switching operation alternately with each other according to SS12) to convert the input DC voltage VPFC into a pulsed voltage.

For example, when the first and second switches S11 and S12 are turned on and off, the input voltage VPFC is supplied to the transformer TF of the resonant transformer unit 20 in the forward direction. When the first and second switches S11 and S12 are turned off and on, current flows in the reverse direction by the energy accumulated in the transformer TF of the resonance type transformer unit 20. By this operation, the input DC voltage can be converted into a pulsed voltage.

Next, the resonant transformer unit 20 converts the pulsed voltage from the primary switching circuit unit 10 input to the primary coil into a secondary voltage by converting the pulsed voltage of the primary coil into an alternating voltage. Through the output to the secondary switching / sustain circuit unit 30.

In the secondary switching / sustain circuit section 30, a switching operation of the secondary first to fourth switches S21 to S24, that is, a pair of first switches, using an AC voltage from the resonance transformer section 20 The first and fourth switches S21 and S24 and the pair of second and third switches S22 and S23 alternately turn on or off in pairs to generate the panel voltage Vyx of the PDP panel 40. do.

In addition, the sustain capacitor Co of the present invention forms the sustain voltage Vs according to the operation of the secondary switching / sustain circuit section 30.

Meanwhile, referring to FIGS. 1 to 3, the process of generating the panel voltage Vyx of the PDP panel 40 will be briefly described by dividing the operation mode 0 (M0) to the operation mode 8 (M8). .

First, in the operation mode 0 (M0), the primary first switch S11 is in the on state, the secondary second and third switches SS22 and SS23 are in the on state, and the primary direction of the transformer unit 20 is in the forward direction. As the current increases linearly, energy build-up is performed to increase the panel voltage Vyx, and the sustain capacitor Co is reversed through the second and third switches S22 and S23. A path is formed to be in a discharged state, and the panel voltage Vyx is not yet increased (transformer-panel-sustain capacitor: builder-discharge-hold).

Next, in the operation mode 1 (M1), the primary first switch (S11) is on, the secondary first to fourth switches (SS21-SS24) are all off, and the primary of the transformer unit 20 The linear current increases further linearly, together with the resonance of the panel capacitor and the resonance capacitor Cr in the resonant inductor Lr and P, the panel voltage Vyx is raised, and in the sustain capacitor Co, both are off. The circuit loop is blocked by the secondary first to fourth switches, so that no current flows. At this time, the sustain voltage Vs of the sustain capacitor Co is maintained, and the panel voltage Vyx starts to rise. (Transformer-panel-sustain capacitor: transfer energy-hold-potential change).

Next, in operation mode 2 (M2), the difference from the operation mode 1 is the change of the switching state of the first order, that is, the primary first and second switches S11 and S12 are both off and the primary second switch ( A primary current loop is formed through the body diode of S12, and the forward current decreases at the primary of the transformer unit 20 (since there is no energy source), and at this time, the panel voltage Vyx rises to the highest point ( Transformer-Panel-Sustain Capacitor: Energy Transfer-Maintain- Potential Change).

Next, in the operation mode 3 (M3), the primary second switch S12 is in the on state, the secondary first and fourth switches SS21 and S24 are in the on state, and the primary part of the transformer unit 20 is turned on. The forward current decreases further (because there is no energy source), the panel voltage Vyx reaches the sustain voltage Vs, and in the sustain capacitor Co, the secondary first and fourth switches S21 and S24 are A forward current flows through it, and at this time, the sustain voltage Vs of the sustain capacitor Co is charged and the panel voltage Vyx is maintained at the highest point (transformer-panel-sustain capacitor: energy transfer-charge). -maintain).

Next, in the operation mode 4 (M4), the primary second switch S12 is in the on state, the secondary first and fourth switches SS21 and S24 are in the on state, and the primary portion of the transformer unit 20 is turned on. The reverse current starts to flow, the panel voltage Vyx is maintained while reaching the sustain voltage Vs, and the sustain capacitor Co passes the reverse current through the secondary first and fourth switches S21 and S24. In this case, the sustain voltage (Vs) of the sustain capacitor (Co) is discharged, and the panel voltage (Vyx) is maintained at the highest point (transformer-panel-sustain capacitor: builder). Up-discharge-maintain).

Next, in the operation mode 5 (M5), the primary second switch (S12) is in the on state, the secondary first to fourth switches (SS21-SS24) are all in the off state, the primary of the transformer unit 20 The reverse current increases further linearly, and together with the resonant inductor Lr and P, the panel capacitor and the resonant capacitor Cr resonate, so that the panel voltage Vyx falls, and both of the sustain capacitor Co are off. No current flows because of separation by the secondary first to fourth switches. At this time, the sustain voltage Vs of the sustain capacitor Co is maintained, and the panel voltage Vyx starts to fall (transformer). -Panel-Sustain Capacitor: Energy Transfer-Maintain-Potential Change).

Next, in operation mode 6 (M6), the difference from the operation mode 5 is the change of the switching state of the first order, that is, the primary first and second switches S11 and S12 are both off and the primary first switch ( A primary current loop is formed through the body diode of S11, and the reverse current is reduced (as an energy source is supplied) to the primary of the transformer unit 20, and at this time, the panel voltage Vyx drops to the lowest point. (Transformer-Panel-Sustain Capacitor: Energy Transfer-Stop-Change Potential).

Next, in the operation mode 7 (M7), the primary first switch S11 is in the on state, the secondary second and third switches SS22 and SS23 are in the on state, and are reverse to the primary of the transformer unit 20. Energy transfer is performed by linearly decreasing current, and the sustain capacitor Co forms a forward current path through the secondary second and third switches S22 and S23 to be in a charged state, thereby providing the panel voltage Vyx. ) Is the state where the descent stops and remains (transformer-panel-sustain capacitor: energy transfer-charge-sustain).

In operation mode 8 (M8), the primary first switch S11 is in an on state, the secondary second and third switches SS22 and SS23 are in an on state, and the primary direction of the transformer unit 20 is forward. As the current increases linearly, energy build-up is performed to increase the panel voltage Vyx, and the sustain capacitor Co is reversed through the second and third switches S22 and S23. A path is formed to be in a discharged state, and the panel voltage Vyx is not maintained yet. This operation mode 8 is the same operation mode as the operation mode 0, and the operation mode is repeated in this way (transformer-panel-sustain capacitor: builder up-discharge-hold).

For the operation of the primary switching circuit section 10, the resonant transformer section 20, the secondary switching / sustain circuit section 30, and the sustain capacitor Co of the present invention described above, previously described

It is described in detail in Application No. 10-2009-0062944.

Hereinafter, the PWM controller 100, the clock generator 200, the sustain circuit 300, the signal shifter 400, the signal generator 500, and the signal transmitter 600 according to the present invention will be described in more detail.

Referring to FIG. 2, the pulse generator 110 of the PWM controller 100 generates a pulse signal synchronized with the synchronous signal Sync and outputs the pulse signal to the pulse shifter 150.

In addition, as shown in FIG. 1, the reference signal generator 120 of the PWM controller 100 generates a triangular waveform reference signal SREF using the synchronization signal Sync to generate a second comparison unit. Output to 140. The first comparator 130 of the PWM controller 100 compares the feedback voltage VFB input through the inverting terminal with a preset reference voltage Vref input through the non-inverting terminal, and thus the reference voltage. The difference signal F / B corresponding to the difference voltage between Vref and the feedback voltage VFB is output to the second comparator 140.

The second comparison unit 140 compares the difference signal F / B input through the non-inverting terminal and the reference signal SREF input through the inverting terminal, so that the reference signal SREF is equal to the difference. When it is lower than the signal F / B, the pulse shift time TS having a high level is detected and output to the pulse shifter 150.

The pulse shifter 150 generates the first pulse signal SP1 by shifting the pulse signal SP by the pulse shift time TS, and outputs the first pulse signal SP1. Inverting SP1) generates and outputs a second pulse signal SP2.

In addition, referring to FIG. 1, when the clock generation unit 200 includes a NOR gate, the NOR gate of the clock generation unit 200 may include a first gate from the PWM control unit 100. And a negative OR operation on the second pulse signals SP1 and SP2 to generate the clock signal SCLK. That is, the NOR gate generates a clock signal having a clock corresponding to a dead time between the first and second pulse signals SP1 and SP2.

)를 통해 출력한다.When the sustain circuit unit 300 is a de-flip flop, the de-flip flop of the sustain circuit unit 300 is input whenever the clock signal SCKL from the clock generator 200 is input. Outputs a first phase signal SQ1 having a level of the D-input signal SDI input through the first output terminal Q, and has a reverse phase of the first phase signal SQ1. 2 phase signal SQ2 to the second output terminal (

)

Here, as described above, the D-input signal SDI may be provided by the logic board unit 50 and may include a plurality of continuous pulses having a period not longer than the period of the synchronization signal Sync. Can be.

1, when the signal shifter 400 includes a first signal shifter 410 and a second signal shifter 420, the first signal shifter 410 may include the first phase signal. The first shift signal SD1 is output to the signal generator 500 by shifting SQ1 by a predetermined shift time TD.

The second signal shifter 420 shifts the second phase signal SQ2 from the holding circuit unit 300 by a predetermined shift time TD to convert the second shift signal SD2 into a signal generator. Output to 500.

When the signal generator 500 includes a first NOR gate 510 and a second NOR gate 520, the first NOR gate 510 is the first NOR gate 510. The first signal SR is output by performing an NOR operation on a phase signal SQ1, the first shift signal, and a predetermined sustain enable signal SSE.

The second NOR gate 520 may perform an NOR operation on the second phase signal SQ2, the second shift signal, and the predetermined sustain enable signal SSE to perform a negative OR operation on the second signal SF. )

Here, as described above, the sustain enable signal SSE may be provided by the logic board unit 50 and has a high level corresponding to sustain disable for a preset time, and after the preset time. It may be set to have a low level corresponding to the sustain enable.

Next, the signal transmission unit 600 may be formed of, for example, a transformer. In this case, the transformer of the signal transmission unit 600 may include the first and the first signals from the first NOR gate 510 through a primary coil. The first and second signals SR and SF are received from the primary coil through a secondary coil electromagnetically coupled with the primary coil. The second switching signals SS1 and SS2 are converted and supplied to the primary first and second switches S11 and S12 of the primary switching circuit unit 10.

According to the present invention as described above, a phase shift method is used for a voltage generation circuit for generating a direct current (DC) sustain voltage and an address voltage in a plasma display panel (PDP) and an integrated circuit in which a sustain driving circuit is integrated. By generating a primary switching signal to control the primary switch of the integrated circuit, in this primary switching operation, having a dead time for a smooth switching operation, the primary switching operation can be made smoothly There is.

1 is a circuit block diagram of a drive control apparatus for a plasma display panel according to the present invention.

2 is a circuit configuration diagram of a PWM control unit of the present invention.

3 is an important signal timing chart of a drive control device for a plasma display panel of the present invention.

Explanation of symbols on the main parts of the drawings

10: primary switching circuit section 20: resonant transformer section

30: secondary switching / sustain circuit section 40: PDP panel

50: logic board portion 60: feedback circuit portion

100: PWM controller 110: pulse generator

120: reference signal generation unit 130: first comparison unit

140: second comparison unit 150: pulse shifter

160: inverter 200: clock generator

300: holding circuit portion 400: signal shifter

410: first signal shifter 420: second signal shifter

500: signal generator 510: first NOR gate

520: second NOR generation unit 600: signal transmission unit

Co: Sustain Capacitor

Claims (20)

A PWM control unit synchronized with a preset synchronization signal and using the phase shift to generate first and second pulse signals composed of pulses that are opposite in phase and continuous to each other; A clock generator configured to generate a clock signal having a clock corresponding to a dead time repeated between the first and second pulse signals; A holding circuit unit for outputting a first phase signal having a predetermined level of a D-input signal and a second phase signal having an inverse phase of the first phase signal when the clock signal is input; A signal shifter for outputting first and second shift signals by shifting each of the first and second phase signals by a predetermined shift time; A signal generator configured to generate first and second signals according to the first and second phase signals and the first and second shift signals; A signal transfer unit converting the first signal and the second signal into first and second switching signals; And It is connected to the input DC voltage terminal in series with each other, and has a first switch and the first switch to switch the input DC voltage into a pulse type voltage alternately switching with each other according to the first and second switching signal Primary switching circuit section Driving control apparatus for a plasma display panel using a phase shift method comprising a. The method of claim 1, A resonant transformer unit having a primary coil receiving the pulsed voltage from the primary switching circuit unit and a secondary coil converting the pulsed voltage of the primary coil into an alternating voltage; Secondary first and second switches connected in series between a sustain voltage terminal and a ground with respect to a first connection node connected to one end of the secondary coil of the resonant transformer part and the other ends of the secondary coil of the resonant transformer part. Secondary third and fourth switches connected in series between the sustain voltage terminal and the ground with respect to the second connection node, and using the AC voltage from the resonant transformer unit of the secondary first to fourth switches A secondary switching / sustain circuit section for generating a panel voltage through a switching operation; And Sustain capacitor for forming a sustain voltage according to the operation of the secondary switching / sustain circuit Driving control apparatus for a plasma display panel using a phase shift method further comprising. The method of claim 2, wherein the PWM control unit, A pulse generator for generating a pulse signal synchronized with the synchronization signal; A reference signal generator for generating a triangular waveform reference signal using the synchronization signal; A first comparison unit comparing the feedback voltage with a preset reference voltage and outputting a difference signal; A second comparison unit comparing the difference signal with a reference signal to detect a pulse shift time; A pulse shifter for generating a first pulse signal by shifting the pulse signal by the pulse shift time; And An inverter that inverts the first pulse signal to generate a second pulse signal Drive control apparatus for a plasma display panel using a phase shift method, characterized in that it comprises a. The clock generator of claim 3, wherein the clock generator comprises: And a NOR gate for generating the clock signal by performing an NOR operation on the first and second pulse signals from the PWM control unit. The method of claim 4, wherein the holding circuit portion, A clock terminal for receiving a clock signal from the clock generator, an input terminal for receiving the D-input signal, and first and second output terminals for outputting the first phase signal and the second phase signal; A drive control apparatus for a plasma display panel using a phase shift method, characterized in that it is made of a flip flop. The method of claim 5, wherein the D-input signal, And a plurality of continuous pulses having a period not longer than the period of the synchronization signal. The method of claim 5, wherein the signal shifter, And a first resistor connected to the first output terminal of the sustain circuit unit, and a first capacitor connected between the first resistor and the ground to shift the first phase signal by a predetermined shift time to output the first shift signal. A first signal shifter; And And a second resistor connected to the second output terminal of the sustain circuit portion, and a second capacitor connected between the second resistor and the ground to shift the second phase signal from the sustain circuit portion by a predetermined shift time. Second signal shifter for outputting a shift signal Drive control apparatus for a plasma display panel using a phase shift method, characterized in that it comprises a. The method of claim 7, wherein the signal generator, A first NOR gate outputting the first signal by performing an NOR operation on the first phase signal, the first shift signal, and a predetermined sustain enable signal; And A second NOR generation unit generating a second signal by performing an NOR operation on the second phase signal, the second shift signal, and a predetermined sustain enable signal; Drive control apparatus for a plasma display panel using a phase shift method, characterized in that it comprises a. The method of claim 8, wherein the sustain enable signal, And a high level corresponding to sustain disable for a predetermined time, and a low level corresponding to sustain enable after a predetermined time. The method of claim 8, wherein the signal transmission unit A primary coil receiving first and second signals from the first and second noah gates, and electromagnetic coupling with the primary coil to receive first and second signals from the primary coil; A transformer comprising a secondary coil for converting the first and second switching signals, The transformer supplies the primary first and second switching signals to the primary first and second switches via the secondary coil. A drive control apparatus for a plasma display panel using a phase shift method. Logic board unit for generating second first to fourth switching signals for generating panel voltage and sustain voltage, a synchronization signal synchronized with the first to fourth switching signals, a predetermined sustain enable signal, and a D-input signal ; A PWM control unit for generating first and second pulse signals composed of pulses which are opposite in phase to each other by using a phase shift by using the synchronization signal; A clock generator configured to generate a clock signal having a clock corresponding to a dead time repeated between the first and second pulse signals; A holding circuit unit for outputting a first phase signal having a level of the D-input signal and a second phase signal having an inverse phase of the first phase signal when the clock signal is input; A signal shifter for outputting first and second shift signals by shifting each of the first and second phase signals by a predetermined shift time; A signal generator configured to generate first and second signals according to the first and second phase signals and the first and second shift signals; A signal transfer unit converting the first signal and the second signal into first and second switching signals; And It is connected to the input DC voltage terminal in series with each other, and has a first switch and the first switch to switch the input DC voltage into a pulse type voltage alternately switching with each other according to the first and second switching signal Primary switching circuit section Driving control apparatus for a plasma display panel using a phase shift method comprising a. The method of claim 11, A resonant transformer unit having a primary coil receiving the pulsed voltage from the primary switching circuit unit and a secondary coil converting the pulsed voltage of the primary coil into an alternating voltage; Secondary first and second switches connected in series between a sustain voltage terminal and a ground with respect to a first connection node connected to one end of the secondary coil of the resonant transformer part and the other ends of the secondary coil of the resonant transformer part. Secondary third and fourth switches connected in series between the sustain voltage terminal and the ground with respect to the second connection node, and using the AC voltage from the resonant transformer unit of the secondary first to fourth switches A secondary switching / sustain circuit section for generating a panel voltage through a switching operation; And Sustain capacitor for forming a sustain voltage according to the operation of the secondary switching / sustain circuit Driving control apparatus for a plasma display panel using a phase shift method further comprising. The method of claim 12, wherein the PWM control unit, A pulse generator for generating a pulse signal synchronized with the synchronization signal; A reference signal generator for generating a triangular waveform reference signal using the synchronization signal; A first comparison unit comparing the feedback voltage with a preset reference voltage and outputting a difference signal; A second comparison unit comparing the difference signal with a reference signal to detect a pulse shift time; A pulse shifter for generating a first pulse signal by shifting the pulse signal by the pulse shift time; And An inverter that inverts the first pulse signal to generate a second pulse signal Drive control apparatus for a plasma display panel using a phase shift method, characterized in that it comprises a. The clock generator of claim 13, wherein the clock generator comprises: And a NOR gate configured to generate the clock signal by performing an NOR operation on the first and second pulse signals from the PWM control unit. The method of claim 14, wherein the holding circuit portion, A clock terminal for receiving a clock signal from the clock generator, an input terminal for receiving the D-input signal, and first and second output terminals for outputting the first phase signal and the second phase signal; A drive control apparatus for a plasma display panel using a phase shift method, characterized in that it is made of a flip flop. The method of claim 15, wherein the D-input signal, And a plurality of continuous pulses having a period not longer than the period of the synchronization signal. The method of claim 15, wherein the signal shifter, And a first resistor connected to the first output terminal of the sustain circuit unit, and a first capacitor connected between the first resistor and the ground to shift the first phase signal by a predetermined shift time to output the first shift signal. A first signal shifter; And And a second resistor connected to the second output terminal of the sustain circuit portion, and a second capacitor connected between the second resistor and the ground to shift the second phase signal from the sustain circuit portion by a predetermined shift time. Second signal shifter for outputting a shift signal Drive control apparatus for a plasma display panel using a phase shift method, characterized in that it comprises a. The method of claim 17, wherein the signal generator, A first NOR gate outputting the first signal by performing an NOR operation on the first phase signal, the first shift signal, and a predetermined sustain enable signal; And A second NOR generation unit generating the second signal by performing an NOR operation on the second phase signal, the second shift signal, and a predetermined sustain enable signal; Drive control apparatus for a plasma display panel using a phase shift method, characterized in that it comprises a. The method of claim 18, wherein the sustain enable signal, And a high level corresponding to sustain disable for a predetermined time, and a low level corresponding to sustain enable after a predetermined time. The method of claim 18, wherein the signal transmission unit A primary coil receiving first and second signals from the first and second noah gates, and electromagnetic coupling with the primary coil to receive first and second signals from the primary coil; A transformer comprising a secondary coil for converting the first and second switching signals, The transformer supplies the primary first and second switching signals to the primary first and second switches via the secondary coil. A drive control apparatus for a plasma display panel using a phase shift method.

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