KR20110034561A - Dual-pore structure polishing pad - Google Patents

Abstract

PURPOSE: A polishing pad of a dual-void structure is provided to reduce defects caused by pads and increase polishing speed. CONSTITUTION: A polishing pad of a dual-void structure comprises a porous polishing layer. The porous polishing layer has a dual-void structure in a polyurethane matrix. The dual-void structure is formed of primary and secondary sets of voids. The void wall of the first set of the void has the thickness of 15~55 micron meters and storage modulus of 10~60 MPa. The second set of the void has the average size of 5~30 micron meters of void. The porous polishing layer is fixed to a polymeric film or a sheet substrate or is formed in woven or non-woven structure.

Description

DUAL-PORE STRUCTURE POLISHING PAD

The present invention is directed to porous polyurethane polishing pads useful for polishing one or more of magnetic, optical and semiconductor substrates. For example, polishing pads are particularly useful for chemical mechanical polishing (CMP) of semiconductor wafer materials and, more particularly, low defect polishing methods of semiconductor substrates.

Semiconductor fabrication typically involves several chemical mechanical polishing (CMP) processes. In each CMP process, the polishing pad, along with a polishing solution such as a abrasive-containing abrasive slurry or a abrasive-free reactive liquid, then removes excess material in a manner that flattens or maintains flatness to accept the layer. The stack of these layers combines in a manner that forms an integrated circuit. The manufacture of these semiconductor devices continues to be more complicated because of the need for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device structure, this translates to more precise linewidth geometry and increased number of metallization levels. These increasingly stringent device design requirements lead to the adoption of smaller and smaller line spacings with corresponding pattern density increases. The ever-increasing scale and increased complexity of the devices has led to greater demand for CMP consumables such as polishing pads and polishing solutions. In addition, as the linewidth size of integrated circuits decreases, defects caused by CMP, such as scratches, become a greater problem. In addition, reducing film thickness of integrated circuits requires defect improvement and at the same time provides acceptable topography for wafer substrates; These topography requirements call for even more stringent flatness, line dishing and small linewidth array erosion polishing specifications. In addition, higher removal rates are required to improve the throughput of the wafer, and the relative removal rates of metal to dielectric materials are important because the metal and dielectric materials are polished simultaneously. In order to meet the needs of future wafer integration, higher dielectric (eg, TEOS) to metal (eg, copper) removal rate selectivity is required.

Historically, cast polyurethane polishing pads have provided mechanical integrity and chemical resistance to most polishing operations used in integrated circuit fabrication. For example, polyurethane polishing pads may have sufficient tensile strength and elongation to resist tearing; Wear resistance to avoid wear problems during polishing; And stability to resist attack by strong acidic and strong corrosive polishing solutions. IC1000 ^TM supplied by Dow Electronic Materials Polishing pads represent industry standard polyurethane polishing pads suitable for polishing multiple substrates, such as aluminum, barrier materials, dielectrics, copper, hard masks, low-k dielectrics, tungsten, and very low-k dielectrics (IC1000 is a Dow electronic material Reals or its affiliates).

Over the past few years, semiconductor manufacturers have gone increasingly shifted much of a porous polishing pad, for example, the Polytechnic's ^TM (Politex ^TM) polyurethane pads for the finishing or final polishing requirements are low defect more important needs (Polytechnic seuneun Dow Electronic meote Real Z or its affiliates). For the purpose of this specification, the term porous refers to a porous polyurethane polishing pad produced in an aqueous or non-aqueous solution. The advantage of these polishing pads is that they have low defects and provide effective removal. This reduction in defects can lead to significant wafer yield increases.

Particularly important polishing applications are copper-barrier polishing, which requires low defects with the ability to simultaneously remove both copper and TEOS dielectrics, allowing the TEOS removal rate to be faster than the copper removal rate to meet improved wafer integration designs. Commercial pads, such as polytex polishing pads, do not have defects low enough for future designs, and the TEOS: Cu selectivity is not high enough. Other commercial pads contain surfactants that leach during polishing, producing excess foam that interferes with polishing. Moreover, surfactants may contain alkali metals that can contaminate the dielectric and reduce the functional performance of the semiconductor.

Despite the low TEOS removal rate associated with porous polishing pads, some improved polishing applications have all-porous because of the potential for porous pads to achieve lower defects compared to other pad types, such as the IC1000 polishing pad. poromeric) pad (CMP) polishing process. Although these processes provide low defects, additional challenges remain to reduce pad-induced defects and increase the polishing rate.

One aspect of the invention is that the porous abrasive layer has a double pore structure in the polyurethane matrix, the double pore structure has a primary set of pores, the primary set of pores has a pore wall, and the pore walls have 15 Having a storage modulus of 10 to 60 MPa as measured at 25 ° C., thickness of from 55 μm, containing a secondary set of voids in the void walls, the secondary set of voids having an average pore size of 5 to 30 μm Polishing useful for polishing one or more of magnetic, optical and semiconductor substrates comprising a porous polishing layer, wherein the porous polishing layer is secured to the polymerizable film or sheet substrate or formed in a woven or nonwoven structure to form a polishing pad. Provide pads.

Another aspect of the invention is that the porous abrasive layer has a double pore structure in the polyurethane matrix, the double pore structure has a primary set of pores, the primary set of pores has a pore wall and an average diameter of at least 40 μm, The pore wall has a thickness of 20 to 50 μm, a storage modulus of 10 to 50 MPa as measured at 25 ° C., contains a secondary set of pores in the pore wall, and the secondary set of pores has an average of 5 to 25 μm. At least one of magnetic, optical and semiconductor substrates comprising a porous abrasive layer having a pore size, wherein the porous abrasive layer is secured to the polymerizable film or sheet substrate or formed in a woven or nonwoven structure to form a polishing pad. Provided are polishing pads useful for polishing.

The polishing pad of the present invention provides various advantages that are not achieved by conventional porous polishing pads. For example, the dual porosity of the polishing pad facilitates high TEOS removal rates and high TEOS: Cu removal rate selectivity with low defects. In addition, dual porosity polishing pads require reduced break-in and provide a stable removal rate; Along with these stable speeds, reduced conditioning is achieved. The pad provides a good lifetime of 1,000 wafers with limited wear. Moreover, woven and nonwoven substrates provide excellent interlayer adhesion and eliminate air entrainment. Finally, the polishing pad is surfactant-free and can be foamed during polishing, or dispersed into dielectrics and low-k dielectrics, providing no alkali metals that interfere with polishing.

The polishing pad of the present invention is useful for polishing one or more of magnetic, optical and semiconductor substrates. In particular, polyurethane pads are useful for polishing semiconductor wafers; In particular, pads are more important than improved applications, such as the ability to planarize very low defects, and include, but are not limited to, multiple materials such as copper, barrier materials and TEOS, low k and very low k dielectrics. It is useful for polishing copper-barrier applications where it is necessary to simultaneously remove them. For the purposes of this specification, "polyurethane" is derived from difunctional or polyfunctional isocyanates such as polyetherureas, polyisocyanurates, polyurethanes, polyureas, polyurethaneureas, copolymers thereof and mixtures thereof. Product. In order to avoid foaming problems and the possibility of contamination of the dielectric, these agents are advantageously surfactant-free agents. The polishing pad includes a porous polishing layer having a double pore structure in a polyurethane matrix coated over a support base substrate. The dual pore structure has a primary set of larger pores and a smaller set of smaller pores inside and between the cell walls of the larger pores. This double void structure serves to reduce defects while increasing the removal rate in some polishing systems.

The porous abrasive layer is fixed to the polymerizable film substrate or formed in a woven or nonwoven structure to form a polishing pad. When depositing a porous abrasive layer on a polymeric substrate, such as a nonporous poly (ethyleneterephthalate) film or sheet, a binder such as a trademarked urethane or acrylic adhesive may be used to increase adhesion to the film or sheet. It is often advantageous. Although these films or sheets may contain voids, they are advantageously nonporous. The advantages of nonporous films or sheets are that they promote uniform thickness or flatness, increase the overall stiffness of the polishing pad, reduce the overall compressibility, and eliminate the slurry wicking effect during polishing.

In alternative embodiments, the woven or nonwoven structure serves as a substrate for the porous abrasive layer. Although the use of a nonporous film as a substrate substrate has the advantages as set out above, the film also has disadvantages. Most notably, when a nonporous film is used as the base substrate, air bubbles can be trapped between the polishing pad and the platen of the polishing tool. This leads to major problems of polishing nonuniformity, higher defects, high pad wear and reduced pad life. These problems are eliminated when felt is used as the substrate substrate because air can pass through the felt and air bubbles are not captured. Secondly, when the abrasive layer is applied to the film, the adhesion of the abrasive layer to the film depends on the strength of the adhesive bond. Under some aggressive polishing conditions, this bond can fail and cause catastrophic failure in polishing. When felt is used, the abrasive layer actually penetrates into the felt to a certain depth to form a strong, mechanically interlocked interface. Although woven structures are also acceptable, nonwoven structures can provide additional surface area for strong bonding to porous polymeric substrates. A good example of a suitable nonwoven structure is a polyester felt that is impregnated with polyurethane to hold the fibers together. Typical polyester felts will have a thickness of 500-1500 μm.

The primary set of voids (also referred to herein as the macropores) is open to the polishing surface and typically has an average diameter of at least 35 μm. For purposes of this specification, the average diameter of the primary voids represents the average maximum width of the voids measured in the cross section in a direction parallel to the polishing surface of the polishing pad. Advantageously, the primary or large pores have an average diameter of at least 40 μm. These large voids facilitate slurry transport and removal of abrasive debris. The macropores have a stretched structure orthogonal to the polishing surface and provide a consistent polishing surface area over the life of the polishing pad. The primary void may have a columnar structure with tapered sidewalls or preferably vertical sidewalls.

In addition, the primary set of voids contains void walls. These void walls have a thickness of 15 to 55 μm. This wall thickness contributes to the rigidity and polishing ability of the pads. If the cell wall is too thin, the stiffness required for consistent polishing will be lacking, pad wear will be high and pad life will be shortened. Similarly, if the cell walls are too thick, there will be a lack of suitable structures for effective polishing. Advantageously, the cell walls have a thickness of 20-50 μm. In addition to the thickness, it is important that the cell walls have the necessary rigidity or modulus to have a modulus low enough to achieve low defect polishing at the same time as delivering appropriate abrasive force to the target substrate, such as a wafer. For the purposes of this specification, modulus dissolves the polymer in dimethylformamide, coats the solution onto a glass plate, removes the solvent at elevated temperature, and then removes the dried coating from the glass plate, leaving a freestanding nonporous film, 50%. After conditioning the film at 25 ° C. for 5 days at humidity, use a thin film fixture to measure 10 / rad / sec. At a temperature of 25 ° C. according to ASTM D5026-06 “Plastic: Standard Test Method for Dynamic Mechanical Properties: Tension”. Tensile storage modulus (E ') of the material measured after testing at frequency is shown. The storage modulus of 10 to 60 MPa through this test method provides good polishing results with low defects. Advantageously, the wall has a storage modulus of 10 to 50 MPa. Most advantageously, the wall has a storage modulus of 10 to 40 MPa. At storage modulus of less than 10 MPa, the void walls have insufficient stiffness to survive the mechanical stress of the aggregate preparation method. At storage modulus above 60 MPa, the defect value increases to an unacceptable level in the required polishing process. From this, there is a relationship between the modulus of the polymer in the void walls and the level of defects that occur during polishing.

In addition to the primary set of voids (large voids), a secondary set of voids (also referred to herein as micropores) within the large void walls provide additional polishing advantages to the polishing pad. Secondary sets of pores have an average pore size of 5 to 30 μm and tend to have a more spherical shape than the primary pores. For the purpose of this specification, secondary pore size refers to the average diameter of the micropores in the large pore cell wall that cut across the abrasive surface dividing the secondary pores. Advantageously, the secondary pores have an average pore size of 5 to 25 μm.

In addition to the micropore size, the cell walls advantageously have a porosity of at least 10% by volume but up to 55% by volume. For purposes of this specification, porosity represents visible pore fractions within the cell wall with a scanning electron microscope at 500 × magnification of the cell wall that cuts across the polishing surface dividing the secondary pores. Preferably, the cell walls advantageously have a porosity of at least 20% by volume but up to 50% by volume. The cell wall most advantageously has a porosity on the order of 20-40% by volume. Moreover, the pore walls optionally have a thickness equal to 2 to 10 times the average size of the micropores or preferably 4 to 10 times the average pore size of the micropores.

The creation of porous polymeric structures by solvent / non-solvent agglomeration techniques can be achieved by artificial leather (see, eg, Encyclopedia of Polymer Science "LeatherLike Materials") or by synthetic membranes (see, for example, Encyclopedia of Polymer Science "Membrane"). Technology "] has been used for many years. In agglomeration processing, a solution of a polymer in a solvent is added to a solution that is non-solvent for that polymer. The polymer phase from the solution separates to form a polymer-rich phase and a polymer-poor phase. The polymer rich phase constitutes the void wall and the polymer lack phase is the void itself. By controlling polymer chemistry and aggregation conditions, it is possible to create a wide variety of pore structures for different applications. In addition to creating a porous structure using a solvent based polymer solution, it is also possible to aggregate the aqueous dispersible polymer coating by processes other than solvent / non-solvent exchange. Possible approaches to destabilize aqueous polymer dispersions include pH changes, ionic strength changes, and temperature changes.

In addition to solvent / non-solvent agglomeration, sometimes referred to as immersion precipitation, it is possible to produce similar porous structures by other techniques. These include processing such as sintering, drawing, track etching, template leaching and phase inversion. The latter includes precipitation by solvent evaporation, precipitation from vapor phase, precipitation by controlled evaporation and thermal precipitation. Another method of making interconnected voids is by using supercritical fluids or using low density foam technology.

Example :

Table 1 summarizes the properties of the pads described in the examples below. It includes values for the overall pad properties, metrology data for large pores, abrasive materials, and various features that define a porous polishing pad. Examples 1-3 show comparative examples of commercial-polyurethane porous polishing pads. Examples 4-7 show polishing pads demonstrating improved polishing performance over commercial polishing pads.

The description for Table 1 is as follows:

DMA Measurement: The tensile storage modulus of the polymer forming the void walls of the porous coating was determined by dynamic mechanical analysis of the cast film. They were prepared by coating a polymer dissolved in dimethylformamide on a glass plate, removing the solvent at elevated temperature, and then removing the dried coating from the glass plate, leaving a free-standing film approximately 300 microns thick, free of air bubbles and other flaw points. . After the film was 5 days conditioning at 50% relative humidity and 25 ℃, the tensile storage modulus was measured using a metric Leo Scientific ^TM (Rheometric Scientific ^TM) Solid Analyzer RSA III. Measurements were made on tension using thin film fixtures at a frequency of 10 / rad / sec at a temperature of 25 ° C. according to ASTM D5026-06 “Plastic: Standard Test Method for Dynamic Mechanical Properties: Tension”. The sample had a value of 20 mm long by 6.5 mm wide.

Pore metrology measurement: Image-Pro® software developed by Nikon SMZ800 ^™ microscope and Media Cybernetics® for the primary (macropores) present on the surface of the porous abrasive layer Characterized by light microscopy. Several pore parameters were determined by software. These are the number of voids P present in the measurement area A ; Average area ( MPA ) of each pore; Pore diameter; And the fraction of voids. From these variables, the average thickness w of each pore wall was calculated using the following formula:

w = (A / πP) ^1/2 -( MPA / π) ^1/2

Polishing Conditions : All abrasive materials were generated using 20 inch (51 cm) diameter pads polished on an Applied Mirra® 200 mm grinder. Pads are embossed in a cross-hatch design with values of 100 mil (2.5 mm) pitch, 30 mil (0.8 mm) wide and 15 mil (0.4 mm) deep, or 180 mil (4.6 mm) It was machined into a cross hatch groove pattern with values of pitch, 30 mil (0.8 mm) wide and 15 mil (0.4 mm) deep. The slurry used was LK393c4 manufactured by Dow Electronic Materials at a flow rate of 200 ml / min. The platen and carrier head speeds were 93 rpm and 87 rpm, respectively, and the downward force was 1.5 psi.

Copper and dielectric removal rates were measured using blanket Cu and TEOS wafers, respectively. Defect metrology data were determined from blanket Cu wafers using the KLA SP1 Blanket Wafer Inspection Tool at 0.8 micron detection limit, and then detected and sorted using a Bistec INS3300 Leica Defect Review Microscope.

Example  1: comparison pad A ( Polytex ^TM CMP  Polishing pads)

Comparative pad A is a polyurethane porous pad that has been widely used for many years to polish semiconductor wafers.

The pad was made by coating a polyurethane solution in dimethylformamide (DMF) onto a urethane impregnated nonwoven polyester felt substrate, which was then immersed in a non-solvent / solvent coagulation bath to form a porous coating on the substrate. After rinsing and drying, the coated substrate was polished with abrasive paper to remove the skin layer and expose the pore structure. The pad was then embossed to produce a cross-hatched groove pattern in the abrasive layer. The embossed groove pattern facilitated slurry dispersion across the pad surface during polishing.

The pore structure of Comparative Pad A included huge vertical voids in the dimensions shown in Table 1. The pores were typically 70 microns in diameter and hundreds of microns in length (when measured in a cross section parallel to the polishing surface). Most of the pores tapered with narrower pores toward the polishing surface. This tapered structure resulted in pore density changing with pad wear; Various pore densities provided inconsistent polishing performance as the pad surface weathered for the life of the pad.

The cell walls had a low porosity and did not have micropores in the desired range of 5-40 microns. Any voids present were significantly less than 5 microns in diameter, and typically less than 1 micron in diameter. From the large pore measurement data, it was possible to calculate the thickness of the pore wall using the equation described above. For comparison pad A, the calculated void wall thickness was 20 microns. Since this value was low, this contributed to excessive contact force on the wafer surface causing higher defects. The modulus of the polymer forming the void walls had a value of 71 MPa, as measured by the DMA method described above. This value was higher than desired and also resulted in higher defects during polishing.

According to the abrasive data and the conditions of Table 1, the polishing performance of this pad was inadequate for low defect polishing applications. For example, the binding value was excessive and the TEOS removal rate was too low to meet the throughput requirements for commercial wafer integrated structures. In particular, the TEOS: Cu removal rate selectivity was too low for improved low defect or future polishing requirements.

Example  2: compare pad B ( H7000HN - PET , Fujibo ( Fujibo ))

Comparative pad B was a polyurethane porous pad used to polish a semiconductor wafer sold under the trade name H7000HN-PET by Fujibo Corporation. The pad was subjected to a process similar to that used in Example 1 except that the polishing layer was coated on the polyester film substrate and the pore structure was controlled, including a surfactant added to the formulation, such as dioctyl sodium sulfosuccinate. Appears to be made by The pore structure of the comparison pad B was different from that of the comparison pad A. Comparative pad B had a pore structure consisting of both large pores and smaller micropores in the pores wall of the pores.

Although some aspects of the present pore structure were adequate for the needs of low defect polishing applications, Comparative Pad B achieved a double pore structure by adding a surfactant to the polyurethane formulation. Some of these surfactants contained metal ions, such as sodium, which could threaten the electrical performance of the device being polished, while other surfactants may cause unacceptable foam generation during polishing.

Secondly, the concentration of micropores in the large pore walls is very high, weakening the cell walls, which can lead to high pad wear and reduced pad life. Finally, in Table 1, it can be seen that the calculated pore wall thickness is 63 microns. The pore structure thus consists of pores separated by walls having dimensions comparable to the diameter of the pores themselves. This pore structure adversely affects both slurry transfer and the contact force between the pad and the wafer and is insufficient for the more demanding low defect polishing applications.

Example  3: compare pad C ( SPM3100 ^TM )

Comparative pad C was a porous pad used to polish silicon wafers. The pads were manufactured under the trade name SPM3100 by Dow Electronic Materials. The pad was made by a process similar to that used in Example 1 except that the abrasive layer was coated on the polyester film substrate. Although Comparative Pad C had the proper pore shape and proper wall thickness with both large and small voids, the modulus of the polymer in the void walls was too high for low defect polishing. This example demonstrates the need to control the modulus of the polymer in the void walls below the threshold to achieve very low defect levels required for abrasive applications where low defects are required. In addition, the TEOS: Cu removal rate selectivity was unacceptably low for improved low defects or future polishing needs.

Example  4: (film base substrate)

Polyurethane was synthesized in DMF by reacting a mixture of polyethylene propylene glycol adipate polyol (0.0102 mol) and butanediol (0.0354 mol) with difetylmethane diisocyanate (MDI) (0.0454 mol) to obtain a weight average molecular weight of 50,000 and 1.6 A polyurethane having a polydispersity of was formed. The resulting polyurethane solution had a room temperature viscosity of approximately 3000 cP at 25 wt% solids. There was no surfactant present in the formulation.

A 75 mil (1.9 mm) wet-thick layer of the polyurethane solution at 17 ° C. was coated onto a 7.5 mil (0.2 mm) thick polyester film substrate. The coated film was immersed in a bath containing 14.5% DMF and 85.5% water maintained at 17 ° C. to aggregate the polymeric coating and form a porous microstructure containing both large and small pores.

After rinsing and drying, the coated film was polished with abrasive paper to remove the skin layer and expose the pore structure. The grooves were machined in an abrasive layer to produce a cross-hatched groove pattern with a nominal dimension of 180 mil pitch (4.6 mm), 15 mil depth (0.4 mm) and 30 mil (0.8 mm) wide. These grooves facilitated slurry dispersion across the pad surface during polishing.

The combination of polyurethane formulation and flocculation conditions results in a suitable pore morphology consisting of a large pore having an average wall thickness of 30 microns with micropores in the large pore wall. The micropores were approximately spherical, about 10 microns in diameter and their concentration was such that there was a continuous large pore wall between the micropores. Thus, unlike the high concentration of overlapping micropores present in Comparative Pad B, the micropores in this example did not threaten the strength or stiffness of the large pore walls.

Polyurethane porous double pore structures have various advantages. First, it serves to increase the TEOS removal rate to the higher value required to polish the improved node, and more importantly significantly increases the TEOS: Cu removal rate selectivity to the desired value. From Table 1, it can be seen that the TEOS removal rate and TEOS: Cu selectivity of Example 4 were significantly higher than the corresponding values in comparison pad A of Example 1. Comparative pad A lacked secondary micropores inside the primary pore wall and did not have the same ability to anchor and transport the slurry in the pad-wafer gap. Although Comparative Pad B of Example 2 had both micro- and large-porosity, the micropore concentration and the thickness of the large pore wall were both too high to maintain optimized contact and slurry transport between the wafer and the pad surface. Thus, the TEOS removal rate achieved by Comparative Pad B was unsuitable for the low defect polishing applications required.

A second advantage of the advantageous double pore structure of Example 4 is that it reduces the change in polishing performance with pad wear. For pads having a structure with only large pores, such as Comparative Pad A of Example 1, the change in removal rate occurred as the pads were worn during polishing. This is the result of a large void with a tapered cross section such that as the pad wears, the void cross section changes. The abrasive materials of the pads having the beneficial dual pore structure of the present invention have established a nearly constant removal rate, or consistent throughput, as the pad wears over the pad lifetime, and the defects have not changed either-commercial pads A, B and Significant advantages over C.

A third advantage of the double pore structure of Example 4 is that the presence of micropores reduces the need to create a texture in the pad surface by diamond conditioning. For conventional polishing pads, it is customary to condition the pad surface with a wear diamond conditioning disk before or during polishing. This step makes it necessary to purchase time-consuming and expensive diamond conditioning discs. The polishing operation requires that the pads having the structure of Example 4 require minimal diamond conditioning before or during polishing, and if necessary, conditioning of the pad surface with a simple, inexpensive nylon brush may result in pad life. It has been shown to be sufficient to maintain low defects and stable removal rates over time. Removal or at least minimization of diamond conditioning results in reduced pad wear and increased pad life.

A fourth advantage of the double pore structure of Example 4 is that the polishing performance is less dependent on the macrogroove design machined or embossed into the pad surface. Macro grooves are required to prevent static friction between the pad and wafer during polishing and to enable slurry transport in the pad-wafer gap. However, unlike conventional polishing pads, the change in the macrogroove design of the pad of Example 4 had only a small effect on polishing performance.

The storage modulus of the polymer in the pore wall was 39 MPa. This value, along with low defect polishing, provided an effective TEOS removal rate and a high TEOS: Cu removal rate selectivity value of 3.5. The pad of Example 4 had a very low defect count value of 6, significantly lower than the defect levels of Comparative Pad Examples A, B and C.

Example  5: ( felt  Substrate)

A 75 mil wet-thick layer of polyurethane solution was prepared in Example 4 at 17 ° C., but it was coated onto a polyurethane-impregnated nonwoven polyester felt substrate. The substrate made by Dow Electronic Materials had a density of 0.340 g / cm ³ and had a compressibility of 14%, a thickness of 49 mil (1.2 mm) and a hardness of 49 Shore DO.

The coated felt was immersed in a bath containing 14.5% by volume DMF and 85.5% by volume water maintained at 17 ° C. to aggregate the polymerizable coating and form a porous microstructure containing both large and small pores. After rinsing and drying, the coated substrates were polished with abrasive paper to remove the skin layer and expose the pore structure. The abrasive layer was then embossed to produce a cross-hatched groove pattern with a nominal dimension of 100 mil pitch (2.5 mm), 15 mil deep (0.4 mm) and 30 mil (0.8 mm) wide. These embossed groove patterns facilitate slurry dispersion across the pad surface during polishing.

Felt substrates have an advantage over films in that air bubbles are not trapped between the polishing pad and the platen of the polishing apparatus because the droplets can disappear through the breathable felt layer, resulting in poor polishing performance. Secondly, when the abrasive layer is applied to the film, the adhesion of the abrasive layer to the film depends on the strength of the adhesive bond. Under some aggressive polishing conditions, this bond may fail, causing catastrophic failure of polishing. If felt is used, the abrasive layer actually penetrates into the felt to some depth and forms a strong, mechanically interlocked interface. In contrast to Example 4, in Example 5 the same abrasive layer is coated on the polyester felt instead of the film substrate. Polyester felt is much more compressible and less rigid than polyester films. Since the abrasive layer was made from the same polymer formulation and the aggregation conditions were the same as in Example 4, similar double pore structure, wall thickness and pore wall polymer modulus values were achieved in Example 5. The only difference was the substrate substrate. From Table 1, it can be seen that the nonwoven pad of Example 5 achieved low defect values, high TEOS removal rate, and high TEOS: Cu removal rate selectivity.

This example demonstrates that good polishing performance can also be obtained with nonwoven felt based substrates and that the problems of air entrainment and adhesive bond failure have been eliminated compared to films.

Example  6: ( felt  Substrate)

A 75 mil wet-thick layer of polyurethane solution was prepared in Example 4 at 17 ° C. and coated on a polyurethane-impregnated nonwoven polyester felt substrate. The substrate made by Dow Electronic Materials had a density of 0.318 g / cm ³ , a compressibility of 17%, a thickness of 44 mil (1.1 mm), and a hardness of 39 shore head.

The coated felt was converted to a polishing pad using the conditions described in Example 5 and the same processing steps.

Example 6 further demonstrates that the nonwoven felt substrate produces good polishing performance.

Example  7: (film base material substrate)

A mixture of polyethylenepropylene glycol adipate (0.0117 moles) and butanediol (0.0259 moles) with difethylmethane diisocyanate (MDI) (0.0373 moles) in DMF to react to a poly having a weight average molecular weight of 40,000 and a polydispersity of 1.6. Urethane was formed to synthesize polyurethane. The polyurethane solution was coated onto the film and converted to a polishing pad using the same processing steps and conditions as described in Example 4.

Example 7 differed from Example 4 in that the polyurethane formulation was modified to reduce the modulus of the polymer in the void walls. Other aspects of the polishing pad, including the double pore structure and the void wall thickness, remained similar to the polishing pad of Example 4.

There was an obvious relationship between the modulus of the polymer in the void walls and the level of defects generated during polishing. Thus, comparing Examples 7 and 4, the values for the modulus of the polymer in the pore walls are 17 and 39 MPa and the defect levels are 2 and 6, respectively, clearly demonstrating that the reduction in pore wall modulus reduces the defects. .

The polishing pad of the present invention provides various advantages that are not achieved by conventional porous polishing pads. For example, the dual porosity of the polishing pad facilitates high TEOS removal rates and high TEOS: Cu removal rate selectivity with low defects. In addition, the dual porosity polishing pad requires reduced release and provides a stable removal rate; Along with these stable speeds, reduced conditioning is achieved. The pad provides a good lifetime of 1,000 wafers with limited wear. Moreover, woven and nonwoven substrates provide excellent interlayer adhesion and eliminate air entrainment. Finally, the polishing pad is surfactant-free and can be foamed during polishing, or dispersed into dielectrics and low-k dielectrics, providing no alkali metals that interfere with polishing.

Claims (10)

The porous abrasive layer has a double pore structure in the polyurethane matrix, the double pore structure has a primary set of pores, the primary set of pores has a pore wall, the pore wall has a thickness of 15 to 55 μm, Having a storage modulus of 10 to 60 MPa as measured at 25 ° C., containing a secondary set of voids in the void walls, the secondary set of voids having an average pore size of 5 to 30 μm, wherein the porous abrasive layer A polishing pad useful for polishing one or more of magnetic, optical and semiconductor substrates comprising a porous polishing layer, which is fixed to the polymerizable film or sheet substrate or formed in a woven or nonwoven structure to form a polishing pad. The polishing pad of claim 1, wherein the primary void has an average diameter of at least 35 μm. The polishing pad of claim 1, wherein the cross section of the pore wall has a porosity of 10 to 55%. The polishing pad of claim 1, wherein the pore wall has a thickness equal to two to ten times the average pore size of the micropores. The polishing pad of claim 1, wherein the polyurethane matrix is a surfactant-free aggregated structure. The porous abrasive layer has a double pore structure in the polyurethane matrix, the double pore structure has a primary set of pores, the primary set of pores has a pore wall and an average diameter of 40 μm or more, and the pore wall has 20 to 50 μm Has a storage modulus of 10 to 50 MPa as measured at 25 ° C., contains a secondary set of voids in the void walls, the secondary set of voids having an average pore size of 5 to 25 μm, wherein A polishing pad useful for polishing one or more of magnetic, optical and semiconductor substrates comprising a porous polishing layer, wherein the porous polishing layer is secured to the polymerizable film or sheet substrate or formed in a woven or nonwoven structure to form a polishing pad. 7. The polishing pad of claim 6 wherein the storage modulus of the pore wall is 10 to 40 MPa as measured at 25 ° C. The polishing pad of claim 6, wherein the cross section of the pore wall has a porosity of 20-50%. The polishing pad of claim 6, wherein the pore wall has a thickness equal to 4 to 10 times the average pore size of the micropores. The polishing pad of claim 6, wherein the polyurethane matrix is a surfactant-free aggregated structure.