KR20110030215A - Liquid crystal display and driving method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display and a driving method thereof are provided to increase display quality by compensating the polarity deflection of data with a dynamic common voltage. CONSTITUTION: In a liquid crystal display and a driving method thereof, an LCD panel(50) comprises data lines, gate lines, and a common electrode(2). The common voltage is supplied to the common electrode. A data voltage is applied to the data lines. The gate pulse is applied to gate lines. A data monitor block determines the degree of polarity deflection of input digital video data. The data monitor block outputs common voltage control data which controls the common voltage. The common voltage generator(54) controls the common voltage.

Description

Liquid Crystal Display and Driving Method

The present invention relates to a liquid crystal display and a driving method thereof.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in a portable information device, an office device, a computer, and a TV, and is rapidly replacing a cathode ray tube.

In order to inspect image quality in the liquid crystal display, a test pattern as shown in FIG. 1 may be used in the inspection process of the liquid crystal display. In the inspection process, as shown in FIG. 1, a stripe pattern in which a pixel charged with white gray voltage and a pixel charged with a black gray voltage is alternately applied to a liquid crystal display to display a stripe pattern for a predetermined time, The voltage applied to the pixels is adjusted to the mid-gradation voltage between the white gray and the black gray. Then, a shift of the common voltage occurs according to the position of the screen, and cross talk occurs. This is because the common voltage applied to the common electrode is shifted by the change of the data voltage applied to the pixel electrode by coupling the pixel electrode and the common electrode of the liquid crystal cell.

The polarity of the data voltage applied to the liquid crystal display device is periodically reversed in order to suppress the direct current of the liquid crystal. When the test pattern shown in FIG. 1 is displayed on the LCD, the polarity of the data voltage is shown in FIG. 2. FIG. 2 is a diagram illustrating polarities of data voltages on a part of the test pattern of FIG. 1. As when a normal image is input, the data voltage of the test pattern is inverted to horizontal and vertical 1 dot inversion. In the horizontal and vertical 1 dot inversions, polarities of data voltages supplied to neighboring liquid crystal cells in the horizontal direction are opposite to each other, and polarities of liquid crystal cells neighboring in the vertical direction are opposite to each other. Inverting the polarity of the data of the test pattern as shown in FIG. 1 into horizontal and vertical 1 dot inversions results in greenish green light, and luminance difference between neighboring lines. This is because the polarity of the data voltage charged in the liquid crystal display device is deflected to either polarity. This will be described with reference to FIGS. 3 and 4.

Referring to FIG. 3, when the white data voltage is applied to the A line of FIG. 2, the polarities of the R data voltage and the B data voltage are positive, and the polarity of the G data voltage is negative. Therefore, the positive data voltage is superior to the negative data voltage in the A line. (+ Polarity dominant) As a result, the common voltage Vcom in the A line is shifted toward the positive polarity due to the coupling with the positive data voltage. is shifted. In the A line, the G data voltage applied as the positive black voltage (+ Vblack) in the previous frame period is changed to the negative white voltage (-Vwhite) in the current frame period, so that the voltage difference of the G data voltage becomes large, so that the green in the A line. The crude phenomenon appears.

Referring to FIG. 4, when the white data voltage is applied to the B line of FIG. 2, the polarities of the R data voltage and the B data voltage are negative, and the polarity of the G data voltage is positive. Therefore, in the B line, the negative data voltage is superior to the positive data voltage. (-Polarity dominant) As a result, the common voltage Vcom in the B line shifts toward the negative polarity due to the coupling with the negative data voltage. do. In the B line, the G data voltage applied as the negative black voltage (-Vblack) in the previous frame period is changed to the positive white voltage (+ Vwhite) in the current frame period, so that the voltage difference of the G data voltage becomes larger, so that the green The crude phenomenon appears.

Accordingly, when data whose voltage difference between the data voltage becomes larger as white voltage and black voltage are input to neighboring pixels, the conventional LCD displays green tone, smear and crosstalk due to polarity deflection of the data voltage. Is generated. As a result, the conventional liquid crystal display device is inferior in display quality in some weak pattern data.

On the other hand, a method of changing the dot inversion method by detecting a pattern in which the display quality may be deteriorated may be considered in the input image. However, in this method, the last frame before the change in the first frame of the polarity control signal is changed. Screen flicker may occur due to the overlapping polarity of the frame and pixels.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which improve the display quality by compensating polarity deflection of data with a dynamic common voltage.

In order to achieve the above object, in the liquid crystal display of the present invention, a common electrode in which data lines supplied with a data voltage and gate lines supplied with a gate pulse are crossed, and a common voltage is supplied is formed. A liquid crystal display panel in which liquid crystal cells driven by a difference in voltage are arranged in a matrix form; A data monitor block for determining a degree of polarization deflection for input digital video data and outputting common voltage control data for adjusting the common voltage; And a common voltage generator for adjusting the common voltage in response to the common voltage control data.

The liquid crystal display may further include a data driving circuit configured to convert the input digital video data into positive / negative data voltages and output the converted digital data data to the data lines; A gate driving circuit supplying the scan signals to the gate lines; And a timing controller for supplying the input digital video data to the data driver circuit and for controlling the operation timing of the data driver circuit and the gate driver circuit.

The data monitor block is embedded in the timing controller.

The data monitor block separately counts the positive data and the negative data from among data above a predetermined first threshold, and adds the sum of the count values of the positive data and the negative data for one line of data. And comparing the difference value of the sum of the count values with a predetermined second threshold value, and supplying common voltage control data to the common voltage generator for adjusting the common voltage in an unbalanced line having the difference value equal to or greater than the second threshold value.

If it is determined that the unbalanced line is deflected positively, the data monitor block generates the common voltage control data by subtracting a shift level proportional to the degree of deflection from a predetermined default value, and the unbalanced line becomes negative. If determined to be deflected, the common voltage control data is generated with the default value plus the shift level.

A method of driving a liquid crystal display device according to the present invention comprises the steps of: determining a degree of polarization deflection with respect to input digital video data; Generating common voltage control data for adjusting the common voltage according to the polarity deflection degree; And adjusting the common voltage in response to the common voltage control data.

According to the present invention, the dynamic common voltage is updated for each line according to the polarity deflection of the data, thereby reducing the deterioration in image quality due to the polarity deflection of the data, and preventing the screen flicker caused by the repetition of the same polarity between frames. .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 12.

Referring to FIG. 5, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 50, a timing controller 51, a data driving circuit 52, a gate driving circuit 53, and a common voltage generator ( 54).

In the liquid crystal display panel 50, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 50 includes liquid crystal cells Clc arranged in a matrix by a cross structure of the data lines 54 and the gate lines 55.

Data lines 54, gate lines 55, TFTs, and a storage capacitor Cst are formed on a lower glass substrate of the liquid crystal display panel 50. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 50. The common electrode 2 is supplied with the dynamic common voltage Dynamic Vcom from the common voltage generator 54. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 50, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate.

The liquid crystal mode of the liquid crystal display panel 50 applicable to the present invention may be implemented in any liquid crystal mode as well as the above-described TN mode, VA mode, IPS mode, and FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The cross-sectional structure of the direct type backlight unit has a structure in which a plurality of optical sheets and a diffusion plate are stacked below the liquid crystal display panel 50 and a plurality of light sources are disposed below the diffusion plate. The edge type backlight unit has a structure in which a light source is disposed to face the side of the light guide plate, and a plurality of optical sheets are disposed between the liquid crystal display panel and the light guide plate.

The timing controller 51 supplies the digital video data RGB to the data driving circuit 52. In addition, the timing controller 51 receives an external timing signal such as a data enable signal (Data Enable, DE), a dot clock (CLK), and the like to control the operation timing of the data driver circuit 52 and the gate driver circuit 53. To generate driving circuit control signals. The external timing signal may include a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. The driving circuit control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 53 and a data timing control signal for controlling the operation timing of the data driving circuit 52 and the vertical polarity of the data voltage. . The timing controller 51 analyzes the gray level of the input data RGB and the polarity inversion pattern of the liquid crystal display panel 50 to determine the polarity shift level of the input data to adjust the output of the common voltage generator 54. Generate common voltage control data. The common voltage control data may be input to the common voltage generator 54 through the serial data bus.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC that generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (Source Output Enable, SOE), and the like. The polarity control signal POL controls the vertical polarity of the data voltage output from the data driving circuit 52. The source output enable signal SOE controls the output of the data driver circuit 52. If the signal transmission system between the timing controller 51 and the data driver circuit 52 is a mini LVDS (Low Voltage Differential Signaling) interface, the source start pulse (SSP) and the source sampling clock (SSC) required in the conventional TTL interface are required. ) May be omitted.

Each of the data drive ICs of the data driving circuit 52 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 52 latches the digital video data RGB under the control of the timing controller 51. The data driving circuit 52 converts the digital video data RGB into an analog positive / negative gamma compensation voltage according to the polarity control signal POL to generate a positive / negative analog data voltage and converts the data voltage. Supply to data lines 54.

The gate drive ICs of the gate driving circuit 53 sequentially supply gate pulses to the gate lines 55 in response to gate timing control signals.

In response to the common voltage control data input from the timing controller 51, the common voltage generator 54 generates a polarity shift level of the input data at the vertical blank time Vblank and the horizontal blank time Hblank as shown in FIGS. 9 and 10. Output a dynamic common voltage (Vcom) adjusted by.

6 is a circuit diagram illustrating the common voltage generator 54 in detail.

Referring to FIG. 6, the common voltage generator 54 includes a resistor 61, a decoder 62, a switch array 63, and a voltage divider resistor circuit 64.

The register 61 samples the serial data SDA according to the serial clock SCL and supplies the sampled data to the decoder 62. The serial clock SCL and the serial data SDA are input from the timing controller 51. The serial data SDA includes a device address, a register address, and common voltage control data to be updated as shown in FIG. 8. The device address includes the identification code of the common voltage generator 54 and the register address includes the input address of the register 61. The common voltage control data includes a default value and a shift level value added to or subtracted from the default value (+/−).

The decoder 62 generates a control signal for selectively turning on the switches T0 to T127 constituting the switch array 63 according to the serial data from the register 61.

The switch array 63 includes a plurality of switches T0 to T127. Gate terminals of the switches T0 to T127 are connected 1: 1 to the output terminal of the decoder 62 to receive a control signal. The source terminals of the switches T0 to T127 are connected 1: 1 to the divided voltage output node between the resistors of the divided resistor circuit 64. The drain terminals of the switches T0 to T127 are connected to the common electrode 2 of the liquid crystal display panel 50 through a common voltage supply wiring (not shown). The switches T0 to T127 may be turned on in response to a control signal from the decoder 62 so that any one of the plurality of divided voltages may be supplied to the common electrode 2. ).

The voltage divider resistance circuit 64 includes a plurality of resistors R1 to R127 connected in series between the high potential power supply voltage source Vh and the low potential power supply voltage source Vl. A plurality of divided voltages having different potentials are supplied to the switches T0 to T127 through the divided voltage output nodes between the resistors R1 to R127 of the divided resistor circuit 64.

In the divided resistor circuit 64, divided voltages of 127 levels having different potentials may be output through different divided voltage output nodes. The default value of the common voltage may be set to a divided voltage of 75 levels. The common voltage generator 54 responds to the common voltage control data from the timing controller 51 to adjust the potential of the dynamic common voltage Vcom by a shift level which is added to or subtracted from the default value input from the timing controller 51. To turn on the switch that outputs the voltage at the desired voltage level.

FIG. 7 is a diagram for describing an example of a method of determining a polarity shift level of input data in the timing controller 51.

Referring to FIG. 7, the timing controller 51 may determine the polarity shift level of the input data RGB by analyzing the gray level of the input data RGB and the polarity inversion pattern of the liquid crystal display panel 50.

It is assumed that the input data RGB is input as in the example of FIG. 7, and the polarity of the data voltage charged in the liquid crystal display panel 50 is inverted to the horizontal 1 dot inversion.

In this data pattern, the odd pixel data (PXL # 1, PXL # 3, PXL # 5, ... PXL # 13) contain R data above a first predetermined threshold and G and B data below a first threshold. Include. The even pixel data PXL # 2, PXL # 4, PXL # 6, ... PXL # 14 include G data above the first threshold and R and B data below the first threshold. In each of the pixel data PXL # 1 to PXL # 14, the data polarity above the first threshold is all positive according to the polar pattern in the form of horizontal 1 dot inversion, whereas the data polarity below the first threshold is positive or negative. Polarity.

Here, the predetermined first threshold value may be selected to extract digital video data of half gray scale or more. For example, if the LCD panel 50 can display data in 256 gray scales by 8 bits of digital video data, the most significant bit (MSB) of digital video data having gray scale values of 64 to 255 is' 01 ',' 10 ', and' 11 '. In this case, the first threshold may be determined as '01'.

The timing controller 51 does not count data below the first threshold but counts only the weighted number of the data above the second threshold. In addition, the timing controller 51 separates the positive data (+) to be supplied to the liquid crystal display panel 50 with the positive data voltage and the negative data (-) to be supplied to the liquid crystal display panel as the negative data voltage. Count. The data displayed in white in the input data of FIG. 7 represents data above the threshold, and the data displayed in black represents data below the threshold.

The timing controller 51 increases the positive count total (+ CNT) by '2' when the first and second pixel data PXL # 1 and PXL # 2 are input, while the negative count total (- CNT) does not increase. When the third and fourth pixel data PXL # 3 and PXL # 4 are input, the timing controller 51 further increases the positive count total + CNT by '2', while the negative count total ( -CNT) does not increase. When the fifth and sixth pixel data PXL # 5 and PXL # 6 are input, the timing controller 51 further increases the positive count total + CNT by '2', while the negative count total ( -CNT) does not increase. After continuing the count operation as described above, the result of counting up to the fourteenth pixel data PXL # 14 is increased by the positive count total (+ CNT) to 14, while the negative count total (-CNT) is' 0 '. In this case, the timing controller 51 determines the shift level to "+14" for the data pattern as shown in FIG.

Next, the timing controller 51 performs positive polarity with respect to one line of data included in one data enable D1 during the blank time of the data enable DE, that is, the horizontal blank time Hblank of FIG. 10. The difference between the count sum (+ CNT) and the negative count sum (-CNT) is compared with a predetermined second predetermined threshold. The timing controller 51 determines that the line is an unbalanced line in which the polarity is deflected when the difference between the positive count sum (+ CNT) and the negative count sum (-CNT) is equal to or greater than the second threshold. Here, the second threshold value may be determined as a value corresponding to 50% of the total number of data included in one line. For example, since the data included in one line in the XGA resolution is 1024 (pixels) × 3 (RGB) = 3072, the second threshold may be determined to be 1536 in the XGA resolution.

The timing controller 51 transmits the common voltage control data to the common voltage generator 54 within the processing time of the internal output block that processes the data RGB after determining the polarity shift level on the unbalanced line. Update the common voltage Vcom. The common voltage generator 54 updates the dynamic common voltage Vcom through the process as shown in FIG. 8. The fast mode clock frequency of typical programmable Vcom logic is several Mhz. Accordingly, the common voltage generator 54 may update the dynamic common voltage Vcom sufficiently within the horizontal blank time Hblank shown in FIG. 10.

As described above, shift level determination of polarity bias in the input data may be performed by the data monitor block in the timing controller 51 in FIG. 11. The data monitor block may receive the polarity control signal POL to determine the polarity of the data.

For reference, the time required for data to be loaded into the liquid crystal display panel 50 from the data input is 2 to 4 horizontal periods in the timing controller 51 and the source of the data driving circuit 52 as shown in FIG. 11. One to three horizontal periods, plus one horizontal period required by the latch integrated in the drive IC, are included. It takes approximately one horizontal period to determine the polarity skew of the input data in line units in the data monitor block of the timing controller 51, and approximately one horizontal period takes to transmit the common voltage control data to be changed through I ₂ C communication. do. Thus, the dynamic common voltage Vcom can be updated every line without the need to delay data.

The timing controller 51 lowers the voltage of the dynamic common voltage Vcom by subtracting the shift level from the default value if the unbalanced line is positively deflected by a predetermined shift level. On the other hand, the timing controller 51 increases the voltage of the dynamic common voltage Vcom by adding the shift level to the default value if the unbalanced line is negatively deflected by a predetermined shift level.

12 illustrates a method of driving a liquid crystal display according to an exemplary embodiment of the present invention step by step.

Referring to FIG. 12, in the driving method of the liquid crystal display according to the exemplary embodiment of the present invention, the polarity shift level is determined for each line of the input digital video data by using the aforementioned method.

In the driving method of the liquid crystal display according to the exemplary embodiment of the present invention, the deflection polarity of the unbalanced line having any polarity is determined, and when the deflection polarity is positive, the predetermined default value is obtained by subtracting a shift level value proportional to the degree of deflection. The dynamic common voltage Vcom is updated (S2 and S3).

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention updates the dynamic common voltage Vcom to a predetermined default value plus a shift level value proportional to the degree of deflection if the deflection polarity of the unbalanced line is negative. (S4 and S5)

As described above, the timing controller 51 may simultaneously process S2 to S5 through the positive count and the negative count. The flow chart of FIG. 12 is a separate processing process for convenience of explanation.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows a test pattern for experimenting with cross talk.

FIG. 2 is an enlarged view of a portion of the test pattern of FIG. 1 showing polarities of data voltages. FIG.

FIG. 3 is a diagram illustrating polarity deflection of a data voltage in an A-Line shown in FIG. 2.

4 is a diagram illustrating polarity deflection of a data voltage in a B-line shown in FIG. 2.

5 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a circuit diagram illustrating in detail the common voltage generator illustrated in FIG. 5.

7 is a diagram illustrating a count example for determining the polarity shift of the input data in horizontal 1 dot inversion.

8 is a timing sequence diagram illustrating a data update process of a common voltage generator.

9 and 10 are waveform diagrams showing vertical blank time and horizontal blank time.

FIG. 11 is a circuit diagram illustrating a processing time of a timing controller and a processing time of a data driving circuit required to load data from a data input to a liquid crystal display panel.

12 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

Description of the Related Art

50: liquid crystal display panel 51: timing controller

52: data driving circuit 53: gate driving circuit

61: data processor 62: gate / data timing signal generator

63: horizontal polarity control unit 71: polarity counter

72: Unbalance Line Counter 73: Unbalance Total Determination Unit

74: horizontal polarity conversion signal generator 91: shift register

92: data register 93: first latch

94: second latch 95: digital-to-analog converter

96: charge share circuit 97: output circuit

101: P-decoder 102: N-decoder

103A to 103D: multiplexer 104: horizontal output inversion circuit

Claims (7)

Data lines supplied with a data voltage and gate lines supplied with a gate pulse intersect with each other, and a common electrode is provided with a common voltage, and liquid crystal cells driven by a difference between the data voltage and the common voltage are arranged in a matrix form. A liquid crystal display panel; A data monitor block for determining a degree of polarization deflection for input digital video data and outputting common voltage control data for adjusting the common voltage; And And a common voltage generator for adjusting the common voltage in response to the common voltage control data. The method of claim 1, A data driving circuit which converts the input digital video data into positive / negative data voltages and outputs the data lines to the data lines; A gate driving circuit supplying the scan signals to the gate lines; And A timing controller for supplying the input digital video data to the data driving circuit and controlling operation timing of the data driving circuit and the gate driving circuit, And the data monitor block is embedded in the timing controller. The method of claim 1, The data monitor block, Separately counting the positive data and the negative data among data above a predetermined first threshold value, Comparing the difference between the sum of the count values of the positive data and the sum of the count values of the negative data for one line of data with a second predetermined threshold value; And supplying common voltage control data to the common voltage generator for adjusting the common voltage in an unbalanced line whose difference value is greater than or equal to the second threshold. The method of claim 3, wherein The data monitor block, If it is determined that the unbalanced line is deflected positively, the common voltage control data is generated by subtracting a shift level proportional to the degree of deflection from a predetermined default value, And when it is determined that the unbalanced line is negatively biased, the common voltage control data is generated by adding the shift level to the default value. Data lines supplied with a data voltage and gate lines supplied with a gate pulse intersect with each other, and a common electrode is provided with a common voltage. The liquid crystal cells driven by the difference between the data voltage and the common voltage are formed in a matrix form. In the driving method of a liquid crystal display device having a liquid crystal display panel disposed, Determining a degree of polarization deflection for the input digital video data; Generating common voltage control data for adjusting the common voltage according to the polarity deflection degree; And And adjusting the common voltage in response to the common voltage control data. The method of claim 5, Adjusting the common voltage, Counting separately the positive data and the negative data from among data above a predetermined first threshold; Comparing a difference value between the sum of the count values of the positive data and the sum of the count values of the negative data for one line of data with a second predetermined threshold; And And generating common voltage control data for adjusting the common voltage in an unbalanced line whose difference is greater than or equal to the second threshold. The method of claim 6, Adjusting the common voltage, Generating the common voltage control data by subtracting a shift level proportional to the degree of deflection from a predetermined default value when the unbalanced line is determined to be positively deflected; And And if the unbalanced line is determined to be negatively biased, generating the common voltage control data at the default value plus the shift level.

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