KR20110029503A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to form an insulation film and a sacrificial pattern with the same material, thereby simultaneously forming bit line contacts in a cell area and an area around the cell. CONSTITUTION: A conductive film(35A) and a protective film(36A) are successively formed on a substrate(31). A sacrificial pattern(37) is formed on the protective film. A conductive pattern with the sacrificial pattern is formed by etching the hard mask film, the protective film, and the conductive film. An insulation film covers the conductive pattern. A contact hole(43) exposes the protective film by etching the sacrificial pattern. The contact hole is filled with a conductive material to form a contact.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of forming a bit line contact (BLC).

In the semiconductor device, for example, the first bit line contact BLC1 and the second bit line contact BLC2 are respectively formed as bit line contacts BLC in the cell region and the peripheral region Peri in a DRAM manufacturing process. Forming. In this case, the first bit line contact is formed to connect the upper bit line and the landing plug of the lower bit in the cell region, and the second bit line contact is formed to connect the upper bit line and the lower gate electrode in the peripheral region. do.

1A and 1B are cross-sectional views illustrating a method of forming a bit line contact according to the related art.

As shown in FIG. 1A, a plurality of gates 17 are formed on a substrate 11 having a cell region and a peripheral region, and having an active region 13 defined by the device isolation layer 12. The gate 17 is a stacked structure in which the gate insulating film 14, the gate electrode 15, and the gate hard mask film 16 are sequentially stacked.

Next, after forming the spacers 18 on both side walls of the gate 17, and then forming the first insulating layer 19 to fill the gates 17, the landing plug 20 penetrating the first insulating layer 19 is formed. ).

As shown in FIG. 1B, after forming the second insulating layer 21 for forming the bit line contact on the entire surface of the substrate 11 on which the landing plug 20 is formed, the bit line contact is formed on the second insulating layer 21. A photoresist pattern (not shown) for forming a photoresist layer is formed, and the second insulating layer 21 of the cell region is etched using the photoresist pattern as an etch barrier to form a first bit line contact hole 22. The second bit line contact hole 23 is formed by etching the second insulating layer 21 and the gate hard mask layer 16 in the region.

Next, the conductive material is filled in the first and second bit line contact holes 22 and 23 to form the bit line contacts BLC and 24. That is, the first bit line contact 24A is formed in the cell region and the second bit line contact 24B is formed in the peripheral region.

Typically, the gate hard mask film 16 is formed of a nitride film, and the second insulating film 21 is formed of an oxide film, which is why the prior art first and second bit lines for forming the bit line contact 24 are formed. Since the process of forming the contact holes 22 and 23 cannot proceed simultaneously, there is a problem that the process is complicated. If the process of forming the first and second contact holes 22 and 23 is performed simultaneously, the gate hard mask layer 16 of the cell region is lost and a short is formed between the first bit line contact 24A and the gate electrode 15. It causes a problem that occurs.

In addition, in the prior art, the second bit line contact hole 23 is formed by using a dry etching method, and there is a problem in that the sidewall of the second contact hole 23 has a negative slope due to the characteristics of the dry etching method. . The sidewall having a negative slope means that the line width decreases from the upper region to the lower region, and as the sidewall of the second bitline contact hole 23 has a negative slope, the sidewall of the second bitline contact 24B Increasing the resistance of the second bit line contact 24B, such as an increase in contact resistance due to a decrease in contact area between the gate electrodes 15, or an increase in resistance due to a decrease in volume of the second bit line contact 24B, causes an increase in resistance. do.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing a resistance component of a second bit line contact formed in a peripheral region.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of simultaneously forming bit line contacts in a cell region and a peripheral region.

According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: sequentially forming a conductive film and a protective film on a substrate; Forming a sacrificial pattern on the passivation layer; Forming a hard mask layer on the passivation layer such that an upper surface is positioned on the same plane as the upper surface of the sacrificial pattern; Etching the hard mask layer, the passivation layer, and the conductive layer to form a conductive pattern including the sacrificial pattern; Forming an insulating film covering the conductive pattern; Selectively etching the insulating layer to expose the sacrificial pattern, and successively etching the sacrificial pattern to form a contact hole exposing the protective layer; And forming a contact by filling a conductive material in the contact hole.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, wherein a sacrificial pattern is sequentially formed on a portion of a gate conductive film, a protective film, and a portion of a gate scheduled area of the peripheral region on a substrate having a cell region and a peripheral region. Forming; Forming a gate hard mask layer on the passivation layer such that an upper surface is positioned on the same plane as an upper surface of the sacrificial pattern; Etching the gate hard mask layer, the passivation layer, and the gate conductive layer to form gates in the cell region and the peripheral region, respectively; Forming a plurality of landing plugs in contact with the substrate on both sides of the gate; Forming an insulating film to cover an entire surface of the substrate including the landing plug; Selectively etching the insulating layer of the cell region to form a first bit line contact hole exposing the landing plug, and selectively etching the insulating layer of the peripheral region to expose the sacrificial pattern, and subsequently Etching to form a second bit line contact hole exposing the passivation layer; And embedding a conductive material in the first and second bit line contact holes to form a first bit line contact in the cell region and to form a second bit line contact in the peripheral region.

The present invention based on the above-described problem solving means has an effect of simultaneously forming bit line contacts in a cell region and a peripheral region by providing a sacrificial pattern. In addition, there is an effect that can prevent the increase of the bit line contact resistance component in the peripheral region.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

The present invention, which will be described later, relates to a method for forming a bit line contact in a semiconductor device, and in particular, simultaneously forms a bit line contact in a cell region and a peripheral region, and reduces a resistance component of a second bit line contact formed in the peripheral region. A method for manufacturing a semiconductor device is provided.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the gate insulating layer 34 and the gate are formed on the substrate 31 having the cell region Cell and the peripheral region Peri and the active region 33 is defined by the device isolation layer 32. The sacrificial pattern 37 is sequentially formed in the conductive layer 35, the passivation layer 36, and a part of the gate predetermined region of the peripheral region.

Specifically, the sacrificial pattern 37 formed in a portion of the gate predetermined region of the peripheral region is preferably formed in the region where the second bit line contact of the peripheral region is to be formed. The sacrificial pattern 37 serves to reduce the difficulty of the bit line contact hole forming process for the subsequent bit line contact and to increase the contact area between the second bit line contact and the gate electrode. It can be formed as. In this case, the sacrificial pattern 37 may be formed such that the sidewalls have a positive slope so that the contact area between the second bit line contact and the gate electrode and the volume of the second bit line contact are easily increased. The sacrificial pattern 37 having a positive slope of the side wall means that the line width of the pattern increases from the upper region to the lower region. As a result, the sacrificial pattern 37 has a bottom line width W2 greater than the top line width W1. Is bigger.

The sacrificial pattern 37 may be formed through a series of processes in which a sacrificial layer (not shown) is deposited on the entire surface of the passivation layer 36 and then the mask for the second bit line contact is etched using the etch barrier.

The passivation layer 36 serves to prevent the gate conductive layer 35 from being damaged during the process of forming the sacrificial pattern 37. The protective layer 36 may be formed of a material having an etching selectivity with respect to the sacrificial pattern 37. In addition, the passivation layer 36 serves as a part of the gate electrode after the time point at which the gate patterning is completed. Accordingly, the protective film 36 is formed of a conductive material, but is formed of a conductive nitride film such as titanium nitride (TiN), tungsten nitride (WN), or the like having excellent barrier properties with respect to the sacrificial pattern 37 made of an oxide film. It is preferable. The conductive nitride film serving as the protective film 36 may be formed by nitriding the surface of the gate conductive film 35, or may be formed through a separate deposition process.

The device isolation layer 32 may be formed through a shallow trench isolation (STI) process. The gate insulating film 34 may be formed of an oxide film, eg, a silicon oxide film (SiO ₂ ) through an oxidation process or a deposition process. The gate conductive film 35 may be formed of a single film made of a silicon film or a metallic film, or a laminated film in which they are stacked. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like can be used. As the metallic film, tungsten (W), titanium (Ti), titanium nitride film (TiN), tungsten silicide film (WSi), etc. Can be used.

As shown in FIG. 2B, the gate hard mask layer 38 is formed on the passivation layer 36 to cover the sacrificial pattern 37. In this case, the gate hard mask layer 38 may be formed of a material having an etching selectivity with the sacrificial pattern 37. For example, when the sacrificial pattern 37 is formed of an oxide film, the gate hard mask film 38 is preferably formed of a nitride film.

Next, the gate hard mask film 38 is planarized to expose the top surface of the sacrificial pattern 37. The planarization process can be carried out using chemical mechanical polishing (CMP).

Through the above-described process, the gate hard mask layer 38 may be formed on the passivation layer 36 on the same plane as the top surface of the sacrificial pattern 37.

As shown in FIG. 2C, the gate hard mask layer 38, the passivation layer 36, the gate conductive layer 35, and the gate insulating layer 34 are sequentially etched to form the gate 39 in the cell region and the peripheral region, respectively. Form. Hereinafter, the reference numerals of the etched gate hard mask layer 38, the passivation layer 36, and the gate insulating layer 34 are changed to '38A', '36A', and '34A', respectively, and the gate conductive layer 35 is represented. Is changed to the gate electrode 35A.

Here, the gate 39 formed in the peripheral region is formed to include the sacrificial pattern 37 inside the gate hard mask film 38A. This is because the sacrificial pattern 37 is formed using a mask for the second bit line contact.

Next, spacers 46 are formed on both side walls of the gate 39. The spacer 46 may be formed by depositing an insulating film for a spacer along the surface of the structure including the gate 39 and then performing an etch back on the entire surface, for example, a first insulating film to be formed through a subsequent process. It is preferable to form with a material having an etch selectivity. For example, the spacer 46 may be formed of a nitride film.

As shown in FIG. 2D, after the first insulating film 40 is formed on the entire surface of the substrate 31 so as to fill the gaps between the gates 39, the substrate 31 on both sides of the gate 39 passes through the first insulating film 40. ) A plurality of landing plugs 41 are formed.

As shown in FIG. 2E, a second insulating layer 42 is formed on the entire surface of the substrate 31 including the landing plug 41 to provide bit line contacts. In this case, the second insulating layer 42 may be formed of a material having an etch selectivity with respect to the gate hard mask layer 38A and no etch selectivity with respect to the sacrificial pattern 38. That is, when the gate hard mask film 38A is formed of a nitride film, the second insulating film 42 is preferably formed of the same oxide film as the sacrificial pattern 37.

Next, after forming a photoresist pattern (not shown) for the bit line contact on the second insulating layer 42, the second insulating layer 42 of the cell region is etched using the photoresist pattern as an etch barrier to form the landing plug 41. While forming the first bit line contact hole 43 exposing the top surface, the second insulating layer 42 of the peripheral area 42 is etched to expose the sacrificial pattern 37, and the sacrificial pattern 37 continuously exposed. ) Is formed to form a second bit line contact hole 44 exposing the passivation layer 36A.

Here, as the sidewall of the sacrificial pattern 37 is formed to have a positive slope, a part of the sidewall of the second bit line contact hole 44 also has a positive slope. As a result, an internal volume of the second bit line contact hole 44 may be increased to increase the volume of the second bit line contact to be formed through a subsequent process, thereby reducing the resistance component of the second bit line contact, By increasing the contact area between the line contact and the gate electrode 35A, the contact resistance therebetween can be reduced more effectively.

In addition, by forming the second insulating layer 42 and the sacrificial pattern 37 with the same material, the first bit line contact hole 43 in the cell region and the second bit line contact hole 44 in the peripheral region are simultaneously formed. The process can be simplified, and even if the first and the first bit line contact holes 43 and 44 are formed at the same time, defects caused by the loss of the gate hard mask film 38A in the cell region can be prevented. .

Next, the protective layer 36A is additionally etched under the second bit line contact hole 44 to expose the gate electrode 35A. This is to more effectively reduce the contact resistance between the second bit line contact and the gate electrode 35A formed through the subsequent process. On the other hand, since the protective film 36A is formed of a conductive material, the etching process of the protective film 36A may be omitted in some cases.

As illustrated in FIG. 2F, conductive materials are filled in the first and second bit line contact holes 43 and 44 to form bit line contacts 45 and BLC. That is, the first bit line contacts 45A and BLC1 are formed in the cell region and the second bit line contacts 45B and BLC2 are formed in the peripheral region.

Next, although not shown in the figure, a bit line is formed on the second insulating film 42 so as to contact the first and second bit line contacts 45A and 45B.

As described above, according to the present invention, the sacrificial pattern 37 may be formed to simultaneously form the first and second bit line contacts 45A and 45B, thereby simplifying the process, and the resistance of the second bit line contact 45B. The ingredients can be reduced.

In addition, according to the present invention, the protective layer 36A may be prevented from damaging the gate conductive layer 35 or the gate electrode 35A due to the sacrificial pattern 37.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A and 1B are cross-sectional views illustrating a method of forming a bit line contact according to the related art.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32 device isolation film

33: active region 34, 34A: gate insulating film

35: gate conductive film 35A: gate electrode

36, 36A: protective film 37: sacrificial pattern

38, 38A: gate hard mask film 39: gate

40: first insulating film 41: landing plug

42: second insulating film 43: first bit line contact hole

44: second bit line contact hole 45: bit line contact

45A: first bit line contact hole (BLC1) 45B: second bit line contact hole (BLC2)

46: spacer

Claims (16)

Sequentially forming a conductive film and a protective film on the substrate; Forming a sacrificial pattern on the passivation layer; Forming a hard mask layer on the passivation layer such that an upper surface is positioned on the same plane as the upper surface of the sacrificial pattern; Etching the hard mask layer, the passivation layer, and the conductive layer to form a conductive pattern including the sacrificial pattern; Forming an insulating film covering the conductive pattern; Selectively etching the insulating layer to expose the sacrificial pattern, and successively etching the sacrificial pattern to form a contact hole exposing the protective layer; And Forming a contact by filling a conductive material in the contact hole Semiconductor device manufacturing method comprising a. The method of claim 1, And etching the passivation layer under the contact hole prior to forming the contact. The method of claim 1, The sacrificial pattern is a semiconductor device manufacturing method for forming a sidewall has a positive slope. The method of claim 1, And forming the hard mask layer from a material having an etching selectivity with the sacrificial pattern and the insulating layer. The method of claim 4, wherein The sacrificial pattern and the insulating film may include an oxide film, and the hard mask film may include a nitride film. The method of claim 1, The protective film is a semiconductor device manufacturing method, characterized in that formed with a conductive material having an etch selectivity with respect to the sacrificial pattern. The method of claim 6, The protective film includes a semiconductor nitride film manufacturing method. The method of claim 1, The conductive pattern includes a gate, a bit line or a metal wiring. Sequentially forming a sacrificial pattern on the gate conductive layer, the passivation layer, and a portion of the gate predetermined region of the peripheral region on a substrate having a cell region and a peripheral region; Forming a gate hard mask layer on the passivation layer such that an upper surface is positioned on the same plane as an upper surface of the sacrificial pattern; Etching the gate hard mask layer, the passivation layer, and the gate conductive layer to form gates in the cell region and the peripheral region, respectively; Forming a plurality of landing plugs in contact with the substrate on both sides of the gate; Forming an insulating film to cover an entire surface of the substrate including the landing plug; Selectively etching the insulating layer of the cell region to form a first bit line contact hole exposing the landing plug, and selectively etching the insulating layer of the peripheral region to expose the sacrificial pattern, and subsequently Etching to form a second bit line contact hole exposing the passivation layer; And Filling a first bit line contact in the cell region by filling a conductive material in the first and second bit line contact holes and forming a second bit line contact in the peripheral region Semiconductor device manufacturing method comprising a. 10. The method of claim 9, Prior to forming the first and second bit line contacts, And etching the passivation layer under the second bit line contact hole. 10. The method of claim 9, Forming the sacrificial pattern, Forming a sacrificial layer on the passivation layer; And Etching the sacrificial layer using the mask for the second bit line contact hole as an etch barrier Semiconductor device manufacturing method comprising a. 10. The method of claim 9, The sacrificial pattern is a semiconductor device manufacturing method for forming a sidewall has a positive slope. 10. The method of claim 9, And forming the hard mask layer from a material having an etch selectivity with the sacrificial pattern and the insulating layer. The method of claim 13, The sacrificial pattern and the insulating film may include an oxide film, and the hard mask film may include a nitride film. 10. The method of claim 9, The protective layer is formed of a conductive material having an etch selectivity with respect to the sacrificial pattern. The method of claim 15, The protective film includes a semiconductor nitride film manufacturing method.

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