KR20110025680A - Capacitance measurement circuit - Google Patents

Abstract

PURPOSE: A capacitance measuring circuit is provided to arrange a pad to which capacitance is applied from the outside in a feedback loop and successively increase a capacitance value to reduce an influence of noise of the pad, thereby accurately a capacitance value. CONSTITUTION: A pulse signal generating unit(210) generates a pulse signal by varying the pulse width of a clock signal in response to a capacitance value. A pulse signal transmitting unit(220) includes a pad, which takes capacitance from the outside, and transmits a pulse signal or prevents a pulse signal from being transmitted according to capacitance. A digital filter(242) filters a counting value to output a capacitance value.

Description

Capacitance measurement circuit

The present invention relates to a capacitance measurement circuit, and more particularly to a capacitance measurement circuit that can reduce noise.

A capacitance measurement circuit is a circuit for measuring capacitance, and is mainly used for measuring capacitance of various circuits or devices. However, recently, as portable devices provide user interfaces such as touch pads, touch screens, and access detection sensors, a range of application of capacitance measurement circuits capable of detecting a user's touch and approach is expanding.

1 is a view showing an example of a conventional touch sensor is disclosed in Korean Patent No. 0683249. The touch sensor of FIG. 1 includes a measurement signal generator 10, a reference signal generator 20, a plurality of sensing signal generators 30-1 to 30-n, and a plurality of variable delay units 35-1 to 35-. n), a plurality of contact signal generators 40-1 to 40-n, and a controller 50.

The measurement signal generator 10 generates a clock signal as a measurement signal in and applies the clock signal to the reference signal generator 20 and the plurality of sensing signal generators 30-1 to 30-n, respectively.

The reference signal generator 20 includes a first resistor R1-1 and a capacitor C, and always delays the measurement signal in for a predetermined time regardless of whether the contact object is in contact with the reference signal ref. ). The first resistor R1-1 and the capacitor C are for setting the delay value of the reference signal ref for the variable delay signals vsen2-1 to vsen2-n.

Each of the plurality of sensing signal generators 30-1 to 30-n may include second resistors positioned between the measurement signal generator 10 and each of the variable delay units 35-1 to 35-n. A contact object having a capacitance located between R2-1 to R2-n, each of the second resistors R2-1 to R2-n and the plurality of variable delay units 35-1 to 35-n contacts A pad PAD is provided. Each of the plurality of second resistors R2-1 to R2-n adjusts the delay component between the measurement signal generator 10 and each of the plurality of pads PAD to be the same. Each of the sensing signal generators 30-1 to 30-n includes a pad PAD to which a contact object is in contact, and when the contact object contacts the pad PAD, the measurement signal in is converted into a reference signal ( Delay more than ref, and if it is not touched delays the measured signal in less than the reference signal (ref) so that the difference between the reference signal (ref) and the delay time (sen2-1 ~ sen2-n) Generates.

The contact object may be any object having a predetermined capacitance, and a representative example is a human body capable of accumulating a large amount of charge.

Each of the variable delay units 35-1 to 35-n adjusts the delay times of the sensing signals sen2-1 to sen2-n in response to the control signals D1 to Dn supplied from the controller 50. The variable delay signals vsen2-1 to vsen2-n are output according to the variable and variable delay time. Each of the variable delay units 35-1 to 35-n may include a plurality of delay cells and a buffer, and each of the plurality of delay cells may include one multiplexer and two inverters.

The multiplexer includes a selection input for selecting one of two inputs, one output, and two inputs, the selection inputs corresponding control signals of control signals D1 to Dn supplied from the controller 50. Controlled by The two inverters serve to delay the output of the multiplexer by a predetermined time.

Each of the plurality of touch signal generators 40-1 to 40-n samples and latches the variable delay signals vsen2-1 to vsen2-n in synchronization with the reference signal ref to generate contact signals S1 to Sn. ) Each of the plurality of contact signal generators 40-1 to 40-n receives the variable delay signals vsen2-1 to vsen2-n from the corresponding variable delay units 35-1 to 35-n, and references A D flip-flop is configured to receive the reference signal ref of the signal generator 20 through the clock input CLK and generate contact signals S1 to Sn.

The controller 50 detects that the touch sensor is in an operating state when the contact object contacts the pad PAD and the contact signals S1 to Sn continuously change, and the contact signal generators corresponding to the contact pad PAD are detected. The touch signals S1 to Sn are received from the 40-1 to 40-n to generate the contact outputs Tout-1 to Tout-n, and the contact object does not come into contact with the pad PAD. If S1 to Sn do not change for a predetermined time, the controller 50 detects that the touch sensor is in a standby state, and is supplied to each of the plurality of variable delay units 35-1 to 35-n to adjust the delay time. Start adjusting the control signal.

2 is a diagram illustrating another example of a conventional touch sensor, and is disclosed in Korean Patent No. 0802656. The pulse signal generator 60 sets the pulse width of the pulse signal pul according to the code value of the control code Code transmitted from the controller 90, and generates a pulse signal pul having the set pulse width. .

The pulse signal generator 60 includes a clock signal generator 61, a variable delay chain VDC, an inverter INV, and an AND gate AND. The clock signal generator 61 generates a clock signal clk and transmits the generated clock signal clk to the variable delay chain VDC and the AND gate AND, respectively. The variable delay chain VDC varies the delay time of the clock signal clk in response to the code value of the control code Code transmitted from the controller 90. The inverter INV inverts the clock signal dclk output from the variable delay chain VDC. The AND gate AND is combined with the clock signal clk transmitted from the clock signal generator 61 and the clock signal / dclk transmitted through the variable delay chain VDC and the inverter INV to perform a variable delay chain ( A pulse signal pul having a pulse width corresponding to the delay time of the VDC) is generated.

The pulse signal transmission unit 70 including the resistor R3 and the pad PAD transmits the pulse signal pul to the pulse signal detection unit 80 as it is when the contacting object is not in contact with the pad PAD. When a contact object having a capacitance is touched, the pulse signal pul is not transmitted to the pulse signal detector 80 by the capacitance of the contact object applied to the pad PAD.

In this case, the contact object may be any object having a predetermined capacitance may be applied, a representative example is a human body that can accumulate a lot of charge.

The pulse signal detector 80 detects a pulse signal pul transmitted by the pulse signal transmitter 70, and notifies the controller 90 of the detection result. The pulse signal detector 80 may be implemented as a T-flip flop (TFF).

T-Flip-Flop (TFF) toggles the output signal in synchronization with the rising or falling edge of the pulse signal pul when the pulse signal pul is delivered, and toggles the output signal when the pulse signal pul is not delivered. Do not ring.

The control unit 90 generates an output signal (out) for notifying whether a contact object is in contact with the detection result of the pulse signal detection unit 80 and outputs it to an external device, and periodically performs a calibration operation to pulse under a non-contact state. The pulse width of the signal pul is corrected for the current operating environment. The control unit 90 outputs an output signal that notifies that the contact object is not contacted when the T-flip-flop TFF outputs an output signal that is toggled, or outputs an output signal that notifies that the contact object has been contacted. Create and output to the outside.

1 and 2 only detects and outputs contact or non-contact, and does not output the magnitude of capacitance. In addition, the portable device frequently changes the surrounding environment due to its characteristics, and a capacitance measurement circuit is required to reduce the influence of noise so that the portable device does not malfunction due to various noises caused by the change of the environment.

An object of the present invention is to provide a capacitance measurement circuit that can reduce the influence of noise.

The capacitance measurement circuit of the present invention for achieving the above object comprises a measurement signal generator for generating a measurement signal, a fixed delay chain for delaying the measurement signal for a time corresponding to a reference delay value, and outputting the measurement signal to a code value. A variable delay chain for delaying and outputting a delayed signal for a corresponding time, a first delay unit for outputting a reference signal by delaying an output signal of the fixed delay chain by a fixed time, and a pad receiving capacitance from the outside; A second delay unit for outputting a sensing signal by variably delaying an output signal of a chain in response to a capacitance applied through the pad; and increasing or decreasing the capacitance value in response to a delay time difference between the reference signal and the sensing signal. Outputting the code value by varying the code value in response to the capacitance value And a data generator.

The data generator of the present invention for achieving the above object is a phase detector for outputting a detection signal in response to the difference between the delay time of the reference signal and the sensing signal, and sequentially in accordance with the specified rule capacitance value in response to the detection signal And a delay pump configured to increase or decrease the output value and to vary the code value in response to the capacitance value to output the variable value to the variable delay chain.

The phase detection unit of the present invention for achieving the above object is a flip-flop as a logic circuit for outputting the detection signal by latching the sensing signal in synchronization with the rising or falling edge of the reference signal.

Capacitance measurement circuit of the present invention for achieving the above object is a delay pump in response to the detection signal to increase or decrease the capacitance value in accordance with a specified rule, and outputs a counter, and subtracts the capacitance value from the reference delay value It characterized in that it comprises a subtractor for outputting the code value.

The counter of the present invention for achieving the above object is characterized in that the capacitance value is sequentially increased or decreased in a predetermined unit in response to the detection signal.

The counter of the present invention for achieving the above object is characterized in that when the detection signal is continuously applied at a high level or a low level, it is output in increments or decreases sequentially while varying in units of change of capacitance value.

The delay pump of the present invention for achieving the above object is further characterized by further comprising a digital filter for filtering and outputting the code value or the capacitance value.

The digital filter of the present invention for achieving the above object is characterized in that the low pass filter or the band pass filter is applied to stabilize the code value or capacitance value, and remove the noise.

A pulse signal generator for generating a pulse signal by varying the pulse width of the clock signal in response to the capacitance value of the present invention for achieving the above object, the pad having a capacitance applied from the outside, the pulse signal to the pad A pulse signal transfer unit for transmitting or not transmitting the pulse signal in response to the capacitance applied through the pulse signal; a pulse signal detector for periodically detecting the pulse signal applied through the pulse signal transfer unit and outputting a detection signal to the detection signal; And a counter for sequentially increasing or decreasing a counting value in response to a specified rule, and a digital filter for filtering the counting value and outputting the capacitance value.

The pulse signal generator of the present invention for achieving the above object is a clock signal generator for generating the clock signal, a variable delay chain for varying and delaying the clock signal according to the capacitance value, the inverted output signal of the variable delay chain And an AND gate for generating the pulse signal having a pulse width corresponding to the delay time of the clock signal by performing an AND operation on the inverter and outputting the clock signal and the output signal of the inverter.

The pulse signal detection unit of the present invention for achieving the above object detects the pulse signal in response to a clock signal, and generates a T-flip flop, and outputs a toggle signal in response to the pulse signal, and the T-flip flop It is characterized in that it comprises a period discriminator for outputting a detection signal by determining whether the output signal of the toggling periodically.

The pulse signal detection unit of the present invention for achieving the above object is an SR flip-flop for outputting the detection signal in response to the pulse signal applied to any one of a set terminal or a reset terminal, the detection signal in response to the clock signal And a mux for transmitting the pulse signal by selecting one of the set terminal or the reset terminal in response to an output signal of the D-flip flop.

The counter of the present invention for achieving the above object is characterized in that the capacitance value is sequentially increased or decreased in a predetermined unit in response to the detection signal.

The counter of the present invention for achieving the above object is characterized in that when the detection signal is continuously applied at a high level or a low level, it is output in increments or decreases sequentially while varying in units of change of capacitance value.

Accordingly, in the capacitance measurement circuit of the present invention, since the pad receiving the capacitance from the outside is disposed inside the feedback loop, the capacitance value is decreased by the noise applied through the pad as the capacitance value is sequentially increased or decreased, thereby measuring the accurate capacitance value. can do.

1 is a view showing an example of a conventional touch sensor.
2 is a view showing another example of a conventional touch sensor.
3 is a diagram illustrating an example of a capacitance measurement circuit according to the present invention.
4 is a diagram illustrating a capacitance measurement circuit of FIG. 3, illustrating an example of a delay time calculation and a data generator.
5 to 7 are views for explaining the operation of the capacitance measurement circuit of FIG.
8 is a diagram illustrating another example of a capacitance measurement circuit according to the present invention.
FIG. 9 is a diagram illustrating an embodiment of the T-flip flop of FIG. 8.

Hereinafter, a capacitance measurement circuit of the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating an example of a capacitance measurement circuit according to the present invention. The capacitance measurement circuit of FIG. 3 includes a measurement signal generator 110, a variable delay unit 120, a fixed delay unit 130, and a delay time calculation and data generator 140 similar to the touch detection sensor of FIG. 1. do. The measurement signal generator 110 may be implemented as a clock generation circuit that generates a clock signal having a predetermined period as the measurement signal in.

The variable delay unit 120 includes a variable delay chain VDC and a resistor R1 connected in series between the measurement signal generator 110 and the data generator 140. The pad PAD is connected between the resistor R1 and the data generator 140 to receive a capacitance from the outside. The variable delay chain VDC variably delays the measurement signal in in response to a code value Code fed back from the delay pump 142 and outputs the resistor R1 and the pad PAD. The variable delayed measurement signal applied at (VDC) is delayed according to the resistance value of the resistor R1 and the capacitance applied through the pad PAD, so that the sensing signal sen is transferred to the delay time calculation and data generator 140. Output

The fixed delay unit 130 includes a fixed delay chain FDC and a resistor R2 connected in series between the measurement signal generator 110 and the data generator 140 in parallel with the variable delay unit 120. . The fixed delay chain FDC compensates for the offset capacitance of the pad PAD to maximize the measurement range of the capacitance, so as to adjust the zero point of the code value applied to the variable delay chain. Nref) is authorized. The fixed delay chain FDC delays and outputs the measurement signal in in response to the reference delay value Nref, and the resistor R2 delays and outputs the measured signal output from the fixed delay chain FDC according to the resistance value. In addition, a delay is output to the delay time calculation and data generator 140.

The fixed delay chain FDC and the variable delay chain VDC may be composed of a plurality of delay cells as shown in the variable delay chains 35-1 to 35-n of FIG. 1, and each of the plurality of delay cells is a multiplexer. (MUX) and two inverters. The fixed delay chain FDC selects delay cells that delay the measurement signal in in response to the reference delay value Nref, and the variable delay chain VDC selects the measurement signal in in response to the code value Code. Select delay cells that delay.

The delay time calculation and data generator 140 includes a phase detector 141 and a delay pump 142. The phase detector 141 determines whether the phase of the sensing signal sen with respect to the reference signal ref is fast or slow and outputs a detection signal det. The delay pump calculates the capacitance value CV in response to the sense signal det, and up or down the code value Code in response to the calculated capacitance value CV. Output

In the capacitance measurement circuit of FIG. 3, in the variable delay unit 120 and the fixed delay unit 130, the variable delay chain VDC and the fixed delay chain FDC respectively measure the measurement signal in from the measurement signal generator 110. Licensed directly. Therefore, the pad PAD to which the capacitance is applied from the outside is disposed between the variable delay chain VDC to which the capacitance value CV is fed back and the delay time calculation and data generator 140 to output the capacitance value CV. Therefore, the pad PAD is disposed inside the feedback loop.

Noise can also occur inside the capacitance measurement circuitry, but most often it comes from the outside through a pad (PAD). In other words, in order to reduce noise, it is most efficient to remove noise applied through the pad PAD. However, in the touch sensing sensor of FIG. 1, it is difficult to reduce noise applied through the pad PAD because the pad PAD is connected to the outside of the feedback loop. In contrast, in the capacitance measurement circuit of FIG. 3, a pad PAD receiving capacitance from the outside is connected to the inside of the feedback loop. When the pad is connected to the inside of the feedback loop, it is possible to attenuate noise by the characteristics of the feedback loop.

FIG. 4 is a diagram illustrating the capacitance measurement circuit of FIG. 3, illustrating an implementation example of a delay time calculation and a data generator. In FIG. 4, the measurement signal generator 110, the variable delay unit 120, and the fixed delay unit 130 are the same as in FIG. 3 and will not be described separately.

In the delay time calculation and data generator 140 of FIG. 4, the phase detector 141 is implemented as a D-flip flop DFF, and the delay pump 142 includes a counter CNT and a subtractor sub. The D-flip-flop DFF latches and outputs the sensing signal sen in synchronization with one of the rising or falling edges of the reference signal ref. The D-flip-flop DFF outputs a low level detection signal det when the delay of the sensing signal sen is less than the reference signal ref and the delay of the sensing signal sen is greater than the reference signal ref. In this case, a high level detection signal det is output. When the detection signal reaches a low level, the delay pump 142 increases the code value Code. When the detection signal reaches a high level, the delay pump 142 decreases the code value Code. The phase of the output signal sen of the variable delay unit 120 is controlled to match the phase of the output signal ref of the fixed delay unit 130. Delay offset may occur between the fixed delay unit 130 and the variable delay unit 120 by the pad PAD. If this offset is larger than the adjustment range of the variable delay chain, the operation range of the capacitance measurement circuit of FIG. Will escape. In this case, the reference delay value Nref of the fixed delay unit 130 compensates for the offset capacitance so that the code value Code of the variable delay chain falls within the variable delay range. In FIG. 4, a D-flip-flop (DFF) is used as an example of the phase detector 141, but it may be implemented in another logic circuit.

The counter CNT is an up / down counter which outputs the capacitance value CV up or down in response to the sensing signal det. The counter CNT may output the capacitor value CV up or down in units of 1 bit according to the level of the detection signal det. However, when the counter CNT outputs the capacitance value CV up or down in units of 1 bit, the capacitance measurement time is long when the capacitance applied through the pad PAD is large. To counter this problem, the counter does not up / down the capacitance value CV in units of 1 bit, and when the sensing signal is continuously applied at a high level or a low level, 1 counter, 2 bits, The capacitance value CV may be output up or down in proportion to a multiplier of 2 in the order of 4 bits and 8 bits, or may be output by up or down the capacitance value CV according to a predetermined rule. In addition, although the counter CNT is shown to receive the detection signal det in response to the reference signal ref, the detection signal det may be applied in response to the measurement signal in.

The subtractor sub outputs a code value Code by subtracting the capacitance value CV from the reference delay value Nref. Therefore, the capacitance value CV represents the total capacitance value applied to the pad PAD. When the capacitance value applied to the pad PAD increases, the feedback loop composed of the phase detector 141 and the delay pump 142 is a pad. Reduce the delay of the variable delay chain by reducing the code value by the increase in capacitance applied through PAD. In addition, when the capacitance value applied to the pad PAD decreases, the code value Code is increased by the decrease to increase the delay amount of the variable delay chain. As a result, the phases of the sensing signal sen and the reference signal ref input to the phase detector 141 are controlled to be the same, so that the capacitance value CV corresponds to the magnitude of the capacitance applied to the pad PAD. do.

Here, the signals for controlling the reference delay value Nref and the fixed delay chain FDC applied to the subtractor sub are described in the same manner, but it can be controlled differently. 3 and 4 illustrate that there is a fixed delay chain (FDC), it can be deleted.

5 to 7 are diagrams for describing an operation of the capacitance measurement circuit of FIG. 4. First, FIG. 5 illustrates a change in a sensing signal sen and a sensing signal det when a capacitor is applied to the pad PAD. Drawing.

The reference signal ref is output by delaying the measurement signal in by the fixed delay time by the fixed delay unit 130, and thus has the same period as the measurement signal in. Since the capacitance value CV is zero at the initial operation of the capacitance measurement circuit, the initial code value Code is equal to the reference delay value Nref, and the time for which the variable delay chain VDC delays the measurement signal in. Is equal to the time that the fixed delay chain FDC delays the measurement signal in. Therefore, at the beginning of the operation of the capacitance measurement circuit, the sensing signal sen is delayed more than the reference signal ref by the capacitance of the pad PAD itself and is output as the D-flip-flop DFF.

Since the sensing signal sen is delayed more than the reference signal ref, the sensing signal sen is at the high level and the sensing signal det is output at the high level at the falling edge of the reference signal ref. Since the detection signal det is at a high level, the counter CV increases the capacitance value CV to output 1, and the subtractor subtracts the capacitance value CV from the reference delay value Nref. The code value Code is pumped down and output as the reference delay value Nref-1.

The variable delay chain VDC outputs the delay time of the measurement signal in in response to the code value Code, and the delay time difference with the reference signal ref as the delay time of the sensing signal sen decreases. Will be reduced. When the delay time difference between the sensing signal sen and the reference signal ref gradually decreases, the delay time of the sensing signal sen becomes equal to or shorter than the delay time of the reference signal ref (t1). The D-flip-flop DFF causes the detection signal det to transition to a low level.

Thereafter, when capacitance is applied from the outside through the pad PAD (t2), the sensing signal sen is additionally delayed by the applied capacitance, and the D-flip-flop DFF outputs a high level sensing signal det. do. When the sense signal det is output at a high level, the capacitance value CV gradually increases until the delay time of the sensing signal sen becomes equal to or shorter than the delay time of the reference signal ref as described above. (T3). After that, the capacitance value CV is repeated to increase and decrease.

FIG. 6 shows a change in the capacitance value CV of a capacitance measurement circuit having a counter CV which up / down the capacitance value CV by 1 bit, and FIG. 7 shows the capacitance value CV according to a specified rule. The change of the capacitance value CV of the capacitance measurement circuit having a counter CV up / down is shown.

 In FIG. 6, since the counter CNT performs up / down by one bit, the time required for the capacitance value CV to represent the applied capacitance is long when the capacitance applied through the pad PAD is large. . However, since the counter CNT performs up / down in units of 1 bit, the capacitance value CV fluctuated by the noise is 1 bit and has a small influence on the capacitance value CV even when a large amount of noise is temporarily applied.

In FIG. 7, the counter CNT is configured to increase or decrease the number of bits to be up / down when the detection signal det is applied to the high level or the low level three times in succession as a rule of up / down the capacitance value CV. An example is shown. That is, when the sensing signal det is continuously applied at a high level, the number of bits to be up every three times is increased. For example, when the sensing signal det is continuously applied at the high level or the low level, the capacitance value of one bit is changed for three times, and the capacitance value of two bits is changed for three times. When the signal is inverted to the low level of the sensing signal det, the capacitance value CV is decreased by decreasing the number of bits previously up / down. Therefore, even when a large capacitance is applied, the capacitance value CV can be represented within a short time. Although the capacitance value CV of FIG. 7 may change to a width larger than the capacitance value CV of FIG. 6 when noise occurs, the influence of noise on the capacitance value CV is small because the limit of the change width is not large. . In particular, as the pad PAD is disposed inside the feedback loop, the variable delay chain VDC is directly applied with the measurement signal in which no noise is included, and the code value considering the noise applied through the pad PAD ( It outputs with delay in response to Code), which reduces the noise by the characteristics of the feedback loop.

In the above description, the data generator 140 includes the D-flip flop DFF and the up / down counter CV to gradually increase or decrease the capacitance value CV. The delay time difference of the sensing signal sen may be directly counted to immediately output the capacitance value CV applied to the pad PAD.

In addition, the delay pump 142 may further include a digital filter that filters and outputs the capacitance value CV to remove noise. In the above embodiment, since the capacitance value CV is configured to output a limited width of the change, the code value Code is also limited in the width of the change. However, if the code value changes by more than a certain level, it may be determined that noise is included. Therefore, a digital low pass filter or a digital band pass filter may be further provided as a digital filter that receives the code value Code from the subtractor sub and filters the code value Code. In addition, it is obvious that the same effect can be obtained by directly filtering the capacitance value CV without filtering the code value Code. Digital filters can also be used to adjust the characteristics of the feedback loop along with the noise characteristics of the capacitance measurement circuit. When the delay time difference between the reference signal ref and the sensing signal sen is sufficiently reduced and the feedback loop is stabilized, the capacitance value CV is oscillated (repeats and decreases) in units of + 1 / -1. This can be fixed using a digital filter. In other words, the hysteresis characteristic may be applied to the digital filter to prevent minute oscillation (continuous variation) of the capacitance value CV in a steady state.

In addition, the counter CNT and the digital filter may be implemented in software as well as hardware.

8 is a diagram illustrating another example of a capacitance measurement circuit according to the present invention. Since the pulse signal generator 210 and the pulse signal transmitter 220 have a structure similar to that of FIG. 2, detailed description thereof will be omitted.

In FIG. 2, the pulse signal detector 80 uses only a T-flip flop (TFF). However, as described above, most of the noise is often applied through the pad PAD, and since the T-flip flop TFF of FIG. 2 is directly connected to the pad PAD, noise is applied to the pulse signal through the pad. There is a possibility that the T-flip-flop (TFF) toggles more than once in one pulse signal when applied. In order for the period discriminator 232 in FIG. 8 to correctly determine the periodicity of the pulses, it is required that the T-flip-flop TFF is toggled only once for one pulse input. In order to solve this problem, the T-flip-flop (TFF) of FIG. 8 is to be toggled only once for one pulse input, which is the same as the toggle circuit of FIG.

Since the pulse signal detector 230 of FIG. 8 receives the pulse signal pul in response to the clock signal clk, the output signal of the T-flop flop 231 is toggled due to noise. Do not ring. In addition, the pulse signal detector 230 of FIG. 8 further includes a period discriminator 232 that determines whether the output signal of the T-flip flop 231 is periodically toggled. The period discriminator 232 determines whether the output signal of the T-flip flop 231 periodically transitions in response to the clock signal clk, and when the output signal of the T-flip flop 231 transitions periodically, A low level sense signal det is output, and if it does not transition periodically, a high level sense signal det is output.

Although the touch detection sensor of FIG. 2 detects only contact or non-contact, the capacitance measurement circuit of FIG. 8 measures the magnitude of the capacitance applied through the pad PAD, and thus outputs a capacitance value CV, thus delaying the pump 240. 4 includes a counter 241 and a digital filter 242. The counter 241 receives a sensing signal det in response to the clock signal clk as an up / down counter, and outputs a counter value Cout up or down according to a 1-bit unit or a specified rule. The digital filter 242 is used to adjust the characteristics of the feedback loop together with the noise characteristics of the capacitance measurement circuit as described above. The digital filter 242 has a hysteresis characteristic and filters the counter value CV to filter the capacitance value CV. By outputting it, it is possible to prevent continuous fluctuations in the capacitance value CV.

In the above description, the counter 241 receives the sensing signal det in response to the clock signal clk. However, when the counter 241 is an asynchronous counter, the clock signal clk may not be applied. The period discriminator 232 may also use a signal other than the clock signal clk to determine whether to periodically toggle the output signal of the T-flip-flop 231.

8, the variable delay chain VDC variably delays the clock signal clk in response to the capacitance value CV.

FIG. 9 is a toggle circuit showing an embodiment of the T-flip-flop of FIG. 8 and includes one mux, an SR flip-flop (SRF), and a D-flip-flop (DF).

The mux 331 receives a pulse signal pul in response to the output signal of the D-flop flop 333 and applies the pulse signal pul to the set terminal S or the reset terminal R of the SR flip-flop 332. The mux 331 applies a pulse signal pul to the set terminal S when the sensing signal det is applied at a low level, and resets the pulse signal pul when the sensing signal det is high. Is applied.

The SR flip-flop 332 maintains the level of the previous monitoring signal det if the pulse signal is not applied from the mux 331, and the high level detection signal when the high level signal is applied to the set terminal S. Det is output to the delay pump 340, and when a high level signal is applied to the reset terminal R, a low level detection signal det is output.

The D-flip-flop 333 latches the detection signal det in response to the clock signal clk applied from the clock signal generator 311 and outputs the detected signal det to the mux 331. The D-flip-flop 333 latches the detection signal det in response to the clock signal clk so that the output signal of the mux 331 is set terminal S or reset terminal R of the SR flip-flop 332. Determine which one of the terminals is applied.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to make various modifications and changes to the present invention without departing from the spirit and scope of the invention as set forth in the claims below. Will understand.

Claims (9)

A pulse signal generator for generating a pulse signal by varying a pulse width of a clock signal in response to a capacitance value;
A pulse signal transmission unit having a pad to which capacitance is applied from the outside, and which transmits or does not transmit the pulse signal in response to the capacitance applied through the pad;
A pulse signal detector for periodically detecting the pulse signal applied through the pulse signal transmitter and outputting a detection signal;
A counter that sequentially increases or decreases a counting value according to a specified rule in response to the detection signal; And
And a digital filter for filtering the counting value and outputting the capacitance value. The method of claim 1, wherein the pulse signal generation unit
A clock signal generator for generating the clock signal;
A variable delay chain configured to variably delay and output the clock signal according to the capacitance value;
An inverter for inverting and outputting an output signal of the variable delay chain; And
And an AND gate for generating the pulse signal having a pulse width corresponding to a delay time of the clock signal by multiplying the clock signal by an output signal of the inverter. According to claim 1, wherein the pulse signal transmission unit
And a resistance coupled between the pulse signal generator and the pulse signal detector, for suppressing the transmission of the pulse signal together with the capacitance applied through the pad. The method of claim 1, wherein the pulse signal detection unit
A T-flip-flop that senses the pulse signal in response to a clock signal and generates an output signal that is toggled in response to the pulse signal; And
And a period discriminator for determining whether the output signal of the T-flip-flop is periodically toggled and outputting a sensing signal. The method of claim 4, wherein the T-flip flop
An SR flip-flop that outputs the sensing signal in response to the pulse signal applied to any one of a set terminal or a reset terminal;
A D-flip-flop that latches and outputs the sensing signal in response to the clock signal; And
And a mux for transmitting the pulse signal by selecting one of the set terminal and the reset terminal in response to the output signal of the D flip-flop. The method of claim 1, wherein the counter
And a capacitance measurement circuit sequentially increasing or decreasing a capacitance value in a predetermined unit in response to the sensing signal. The method of claim 1, wherein the counter
When the sensing signal is continuously applied at a high level or a low level, the capacitance measurement circuit, characterized in that the variable increases in increments or decreases sequentially in units of change of the capacitance value. The method of claim 1, wherein the digital filter
And a low pass filter or a band pass filter for stabilizing by applying the counting value, removing noise, and outputting the capacitance value. The method of claim 1, wherein the counter and the digital filter
Capacitance measurement circuitry, characterized in that implemented in software.

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