KR20110025337A - Internal voltage generator for semiconductor memory apparatus - Google Patents

Internal voltage generator for semiconductor memory apparatus Download PDF

Info

Publication number
KR20110025337A
KR20110025337A KR1020090083350A KR20090083350A KR20110025337A KR 20110025337 A KR20110025337 A KR 20110025337A KR 1020090083350 A KR1020090083350 A KR 1020090083350A KR 20090083350 A KR20090083350 A KR 20090083350A KR 20110025337 A KR20110025337 A KR 20110025337A
Authority
KR
South Korea
Prior art keywords
internal voltage
voltage
period
enable signal
internal
Prior art date
Application number
KR1020090083350A
Other languages
Korean (ko)
Inventor
최영경
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090083350A priority Critical patent/KR20110025337A/en
Publication of KR20110025337A publication Critical patent/KR20110025337A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

PURPOSE: An internal voltage generator for a semiconductor memory apparatus are provided to make the operating properties of an internal circuit stable by generating an internal voltage having minimum AC noise. CONSTITUTION: In an internal voltage generator for a semiconductor memory, a first driving part(31) generates the internal voltage for an active period. A second driver part(32) additionally generates the internal voltage during a data read period and data writing period. A third driving part(33) generates the internal voltage during at least one initial constant period.

Description

INTERNAL VOLTAGE GENERATOR FOR SEMICONDUCTOR MEMORY APPARATUS}

The present invention relates to a semiconductor design technique, and to a technique for generating an internal voltage.

In general, a semiconductor memory device receives an external power source to generate internal voltages of various voltage levels, and operates an internal circuit using the internal voltages.

1 is a diagram illustrating a change in the internal voltage VINT according to a change in the external power supply voltage VDD.

Referring to FIG. 1, an internal voltage generation circuit of a semiconductor memory device receives an external power supply voltage VDD to generate an internal voltage VINT having a voltage level lower than the power supply voltage VDD, and the internal voltage VINT is a power supply. When the voltage VDD reaches the target level, the voltage VDD maintains a constant voltage level even if the power supply voltage VDD rises further. Therefore, in the internal circuit using the internal voltage VINT as the operating power source, the stability of the operation is improved because the internal voltage VINT maintains a constant voltage level even when the power supply voltage VDD changes.

On the other hand, according to the estimated current consumption of the internal voltage (VINT), the circuit should be designed in consideration of the driving force and the driving speed (response time to drive to the predetermined voltage level) of the internal voltage generating circuit. It is very important to design so as to minimize the noise of the internal voltage (VINT) due to the driving force and driving speed of the internal voltage generator circuit.

2 is a diagram illustrating an internal operation of an internal voltage generation circuit of a semiconductor memory device of the related art.

Referring to FIG. 2, when the current consumption amount of the internal voltage VINT decreases due to an increase in the current consumption of the internal voltage VINT, the internal voltage generation circuit detects it internally and increases the driving force to increase the internal voltage. VINT) is controlled to rise. The driving control signal V_CTRL is a signal for adjusting the driving force of the internal voltage VINT. When the voltage level of the internal voltage VINT decreases, the voltage level of the driving control signal V_CTRL also decreases to increase the driving force. do.

On the other hand, even when the voltage level of the driving control signal V_CTRL decreases, there is a reaction time required to drive the internal voltage VINT internally. In FIG. 2, the first point A is the point at which the internal voltage VINT falls most and starts to increase the driving force under the control of the driving control signal V_CTRL. The second point B is a time point at which the current consumption of the internal voltage VINT hardly occurs. Since the rise of the driving control signal V_CTRL is delayed due to the reaction time, the internal voltage VINT is at a target level during this period. It rises above. As the variation of the internal voltage VINT increases due to the driving force and the driving speed of the internal voltage generating circuit as described above, the operation of the internal circuit using the internal voltage VINT as the operating power becomes unstable, and thus a technique for improving this is required. have.

The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide an internal voltage generation circuit of a semiconductor memory device capable of generating a stable internal voltage.

Another object of the present invention is to provide an internal voltage generation circuit of a semiconductor memory device capable of minimizing unnecessary current consumption when generating an internal voltage.

According to an aspect of the present invention for achieving the above technical problem, the first driver for generating and driving the internal voltage of the predetermined voltage level during the active period; A second driver configured to generate and additionally drive the internal voltage during a data read period and a data write period; And a third driver configured to generate and additionally drive the internal voltage during any one of the active period, the data read period, and the data write period, or a plurality of initial predetermined periods of the semiconductor memory device. do.

Further, according to another aspect of the invention, the first driver for generating and driving the internal voltage of the predetermined voltage level during the active period; And a second driver configured to generate and additionally drive the internal voltage during the data read period and the data write period.

The internal voltage generation circuit of the semiconductor memory device according to the present invention may generate an internal voltage with minimal AC noise. Therefore, the operating characteristics of the internal circuits using the internal voltage as the operating power source are stabilized.

In addition, the internal voltage generation circuit may prevent the internal voltage from falling due to excessive current consumption or the excessive increase of the internal voltage due to the excessive driving force by controlling the driving force of the internal voltage according to the operation mode. Therefore, unnecessary current consumption due to excessive increase in internal voltage can be minimized.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.

In general, logic signals and binary data values of a circuit are classified into high level (high level) or low level (low level) corresponding to voltage level, and may be expressed as '1' and '0', respectively. . In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, PMOS (P-channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS), which are terms used in the present embodiment, are known to be a type of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

3 is a configuration diagram of an internal voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, an internal voltage generation circuit of a semiconductor memory device includes a first driver 31 for generating and driving an internal voltage VINT having a predetermined voltage level during an active period, and an internal voltage during a data read period and a data write period. The second driver 32 for generating and additionally driving the voltage VINT, and generating and driving the internal voltage VINT during any one of the active period, the data read period, the data write period, or a plurality of initial predetermined periods. It is provided with a third drive unit 33 for. Here, the second driving unit 32 has a lower driving force than the first driving unit 31, but a lower driving speed, and the third driving unit 33 has a higher driving force than the second driving unit 32 and drives the first driving unit 31. Speed is fast

The first driver 31 drives the internal voltage VINT when the active signal RAS is activated. The first driver 31 drives the internal voltage VINT with a basic driving force during the active period. Meanwhile, the first driver 31 may be designed to drive the internal voltage VINT for a predetermined time even after the active signal RAS is deactivated in order to secure the stability of the internal voltage VINT. For reference, the active signal RAS is a signal that is activated during the active period and deactivated during the precharge period, and is a signal related to the control of the row path of the semiconductor memory device.

In addition, the second driver 32 additionally drives the internal voltage VINT when any one of the data write signal CASP_WT and the data read signal CASP_RD is activated. When the data write signal CASP_WT or the data read signal CASP_RD is activated and the semiconductor memory device operates in the data write mode or the data read mode, the current consumption of the internal voltage VINT increases, so that the second driver 32 Operate additionally to prevent the internal voltage (VINT) from falling. Meanwhile, the second driver 32 may be designed to drive the internal voltage VINT for a predetermined time even after the data write signal CASP_WT and the data read signal CASP_RD are deactivated to ensure the stability of the internal voltage VINT. Could be For reference, the data write signal CASP_WT is a signal that is activated during the data write period, and the data read signal CASP_RD is a signal that is activated during the data read period, and is a signal related to the column path control of the semiconductor memory device. .

In addition, the third driver 33 additionally drives the internal voltage VINT during an initial predetermined period of activation periods of the active signal RAS, the data write signal CASP_WT, and the data read signal CASP_RD. Since the third driving unit 33 has the fastest driving speed and strong driving force, the third driving unit 33 operates only during the initial period of the active mode, the data writing mode, and the data reading mode, thereby minimizing the current consumption and suppressing the variation of the internal voltage VINT. . For reference, in the present embodiment, the third driving unit 33 is designed to operate during an initial predetermined period of all the operation modes (active mode, data read mode, data write mode). 3 drive 33 may be designed to operate.

The detailed configuration and main operations of the internal voltage generation circuit of the semiconductor memory device configured as described above are as follows.

FIG. 4 is a circuit diagram of the first driver 31 of the internal voltage generator of FIG. 3.

Referring to FIG. 4, the first driver 31 includes a first enable signal generator 41 for generating a first enable signal ACTEN that is activated during an active period, and a first enable signal ACTEN. In response, the first voltage generator 42 generates an internal voltage VINT. Here, the first enable signal generator 41 includes an inverter INV1 for inputting the active signal RAS, a delay unit 41_1 for delaying a signal output from the inverter INV1 for a predetermined time period, And a logic unit NAND, INV2, and INV3 for negatively multiplying the signal output from the inverter INV1 and the signal output from the delay unit 41_1 to output the first enable signal ACTEN. In addition, the first voltage generator 42 may output a driving control voltage V_CTRL corresponding to a result of comparing the reference voltage VREF and the feedback voltage VFEED in response to the first enable signal ACTEN. A comparator 42_1, a voltage output unit MP11, MP12, and MP13 for generating an internal voltage VINT corresponding to the voltage level of the driving control voltage V_CTRL and outputting it to the internal voltage terminal N1; And a feedback unit MP11, MP12, and MP13 for providing the feedback unit VFEED corresponding to the voltage level of the voltage terminal N1 to the comparison unit 42_1.

The first enable signal generator 41 further extends the activation period of the active signal RAS by the delay value of the delay unit 41_1 to generate the first enable signal ACTEN. The comparator 42_1 is configured in the form of a differential amplification circuit and performs a comparison operation when the first enable signal ACTEN is activated. The reference voltage VREF and the feedback voltage VFEED are applied to the differential input terminals MN1 and MN2, and the driving voltages V_CTRL are output by comparing the levels of the two voltages. When the feedback voltage VFEED is higher than the reference voltage VREF, the driving control voltage V_CTRL is increased. When the feedback voltage VFEED is lower than the reference voltage VREF, the driving control voltage V_CTRL is lowered. The PMOS transistors MP11 of the voltage output units MP11, MP12, and MP13 drive the internal voltage VINT to the internal voltage terminal N1 through the control of the driving control voltage V_CTRL. That is, the driving force of the internal voltage VINT is adjusted according to the voltage level of the driving control voltage V_CTRL. The feedback units MP11, MP12, and MP13 provide a feedback voltage VFEED to the differential input terminal MN2 of the comparator 42_1, and the feedback voltage VFEED changes in response to the voltage level of the internal voltage terminal N1. do. Therefore, when the voltage level of the internal voltage terminal N1 falls, the feedback voltage VFEED also decreases. Therefore, the voltage level of the driving control voltage V_CTRL is lowered, thereby enhancing the driving force of the PMOS transistor MP11, thereby increasing the internal voltage VINT. Rises. For reference, in the present exemplary embodiment, detailed circuits of the voltage output units MP11, MP12, and MP13 and the feedback units MP11, MP12, and MP13 are not accurately distinguished, but are configured by sharing a plurality of elements.

FIG. 5 is a circuit diagram of the second driver 32 of the internal voltage generation circuit of FIG. 3.

Referring to FIG. 5, the second driver 32 may include a second enable signal generator 51 for generating a second enable signal RDWTEN that is activated during a data read period and a data write period. The second voltage generator 52 is configured to generate the internal voltage VINT in response to the enable signal RDTW. Here, the second enable signal generator 51 is configured to delay the first inverter INV1 receiving the data write signal CASP_WT and the signal output from the first inverter INV1 for a predetermined time. First delay unit 51_1, first logic unit NAND1, INV2, and INV3 for negative ANDing the signal output from first inverter INV1 and the signal output from first delay unit 51_1, and reading data The second inverter INV4 having the signal CASP_RD as an input, the second delay unit 51_2 for delaying the signal output from the second inverter INV4 for a predetermined time, and the output from the second inverter INV4. The second logic unit NAND2, INV5, INV6, and the first logic unit NAND1, INV2, INV3, and the second logic unit NAND2 for negative ANDing the signal and the signal output from the second delay unit 51_2. To the third logic unit NOR and INV7 for outputting the second enable signal RDWTEN by ORing the signals WTEN and RDEN output from the INV5 and INV6. It is composed. In addition, the second voltage generator 52 may output a driving control voltage V_CTRL corresponding to a result of comparing the reference voltage VREF and the feedback voltage VFEED in response to the second enable signal RDWTEN. A comparator 52_1, a voltage output unit MP11, MP12, and MP13 for generating an internal voltage VINT corresponding to the voltage level of the driving control voltage V_CTRL and outputting it to the internal voltage terminal N1; And a feedback unit MP11, MP12, and MP13 for providing the feedback unit VFEED corresponding to the voltage level of the voltage terminal N1 to the comparison unit 52_1.

The second enable signal generator 51 further extends the activation period of the data write signal CASP_WT by the delay value of the first delay unit 51_1 or delays the activation period of the data read signal CASP_RD by the second delay. The second enable signal RDWTEN is generated by further extending the delay value of the unit 51_2. The comparator 52_1 is configured in the form of a differential amplifier and performs a comparison operation when the second enable signal RDWTEN is activated. The reference voltage VREF and the feedback voltage VFEED are applied to the differential input terminals MN1 and MN2, and the driving voltages V_CTRL are output by comparing the levels of the two voltages. When the feedback voltage VFEED is higher than the reference voltage VREF, the driving control voltage V_CTRL is increased. When the feedback voltage VFEED is lower than the reference voltage VREF, the driving control voltage V_CTRL is lowered. The PMOS transistors MP11 of the voltage output units MP11, MP12, and MP13 drive the internal voltage VINT to the internal voltage terminal N1 through the control of the driving control voltage V_CTRL. That is, the driving force of the internal voltage VINT is adjusted according to the voltage level of the driving control voltage V_CTRL. The feedback units MP11, MP12, and MP13 provide a feedback voltage VFEED to the differential input terminal MN2 of the comparator 52_1. The feedback voltage VFEED changes in response to the voltage level of the internal voltage terminal N1. do. Therefore, when the voltage level of the internal voltage terminal N1 falls, the feedback voltage VFEED also decreases. Therefore, the voltage level of the driving control voltage V_CTRL is lowered, thereby enhancing the driving force of the PMOS transistor MP11, thereby increasing the internal voltage VINT. Rises. For reference, in the present exemplary embodiment, detailed circuits of the voltage output units MP11, MP12, and MP13 and the feedback units MP11, MP12, and MP13 are not accurately distinguished, but are configured by sharing a plurality of elements.

FIG. 6 is a circuit diagram of the third driver 33 of the internal voltage generation circuit of FIG. 3.

Referring to FIG. 6, the third driver 33 generates a third enable signal generator for generating a third enable signal CMOSENP that is activated during each initial period of an active period, a data read period, and a data write period. 61 and a third voltage generator 62 for generating the internal voltage VINT in response to the third enable signal CMOSENP. Here, the third enable signal generator 61 is activated at the activation time of the data read signal CASP_RD and the activation time of the data write signal CASP_WT, and pulses the pulse signal RDWTEN and the active signal RAS for a predetermined time. ), The first logic unit NOR for negating the logical sum, the first inverter INV1 for inputting the signal output from the first logic unit NOR, and the signal output from the first logic unit NOR. A second unit for outputting the third enable signal CMOSENP by ORing the delay unit 61_1 for delaying the predetermined time and the signal output from the first inverter INV1 and the signal output from the delay unit 61_1 It consists of logic sections (NAND, INV2). In addition, the third voltage generator 62 may adjust the driving control signal CTRL-logic level corresponding to a result of comparing the reference voltage VREF and the feedback voltage VFEED in response to the third enable signal CMOSENP. Comparator 62_1 for outputting a signal and a voltage output part MP11, MP12, for generating an internal voltage VINT in response to the drive control signal CTRL and outputting the internal voltage VN. MP13 and feedback sections MP11, MP12, and MP13 for providing the feedback voltage VFEED corresponding to the voltage level of the internal voltage terminal N1 to the comparison section 62_1.

The third enable signal generation unit 61 has a third enable signal CMOSENP having an activation period corresponding to a delay value of the delay unit 61_1 from an activation time of the active signal RAS and an activation time of the pulse signal RDWTEN. Will be generated. The comparator 62_1 is configured in the form of a differential amplifier and performs a comparison operation when the third enable signal CMOSENP is activated. The reference voltage VREF and the feedback voltage VFEED are applied to the differential input terminals MN1 and MN2, and the driving control signal CTRL corresponding to the result is output by comparing the levels of the two voltages. When the feedback voltage VFEED is higher than the reference voltage VREF, the driving control signal CTRL becomes high level. When the feedback voltage VFEED is lower than the reference voltage VREF, the driving control signal CTRL becomes low level. do. The PMOS transistors MP11 of the voltage output units MP11, MP12, and MP13 drive the internal voltage VINT to the internal voltage terminal N1 through the control of the drive control signal CTRL. The feedback units MP11, MP12, and MP13 provide a feedback voltage VFEED to the differential input terminal MN2 of the comparator 62_1. The feedback voltage VFEED changes in response to the voltage level of the internal voltage terminal N1. do. Therefore, when the voltage level of the internal voltage terminal N1 falls, the feedback voltage VFEED also falls, so the driving control signal CTRL becomes low level and the PMOS transistor MP11 is turned on to turn on the internal voltage. VINT) rises. For reference, in the present exemplary embodiment, detailed circuits of the voltage output units MP11, MP12, and MP13 and the feedback units MP11, MP12, and MP13 are not accurately distinguished, but are configured by sharing a plurality of elements.

For reference, in the present embodiment, the internal voltage generation circuit of the semiconductor memory device including the first driver 31, the second driver 32, and the third driver 33 has been described. However, the driving force is strong and the driving speed is high. Since the fast third driver 33 consumes a lot of current, the first third driver 33 may include only the first driver 31 and the second driver 32 to generate the internal voltage VINT according to the semiconductor memory device.

7 is a timing diagram showing the internal operation of the internal voltage generation circuit according to an embodiment of the present invention.

Referring to the timing diagram of FIG. 7 and FIGS. 3 to 6, the internal operation of the internal voltage generation circuit of the semiconductor memory device according to the embodiment will be described as follows.

In the semiconductor memory device, the active signal RAS is activated at the high level in the active mode, the data write signal CASP_WT is activated at the high level in the data write mode, and the data read signal CASP_RD is set at the high level in the data read mode. Is activated.

First, since the first enable signal ACTEN of the first driver 31 is activated at the high level during the period in which the active signal RAS is activated at the high level, the first voltage generator of the first driver 31 ( 42) drives the internal voltage VINT to the internal voltage terminal N1. Here, the first enable signal ACTEN is activated for a predetermined time even after the active signal RAS is deactivated to a low level in order to secure stability of the internal voltage VINT.

Next, during the period in which the data write signal CASP_WT is activated at the high level or the data read signal CASP_RD is activated at the high level, the second enable signal RDTWTEN of the second driver 32 is activated at the high level. The second voltage generator 52 of the second driver 32 additionally drives the internal voltage VINT to the internal voltage terminal N1. Here, the second enable signal RDWTEN is activated for a certain time even after the data write signal CASP_WT is inactivated to a low level to ensure the stability of the internal voltage VINT, and the data read signal CASP_RD is low. Even after being deactivated, it is activated for a certain time.

Next, from a time when the active signal RAS is activated to a high level, from a time when the data write signal CASP_WT is activated to a high level, from a time when the data read signal CASP_RD is activated to a high level. Since the third enable signal CMOSENP of the third driver 33 is activated at a high level for a certain period, the third voltage generator 62 of the third driver 33 is connected to the internal voltage terminal N1 to the internal voltage. It will drive (VINT) additionally.

In summary, since the current consumption amount of the internal voltage VINT is different for each operation mode (active mode, data read mode, data write mode), the first driver 31 and the second driver ( 32, the variation of the internal voltage VINT may be minimized by adjusting the driving period of the internal voltage VINT of the third driver 33.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, although not directly related to the technical spirit of the present invention, in order to explain the present invention in more detail, an embodiment including an additional configuration may be illustrated. In addition, the configuration of an active high or an active low for indicating an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a view showing a change in the internal voltage according to the change in the external power supply voltage.

2 is a diagram illustrating an internal operation of an internal voltage generation circuit of a semiconductor memory device of the related art.

3 is a configuration diagram of an internal voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of the first driver of the internal voltage generator of FIG. 3.

FIG. 5 is a circuit diagram of a second driver of the internal voltage generator of FIG. 3.

FIG. 6 is a circuit diagram of a third driver of the internal voltage generator of FIG. 3.

7 is a timing diagram showing the internal operation of the internal voltage generation circuit according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

41: first enable signal generator 42: first voltage generator

51: second enable signal generator 52: second voltage generator

61: third enable signal generator 62: third voltage generator

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (9)

A first driver for generating and driving an internal voltage having a predetermined voltage level during an active period; And A second driver for additionally generating the internal voltage during a data read period and a data write period An internal voltage generation circuit of a semiconductor memory device having a. The method of claim 1, And a third driver configured to generate and additionally drive the internal voltage during an initial predetermined period of at least one of the active period, the data read period, and the data write period. . The method according to claim 1 or 2, The first driving unit, The internal voltage generation circuit of the semiconductor memory device, wherein the internal voltage is driven for a predetermined time even after the deactivation time of the active period. The method according to claim 1 or 2, The second drive unit, And the internal voltage is driven for a predetermined time even after the data read period and the data write period are inactivated. The method of claim 1, And the second driving unit has a lower driving force than the first driving unit but a lower driving speed. The method of claim 2, The second driving unit has a lower driving force than the first driving unit but a lower driving speed, and the third driving unit has a higher driving force than the second driving unit and a higher driving speed than the first driving unit. Voltage generating circuit. The method according to claim 1 or 2, The first driving unit, An enable signal generator for generating an enable signal activated during the active period; And And a voltage generator configured to generate the internal voltage in response to the enable signal. The method according to claim 1 or 2, The second drive unit, An enable signal generator for generating an enable signal activated during the data read period and the data write period; And And a voltage generator configured to generate the internal voltage in response to the enable signal. The method of claim 2, The third drive unit, An enable signal generator configured to generate an enable signal activated during each initial period of the active section, the data read section, and the data write section; And And a voltage generator configured to generate the internal voltage in response to the enable signal.
KR1020090083350A 2009-09-04 2009-09-04 Internal voltage generator for semiconductor memory apparatus KR20110025337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090083350A KR20110025337A (en) 2009-09-04 2009-09-04 Internal voltage generator for semiconductor memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090083350A KR20110025337A (en) 2009-09-04 2009-09-04 Internal voltage generator for semiconductor memory apparatus

Publications (1)

Publication Number Publication Date
KR20110025337A true KR20110025337A (en) 2011-03-10

Family

ID=43932903

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090083350A KR20110025337A (en) 2009-09-04 2009-09-04 Internal voltage generator for semiconductor memory apparatus

Country Status (1)

Country Link
KR (1) KR20110025337A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210018053A (en) 2019-08-06 2021-02-17 히다치 조센 가부시키가이샤 Belt conveying type polishing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210018053A (en) 2019-08-06 2021-02-17 히다치 조센 가부시키가이샤 Belt conveying type polishing device

Similar Documents

Publication Publication Date Title
US7528624B2 (en) Output buffer and method having a supply voltage insensitive slew rate
CN111292780B (en) Memory circuit
KR100795014B1 (en) Internal voltage generator of semiconductor memory device
US8283971B2 (en) Internal voltage generation circuit and semiconductor apparatus using the same
US20050024911A1 (en) Semiconductor memory device capable of reducing current consumption in active mode
KR20040092772A (en) Semiconductor memory device and method for generation of core voltage of the same
KR100954110B1 (en) Power up signal generator and integrated circuit using the same
JP2009181638A (en) Semiconductor storage device
KR100954112B1 (en) Semiconductor memory device
US8362827B2 (en) Semiconductor device including transistors that exercise control to reduce standby current
US9479146B1 (en) Data output device
KR20110025337A (en) Internal voltage generator for semiconductor memory apparatus
JP5580179B2 (en) Semiconductor device
KR100816729B1 (en) Vcore generator and semiconductor memory device include the same
KR20160115484A (en) Power driving device and semiconductor device including the same
KR100761371B1 (en) Active driver
KR20090027106A (en) Circuit of internal voltage generation
KR100849957B1 (en) Semiconductor memory device and i/o drive circuits thereof and currunt supply method for them
KR101559500B1 (en) Circuit for driving bitline sense amplifier of semiconductor memory device and method of operating driver for bitline sense amplifier
KR100889324B1 (en) VCORE release driver
KR20030002251A (en) Circuit for providing a voltage to a sense amplifier of semiconductor memory device
KR100799103B1 (en) Semiconductor device
KR100762240B1 (en) Power control circuit
KR100431525B1 (en) Input Buffer Circuit in Semiconductor Memory Device
KR20070036628A (en) Over-driving scheme of semiconductor memory device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination