KR20110024035A - Manufacturing method one time programmable memory device and memory cell structure thereof - Google Patents

Abstract

PURPOSE: A method for manufacturing a one time programmable memory and a memory cell structure are provided to stably maintain the performance of an OTP ROM device by decreasing influences on a manufacturing process. CONSTITUTION: Gate electrodes of a select transistor(40) and a memory transistor are formed by patterning a poly silicon layer. An LDD ion is implanted to an active area between the gate electrodes of the memory transistor and the select transistor. A spacer(60) is formed on the sides of the gate electrodes of the memory transistor and the select transistor. A source/drain ion implantation process is performed after a photosensitive pattern which masks the active area is formed. A silicide(70) is formed after the silicide preventing layer is etched by forming the photosensitive pattern.

Description

Manufacturing method one time programmable memory device and memory cell structure

The present invention relates to a one time programmable memory manufacturing method and a memory cell structure, and more particularly, to a one time programmable memory manufacturing method and a memory cell structure capable of stably maintaining a resistance of an active region connecting a memory transistor and a select transistor. It is about.

In general, non-volatile memory has the advantage that the stored data is not lost even if the power is interrupted. For PC BIOS, set top box, printer and network server, etc. It is widely used for data storage, and recently, it is also widely used in digital cameras and mobile phones.

Such nonvolatile memories are classified into one-time programmable (OTP) and multi-time programmable (MTP) according to the number of possible programming operations.

The OTP ROM device refers to a device that can be programmed only once in a circuit, and includes a fuse, an anti-fuse, a charge storage (EPROM), and a mask ROM. Can be classified into four basic types.

In the case of the charge storage method or erasable program ROM (EPROM), bit programming requires a high write voltage and a floating gate of a memory cell from a substrate by Fowler-Nordheim electron tunneling. To record data by transferring charge to a floating gate.

Since the mask ROM is a memory that is programmed at the time of manufacture, the mask ROM is relatively simple and inexpensive compared to other OTP memories since no circuit is required to enable writing.

However, this mask ROM has the disadvantage that since programming is part of the manufacturing process, the mask ROM cannot be “field programmed”, ie programmed by the buyer to meet the buyer's specific needs.

The fuse method is to cut metal or poly resistors. That is, in the normal state, the fuse in the one-time-programmable cell is shorted to have a minimum resistance value, and after being cut, it is opened to have an infinite resistance value.

The fuse method has a disadvantage in that it requires a laser device for cutting a metal or a poly resistor, which is costly and time consuming.

The anti-fuse method is implemented by a gate oxide capacitor having a gate and a substrate of a CMOS transistor as electrodes. In the normal state, the capacitor has infinite resistance, and the antifuse is open.When a high voltage (V _PP ) is applied to the gate or the substrate, the gate and the substrate are shorted and the antifuse has a resistance value of several tens of Ω. Has At this time, a resistance value of several to several tens of Ω is a resistance value when the gate insulating layer is broken down.

The anti-fuse method, which consists of CMOS gate insulation layers, applies a voltage for cutting through a circuit design. Unlike the fuse method, the anti-fuse method does not require investment cost for laser equipment and is not affected by time and temperature. There is an advantage to having.

The OTP ROM is used without performing an additional program operation or erase operation after performing only one program operation. As such, since the OTP ROM cannot change the stored information, it is not used as a product by itself, but merely as a means of performing an auxiliary function in a semiconductor product.

Of course, in the case of EPROM, erasing is possible when irradiated with ultraviolet rays. However, in this case, a physical auxiliary device is required for the erasing operation.

1 is a circuit diagram of a unit cell of an OTP ROM device according to the prior art, FIG. 2A is a layout diagram of an OTP ROM corresponding to the dotted line of FIG. 1, and FIG. 2B is cut along the line a-a 'of FIG. 2A. A cross-sectional view on a wafer.

Among the OTP ROM devices according to the related art, in the case of an OTP ROM device storing data by an oxide breakdown method for a gate of a memory transistor, a transistor for selecting a corresponding cell (hereinafter, referred to as a 'select transistor') And the memory transistor are connected through an active region.

However, various unstable factors in the process point of view such as salicide formation and excessive source / drain formation exist in the active region, and thus the characteristics of the unstable memory device related to resistance cannot be avoided.

Referring to FIG. 2A, the active region A is connected between the memory transistor 300 and the select transistor 400. In this area, low concentrations of lightly doped drain (LDD) ions are implanted as well as high concentration source / drain ions. It is also an area where silicide is formed through the salicide process.

Recently, when the distance between the memory transistor and the gate of the select transistor is reduced to minimize the size of the OTP ROM device, an abnormal profile formed by the source / drain ion implantation process and the salicide process as shown in FIG. profile) causes the resistance of the active region A to become unstable, thereby degrading the performance of the OTP ROM device.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the one-time programmable memory that can maintain the performance of a more stable OTP ROM device by reducing the factors that can affect the process viewpoint by changing the design of the OTP memory cell Its purpose is to provide a fabrication method and a memory cell structure.

One-time programmable memory manufacturing method of the present invention for realizing the above object is a first step of defining an active region by forming an isolation layer between the semiconductor substrate in order to manufacture an anti-fuse OTP ROM device; Forming a gate electrode of a memory transistor and a select transistor by sequentially forming a gate insulating film and a polysilicon film and then patterning the polysilicon film by a photolithography process; Performing an LDD ion implantation process into an active region between the gate electrode of the memory transistor and the gate electrode of the select transistor; Depositing a spacer layer and performing blanket etching to form spacers on side surfaces of gate electrodes of the memory transistor and the select transistor; A fifth step of forming a photoresist pattern for masking an active region between the gate electrode of the memory transistor and the gate electrode of the select transistor, and then performing source / drain ion implantation; And depositing a silicide barrier layer to form a photoresist pattern for masking an active region between the gate electrode of the memory transistor and the gate electrode of the select transistor to etch the silicide barrier layer to form silicide. Characterized in that made.

In addition, the first step is characterized in that to form an isolation device between the elements by the shallow trench isolation method.

In the fourth step, a double film in which a silicon oxide film and a silicon nitride film are sequentially deposited is used as a spacer film.

In addition, the fifth step is characterized by forming titanium silicide using titanium metal.

The one-time programmable memory cell structure of the present invention is a semiconductor device having an anti-fuse type OTP ROM element, comprising: LDD ions in an active region between a gate electrode of a memory transistor in which programmed data is stored and a gate electrode of a select transistor. An injection region is formed.

According to the one-time programmable memory manufacturing method and the memory cell structure according to the present invention, it is possible to maintain the performance of a more stable OTP ROM device by changing the design of the OTP memory cell and reducing the factors that can affect the process point of view. .

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the preferred embodiment of the present invention will be described in detail so that those skilled in the art can easily practice.

However, the configuration and operation of the present invention shown in the drawings and described by it are described as at least one embodiment, and the present invention is not intended to be limited to the specific embodiments by the present invention. It is to be understood that all changes, equivalents, and substitutes included in the technical scope are included.

3A to 3F are cross-sectional views on a wafer for each process for explaining a method of manufacturing a one-time programmable memory according to an embodiment of the present invention, and FIG. 4 is a layout diagram of an OTP ROM according to an embodiment of the present invention.

One time programmable memory manufacturing method according to an embodiment of the present invention comprises a first step to a sixth step.

Referring to FIG. 3A, the first step is to define an active region by forming an isolation device 20 on the semiconductor substrate 10 to manufacture an anti-fuse OTP ROM device. The interlayer isolation layer 20 may be formed by a LOCOS (LOCal Oxidatin of Silicon) process, but is preferably formed by a shallow trench isolation method.

Referring to FIG. 3B, the second step is to sequentially form a gate insulating film and a polysilicon film, and then pattern the polysilicon film by a photolithography process to form a gate of the memory transistor 30 and the select transistor 40. Forming an electrode. The gate insulating film may be formed of any one of a silicon oxide film (SiO ₂ ), a TaO film, or a TiO film.

Referring to FIG. 3C, the third step is to perform an LDD ion implantation process in the active region A between the gate electrode of the memory transistor 30 and the gate electrode of the select transistor 40. In this case, it is natural that the LDD ion implantation process is performed not only in the active region A but also in the active region of another logic region or a peripheral circuit region.

Referring to FIG. 3D, the fourth step is to form a spacer 60 on side surfaces of the gate electrodes of the memory transistor 30 and the select transistor 40 by depositing a spacer layer and then performing blanket etching. . It is also possible to use a single silicon oxide film as the spacer film here, but it is preferable to use a double film in which a silicon oxide film and a silicon nitride film are sequentially deposited.

Referring to FIG. 3E, the fifth step includes forming a photoresist layer 50 pattern for masking the active region A between the gate electrode of the memory transistor 30 and the gate electrode of the select transistor 40. This step is followed by source / drain ion implantation.

That is, the source / drain ion implantation mask is manufactured by changing the mask generation rule when fabricating the source / drain ion implantation mask using the dummy layer 200 as shown in FIG. 4. The photo process and the ion implantation process are performed to prevent the source / drain ion implantation region from being formed in the active region A between the gate electrode of the memory transistor 30 and the gate electrode of the select transistor 40. .

Referring to FIG. 3F, in the sixth step, the photoresist layer pattern masking the active region A between the gate electrode of the memory transistor 30 and the gate electrode of the select transistor 40 after depositing a silicide prevention layer. The silicide 70 is formed by etching the silicide barrier layer (not shown) to form a silicide 70, thereby completing the method of manufacturing a one-time programmable memory according to an embodiment of the present invention. Here, the silicide formation is preferably to form titanium silicide using titanium metal.

Likewise, when the mask is formed to define the non-salicide region using the dummy layer 200 as shown in FIG. 4, the Masg generation rule is changed to change the gate electrode of the memory transistor 30. The silicide is prevented from being formed in the active region A between the gate electrodes of the select transistor 40.

A one-time programmable memory cell structure according to an embodiment of the present invention is a semiconductor device having an anti-fuse type OTP ROM device, comprising: between a gate electrode of a memory transistor in which programmed data is stored and a gate electrode of a select transistor. Only the LDD ion implantation region is formed in the active region.

That is, the dummy electrode 200 as shown in FIG. 4 is added to the gate electrode of the memory transistor 300 when the source / drain ion implantation mask and the non-salicide mask are manufactured using the dummy layer 200. And source / drain ion implantation and silicide formation in the active region A between the gate electrode and the gate electrode of the select transistor 400.

Therefore, as shown in FIG. 3F, the active region A between the gate electrode of the memory transistor 30 and the gate electrode of the select transistor 40 has only an LDD ion implantation process, It exists as a major process factor that affects sheet resistance (Rs; Rs) to maintain more stable OTP ROM device performance.

Moreover, this method has the advantage that there is no burden of additional cost because the process element can be reduced through a simple design change and a mask generation rule change without additional FAB process change.

It is apparent to those skilled in the art that the present invention is not limited to the above-described embodiments and can be practiced in various ways without departing from the spirit and scope of the present invention. It is.

1 is a circuit diagram of a unit cell of an OTP ROM device according to the prior art;

FIG. 2A is a layout diagram of an OTP ROM corresponding to the dotted line of FIG. 1;

FIG. 2B is a cross-sectional view of the wafer taken along the line a-a 'of FIG. 2A;

3A to 3F are cross-sectional views on a wafer for each process for explaining a method of manufacturing a one-time programmable memory according to an embodiment of the present invention;

4 is a layout diagram of an OTP ROM in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10 semiconductor substrate 20 separator between devices

30, 300: memory transistor 40, 400: select transistor

50: photosensitive film 60: spacer

70: silicide 200: dummy layer

100: active layer 500: contact layer

Claims (5)

A first step of defining an active region by forming an interlayer separator on a semiconductor substrate to manufacture an anti-fuse OTP ROM device; Forming a gate electrode of a memory transistor and a select transistor by sequentially forming a gate insulating film and a polysilicon film and then patterning the polysilicon film by a photolithography process; Performing an LDD ion implantation process into an active region between the gate electrode of the memory transistor and the gate electrode of the select transistor; Depositing a spacer layer and performing blanket etching to form spacers on side surfaces of gate electrodes of the memory transistor and the select transistor; A fifth step of forming a photoresist pattern for masking an active region between the gate electrode of the memory transistor and the gate electrode of the select transistor, and then performing source / drain ion implantation; And depositing a silicide barrier layer to form a photoresist pattern for masking an active region between the gate electrode of the memory transistor and the gate electrode of the select transistor to etch the silicide barrier layer to form silicide. One time programmable memory manufacturing method, characterized in that made. The method of claim 1, wherein the first step is to form an isolation device between cells by a shallow trench isolation method. The method of claim 1, wherein the fourth step comprises using a double film in which a silicon oxide film and a silicon nitride film are sequentially deposited as a spacer film. The method of claim 1, wherein the sixth step is to form titanium silicide using titanium metal. A semiconductor device having an anti-fuse type OTP ROM element, wherein the LDD ion implantation region is formed in an active region between a gate electrode of a memory transistor and a gate electrode of a select transistor in which programmed data is stored. Programmable Memory Memory Cell Structure.

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