KR20110020973A - Non-volatile static random access memory cell comprising memristor element - Google Patents

Non-volatile static random access memory cell comprising memristor element Download PDF

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Publication number
KR20110020973A
KR20110020973A KR1020090078478A KR20090078478A KR20110020973A KR 20110020973 A KR20110020973 A KR 20110020973A KR 1020090078478 A KR1020090078478 A KR 1020090078478A KR 20090078478 A KR20090078478 A KR 20090078478A KR 20110020973 A KR20110020973 A KR 20110020973A
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KR
South Korea
Prior art keywords
memory cell
sram memory
memristor
power supply
supply voltage
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KR1020090078478A
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Korean (ko)
Inventor
유영갑
전수철
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충북대학교 산학협력단
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Priority to KR1020090078478A priority Critical patent/KR20110020973A/en
Publication of KR20110020973A publication Critical patent/KR20110020973A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Disclosed is a static random access memory cell having a non-volatile characteristic for restoring data stored in an SRAM memory cell even when a power supply is cut off using a memristor element. According to the present invention, a latch of an SRAM memory cell is cut when a power supply voltage Vdd supplied to an SRAM memory cell is cut off by adding a pair of memristor elements between the power supply voltage Vdd and a load element. Reads data stored in the memristor element and restores the value stored in the latch of the SRAM memory cell due to the resistance difference inside the pair of the memristor element when the supply of the power supply voltage Vdd is resumed. Characterized in that.

Description

Non-volatile static random access memory cell comprising memristor element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to static random access memory cells (hereinafter, referred to as SRAM memory cells) in semiconductor memories. The present invention relates to data stored in SRAM memory cells even when power supply is cut off using a memristor element. The present invention relates to a static random access memory cell having a non-volatile characteristic for making it possible to recover them again.

In general, an SRAM memory cell, which is a static random access memory, has been widely used in information equipment in that a memory cell is composed of a flip flop and an access transistor, so that the operation time is fast and the access time is short.

1 is a circuit diagram showing the structure of a conventional SRAM memory cell. The SRAM memory cell is connected to a resistor (3), n MOS transistor (1) and resistor (4) and n MOS transistor (2) in a pair to form an inverter, each pair is connected to the supply voltage Vcc and ground voltage (GND) Are connected in series. The flip flop is constituted by a pair of resistors 3 and 4 and a pair of n MOS transistors 1 and 2.

The gates of each of the n MOS transistors 1 and 2 are crossed and coupled to each other's drain and the source is grounded. The drain of the n MOS transistor 1 is connected to the bit line BL through the n MOS transistor 5 which is an access transistor, and the drain of the n MOS transistor 2 is connected to the bit line through the access transistor n MOS transistor 6. It is connected to BLb.

A word line WL is connected to a gate of each of the pair of n MOS transistors 5 and 6 which are access transistors.

The SRAM memory cell configured as described above is generally composed of a flip-flop circuit composed of two access transistors, two drive transistors, and two load resistors. The voltage difference between the input and output terminals, i.e., the charge accumulated in the cell node, is stored. The charge of the cell node is always supplemented from the constant power supply Vdd through a load resistor or a PMOS transistor which is a load element.

When the SRAM memory cell is powered, the voltage difference between the input and output terminals of the flip-flop, i.e., the charge accumulated in the cell node is preserved to store the data, and when the power supply is cut off, the cell node It is a volatile device that loses the electric charge stored in) and erases all stored data.

However, in the conventional SRAM memory cell, stored data is not erased as long as power is supplied. However, when the power supply is cut off, data stored in the cell is erased and it is difficult to restore data again. Since a SRAM memory cell having a volatile characteristic has difficulty in restoring data when power supply is cut off, a memristor is applied to a conventional SRAM memory cell to manufacture a nonvolatile SRAM memory cell.

Memristors, which are recognized as one of the basic components of electric circuits, along with resistors, capacitors, and inductors, have the characteristic of storing the amount of charge and changing the resistance according to the stored amount of charge. If the characteristics of the memristor are used as computer system memory, it is expected that the energy consumption and boot time required to turn off and on the computer will be greatly reduced. In other words, memristors are new concept devices that enable the construction of new logic circuits, such as terabit memories and fault recognition devices by neural network configuration, by using the ability to store and store a series of events even when the current is turned off. The memristor device has attracted worldwide attention in May 2008 when Hewlett-Packard researchers created and announced an RRAM-type memristor thin film device.

In order to solve the volatile problem of the SRAM memory cell memory, the nonvolatile static random access memory cell employing the memristor device according to the present invention has information written in the SRAM memory cell even when the power is cut off by applying the memristor device. The purpose is to fabricate a nonvolatile ERAM memory cell.

The present invention for performing the above object

In an SRAM memory cell, a pair of memristor elements are added between the power supply voltage Vdd and the load element to block the power supply voltage Vdd supplied to the SRAM memory cell. Reads and stores the data in the memristor element, and restores the value stored in the latch of the SRAM memory cell by the resistance difference in the pair of the memristor element when the supply of the power supply voltage Vdd is resumed. It is done.

In the SRAM memory cell of the present invention, by adding a memristor element between a power supply voltage and a load element, data stored in the latch circuit is stored in the memristor element when the power is turned off. There is an effect that the non-volatile operation can be performed by restoring the data stored in the latch circuit.

The present invention uses a memristor element in a volatile SRAM memory cell to manufacture a nonvolatile SRAM memory cell in which stored data is stored even when power supply is cut off.

As shown in FIG. 2, a nonvolatile SRAM memory cell employing the memristor device according to the present invention has a memristor device 50, 60 placed in front of a pull-up resistor 30, 40 of the SRAM memory cell. ) In series.

Therefore, the memristor element 70, the pull-up resistor 30, and the n MOS transistor 10 are connected in series in a group, and another pair of the memristor element 80, the pull-up resistor 40, and the n MOS transistor ( 20) is connected in series. Each pair is connected between the supply voltage Vcc and the ground voltage GND, and a flip flop is constituted by a pair of pull-up resistors 30 and 40 and a pair of n MOS transistors 10 and 20.

The gates of each of the n MOS transistors 10, 20 are crossed and coupled to each other's drain and the source is grounded. The drain of the n MOS transistor 10 is connected to the bit line BL through the n MOS transistor 50 which is an access transistor, and the drain of the n MOS transistor 20 is connected to the bit line through the access transistor n MOS transistor 60. The word line WL is connected to the gate of each of the pair of n MOS transistors 50 and 60 which are connected to BLb and which are access transistors.

As shown in FIG. 2, an SRAM memory cell according to the present invention has two memristor elements 70 and 80 and two pull-down transistors that store data in a latch of the SRAM memory cell when the power is turned off. (pull-down transistor) elements 10 and 20 and two pass transistor elements 50 and 60.

3 is a circuit diagram illustrating an example of an operation in which data is stored when the power supply voltage Vdd is turned off. When the power supplied to the SRAM memory cell latch according to the present invention is converted from Vdd to 0, data written to the latch of the SRAM memory cell is read and stored in a memristor element. Memristors have the characteristic of remembering the amount of charge and changing the resistance according to the stored amount of charge.

As shown in FIG. 3, when there is data in the SRAM memory cell when the power supply voltage Vdd is turned off (when Vdd => 0), charge is induced in the meister circuit 70 through the resistor 30. The resistance value of the Lister element 70 is changed (100KΩ => 50Ω), and when there is no data, there is no charge induced in the thyristor element 70 through the resistor 40 so that the resistance value of the thyristor element 70 is reduced. Does not change.

In this state, as shown in FIG. 4, when the power supply voltage Vdd is turned on (when 0 => Vdd), the power supply voltage Vdd is changed due to the resistance difference inside the paired memristor elements 70 and 80. Through the device 50 and the resistor 30 is applied to the gate terminal of the n MOS transistor 20. Therefore, the value stored in the latch of the SRAM memory cell is restored by itself.

5 is a circuit diagram showing an operation when the power supply voltage Vdd is continuously supplied. When the power supply voltage Vdd is continuously supplied, the memristor element 70 is re-initialized by changing the resistance value, and the SRAM memory cell according to the present invention performs an operation that is the same as that of a conventional SRAM memory cell. The present invention is also applicable to a full CMOS SRAM memory cell in which a PMOS transistor is used in place of a pull-up resistor and the operation is as described above.

In the SRAM memory cell of the present invention, by adding a memristor element between a power supply voltage and a load element, data stored in the latch circuit is stored in the memristor element when the power is turned off. There is an effect that the non-volatile operation can be performed by restoring the data stored in the latch circuit.

Although the preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

1 is a circuit diagram of a conventional SRAM memory cell.

2 is a circuit diagram of an SRAM memory cell to which a memristor is applied according to the present invention.

3 is a circuit diagram illustrating a data storage operation in an SRAM memory cell according to the present invention.

4 is a circuit diagram illustrating a restoration operation of data stored in an SRAM memory cell according to the present invention.

FIG. 5 is a circuit diagram illustrating an initialization of a memristor device and a basic operation of an SRAM memory cell according to the present invention.

FIG. 6 is a circuit diagram of a full CMOS SRAM memory cell employing a memristor device as another embodiment of the present invention.

Claims (1)

In an SRAM memory cell, When a pair of memristor elements are added between the power supply voltage Vdd and the load element to block the power supply voltage Vdd supplied to the SRAM memory cell, the data present in the latch circuit of the SRAM memory cell is read. Storing the memory in the memristor device and restoring a value stored in the latch circuit of the SRAM memory cell by a resistance difference in the pair of memristor devices when the supply of the power supply voltage Vdd is resumed. A nonvolatile static random access memory cell employing a memristor element.
KR1020090078478A 2009-08-25 2009-08-25 Non-volatile static random access memory cell comprising memristor element KR20110020973A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097023A (en) * 2015-07-22 2015-11-25 宁波时代全芯科技有限公司 Non-volatile memory unit and non-volatile memory apparatus
KR20150139237A (en) * 2014-06-03 2015-12-11 제주대학교 산학협력단 Memory cell using memresistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150139237A (en) * 2014-06-03 2015-12-11 제주대학교 산학협력단 Memory cell using memresistor
CN105097023A (en) * 2015-07-22 2015-11-25 宁波时代全芯科技有限公司 Non-volatile memory unit and non-volatile memory apparatus
CN105097023B (en) * 2015-07-22 2017-12-12 江苏时代全芯存储科技有限公司 Nonvolatile storage unit and non-volatile memory

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