KR20110002318A - Semiconductor memory device and testing method thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a test method thereof are provided to prevent the malfunction of a test device by reducing a peak current which is generated in the test device. CONSTITUTION: A bank enable signal generating part(310) generates a plurality of bank enable signals in response to a compression test signal and an active signal. A plurality of memory banks are enabled in response to the plurality of bank enable signals. A delay part(330) comprises a plurality of delay units. The plurality of delay units outputs the plurality of bank enable signals having different delay time in response to the active signal.

Description

Semiconductor memory device and its test method {SEMICONDUCTOR MEMORY DEVICE AND TESTING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a semiconductor memory device and a test method thereof for enabling a plurality of memory banks to perform a test operation.

In general, as the process technology of semiconductor memory devices including DDR Double Data Rate Synchronous DRAM (DRAM) is rapidly developed, the density of internal circuits constituting the semiconductor memory device is increasing day by day. This high degree of integration allows more than tens of millions of memory cells to be provided in a semiconductor memory device, and the increase in memory cells has provided a foundation for storing more data. However, the increase in memory cells also increased the time spent testing them. Since the time spent performing the test is a factor in determining the cost of the product, various measures have been proposed to shorten it. One of them is the compression test mode. The compression test mode is a method of compressing and outputting stored data after storing desired data in a plurality of memory cells, and a tester can determine whether the memory cells are normal or defective based on the compressed and output compressed data. .

1 is a block diagram illustrating a part of a configuration of a conventional semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device includes a bank enable signal generator 110 and a memory region 130.

The bank enable signal generator 110 generates a plurality of bank enable signals EN_BK <0: 7> in response to the compression test signal TPARA and the active signal ACT. The compression test signal TPARA is a signal that is activated when the compression test mode is entered, and the active signal ACT is a signal that is activated during the active operation of the semiconductor memory device.

The memory area 130 includes a plurality of memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, each having a plurality of memory cells, and each memory bank BANK0, BANK1, BANK2, BANK3. , BANK4, BANK5, BANK6, BANK7 are enabled in response to each of the corresponding plurality of bank enable signals EN_BK <0: 7>.

FIG. 2 is a timing diagram for describing an operation waveform of each signal in the configuration of FIG. 1.

A compression test mode of a semiconductor memory device will be described with reference to FIGS. 1 and 2. First, when the compression test mode is entered, the compression test signal TPARA transitions from logic 'low' to logic 'high'. Thereafter, when the active signal ACT is activated, all of the bank enable signals EN_BK <0: 7> are activated by transitioning from logic 'low' to logic 'high'. The activated plurality of bank enable signals EN_BK <0: 7> enable the plurality of memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7.

Then, when multiple memory banks (BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7) are enabled, the test performer performs a plurality of memory banks (BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, Enter test data in BANK7). The data thus input is stored in a plurality of memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, and the test data thus stored is compressed and output through a data compression circuit (not shown). . The test performer may determine whether the memory cells are included in the memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 in a normal / defective manner based on the output compressed data.

As described above, in the compression test mode, the plurality of memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 are all enabled at one time in response to the active signal ACT. This causes the test equipment to have excessive peak current. That is, as many memory banks (BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7) are all enabled at one time, the required amount of current rapidly increases and excessive peaks are required for test equipment that must supply them. Current is generated. Excessive peak current causes a malfunction of the test equipment, and the malfunction of the test equipment cannot accurately determine the state of the semiconductor memory device to be tested. Furthermore, a false test result of normal can be detected with respect to a defective semiconductor memory device, which greatly reduces the reliability of the shipped semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of performing a test mode by sequentially enabling a plurality of memory banks.

In accordance with an aspect of the present invention, a semiconductor memory device includes: a plurality of memory banks enabled in response to a plurality of bank enable signals; And delay means for sequentially activating the plurality of bank enable signals in response to an active signal in a test mode.

In accordance with another aspect of the present invention, a semiconductor memory device includes: enable signal generation means for generating first and second bank enable signals in response to an active signal in a test mode; First and second delay means for delaying and outputting each of the first and second bank enable signals by a first and a second delay time; And a plurality of memory banks enabled in response to the signals output from the first and second delay means.

According to another aspect of the present invention, there is provided a semiconductor memory device, comprising: enable signal generation means for generating a source enable signal in response to an active signal in a test mode; Delay means for generating a plurality of bank enable signals by reflecting different delay times to the source enable signals; And a plurality of memory banks enabled in response to the plurality of bank enable signals.

According to another aspect of the present invention, there is provided a test method of a semiconductor memory device, the method comprising: generating a plurality of bank enable signals sequentially activated in a test mode; Enabling a plurality of memory banks in response to the plurality of bank enable signals; And inputting predetermined test data into the plurality of memory banks, compressing the predetermined test data, and outputting the compressed test data.

In the semiconductor memory device according to the embodiment of the present invention, by sequentially enabling the plurality of memory banks in the test mode, it is possible to reduce the peak current generated in the test equipment in the test mode.

According to the present invention, by enabling a plurality of memory banks sequentially in the test mode, the peak current generated in the test equipment is reduced, thereby preventing the malfunction of the test equipment.

In addition, the present invention can obtain the effect of accurately determining the memory cell state of the semiconductor memory device to be tested through the test result obtained through the stable compression test mode.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device includes a bank enable signal generator 310, a delay unit 330, and a memory region 350.

The bank enable signal generator 310 generates a plurality of bank enable signals EN_BK <0: 7> in response to the compression test signal TPARA and the active signal ACT. According to the first embodiment of the present invention, the 'EN_BK <0: 3>' bank enable signal of the plurality of bank enable signals EN_BK <0: 7> is transferred directly to the memory area 350 and the remaining 'EN_BK' The bank enable signal <4: 7> is transmitted to the delay unit 330.

The delay unit 330 delays the 'EN_BK <4: 7>' bank enable signal to generate a delayed bank enable signal D_EN_BK <4: 7>. Here, the delay unit 330 performs a delay operation on the input signal in response to the compression test signal TPARA. For reference, a circuit for transferring a plurality of bank enable signals EN_BK <0: 7> to the memory area 350 in a normal mode in order to perform an operation corresponding to a normal mode. (Not shown) is preferably provided, in which a plurality of bank enable signals EN_BK <0: 7> are activated corresponding to an address applied from the outside.

The memory area 350 includes a plurality of memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 each having a plurality of memory cells, and each memory bank BANK0, BANK1, BANK2, BANK3. , BANK4, BANK5, BANK6, BANK7) are enabled in response to each of the 'EN_BK <0: 3>' bank enable signal and the delayed bank enable signal D_EN_BK <4: 7>.

FIG. 4 is a timing diagram illustrating an operation waveform of each signal in the configuration of FIG. 3.

A compression test mode according to a first embodiment of the present invention will be described with reference to FIGS. 3 and 4. First, when the compression test mode is entered, the compression test signal TPARA transitions from logic 'low' to logic 'high'. Thereafter, when the active signal ACT is activated, all of the bank enable signals EN_BK <0: 7> are activated by transitioning from logic 'low' to logic 'high'. At this time, the 'EN_BK <4: 7>' bank enable signal is input to the delay unit 330 and output as a delayed bank enable signal D_EN_BK <4: 7> delayed by 'tD' time. Accordingly, among the memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, the 'BANK0', 'BANK1', BANK2 ', and' BANK3 'memory banks are divided into' EN_BK <0: 3> 'banks. Enabled by the enable signal, and after the 'tD' time, the 'BANK4', 'BANK5', 'BANK6', and 'BANK7' memory banks are enabled by the delayed bank enable signal (D_EN_BK <4: 7>). do.

Here, the memory banks' BANK0 ',' BANK1 ', BANK2', and 'BANK3' and the 'BANK4', 'BANK5', 'BANK6' and 'BANK7' memory banks are defined as one bank group, respectively. In an exemplary embodiment, one bank group of the plurality of memory banks BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, and BANK7 and the other bank group are sequentially enabled. This sequential enable operation reduces the peak current generated by the test equipment.

5 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, a semiconductor memory device includes a bank enable signal generator 510, a plurality of delay units 530, and a memory region 550. The bank enable signal generation unit 510 and the memory area 550 have already been described in the first embodiment of FIG. 3, and in the second embodiment, a plurality of delay units 530 are different from the first embodiment. lost.

The plurality of delay units 530 are used to reflect different delay times to each of the plurality of bank enable signals EN_BK <0: 7> output from the bank enable signal generator 510. To seventh delay parts 531 to 537. The first to seventh delay units 531, ..., 537 perform a delay operation on the input signal in response to the compression test signal TPARA, and the first to seventh delay units 531, ..., 537 are input. It is desirable to design a different delay time for the signal to be reflected.

FIG. 6 is a timing diagram for describing an operation waveform of each signal in the configuration of FIG. 5.

A compression test mode according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6.

When the active signal ACT is activated while the compression test mode is entered, that is, when the compression test signal TPARA is activated, the 'EN_BK <0>' bank enable signal is generated by the bank enable signal generator 510. The output is transferred to the memory area 550 to enable a corresponding memory bank (not shown). Here, the 'EN_BK <1: 7>' bank enable signal is also activated along with the 'EN_BK <0>' bank enable signal. In this case, the 'EN_BK <1: 7>' bank enable signal is input to a corresponding delay unit among the first to seventh delay units 531,..., 537, and the first to seventh delay units 531,..., 537. Outputs the delayed bank enable signal D_EN_BK <1: 7>. Since the delay times reflected by the first to seventh delay units 531 to 537 are different from each other, the delayed bank enable signals D_EN_BK <1: 7> may reflect different delay times. As shown in the figure, the 'D_EN_BK <1>' delayed bank enable signal is activated after 'tD1' in contrast to the 'EN_BK <0>' bank enable signal, and the 'D_EN_BK <7>' delayed bank enable signal is It is activated after 'tD7' in contrast to the 'EN_BK <0>' bank enable signal. Each bank included in the memory area 550 is enabled in response to an 'EN_BK <0>' bank enable signal having a different activation time point and a delayed bank enable signal D_EN_BK <1: 7>. As a result, this sequential enable operation reduces the peak current generated in the test equipment.

7 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to a third embodiment of the present invention.

Referring to FIG. 7, a semiconductor memory device includes a bank enable signal generator 510 and a plurality of delay units 730.

The bank enable signal generator 510 generates an 'EN_BK <0>' bank enable signal for enabling a corresponding memory bank among a plurality of memory banks (not shown) in the compression test mode. Here, the 'EN_BK <0>' bank enable signal is a source signal for generating the 'EN_BK <1: 7>' bank enable signal.

The plurality of delay units 730 are configured to generate the plurality of bank enable signals EN_BK <1: 7> by receiving the 'EN_BK <0>' bank enable signal. The first to seventh delay units connected in series are provided. 731, ..., 737 are provided. In this case, each of the first to seventh delay units 731 to 737 may be enabled in response to the compression test signal TPARA.

In the third embodiment of the present invention, as in the second embodiment, a plurality of bank enable signals EN_BK <0: 7> having different activation points can be obtained. The sequentially enabled bank enable signals EN_BK <0: 7> enable the memory banks sequentially, and the peak current generated in the test equipment is reduced by the sequential enable operations. .

As described above, in the first to third embodiments of the present invention, by sequentially activating a plurality of memory banks, it is possible to reduce the peak current generated in the test equipment. Reducing the peak current from the test equipment means that the semiconductor memory device under test can be tested more stably, and thus, it is possible to more accurately determine the state of the semiconductor memory device under test.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, in the above-described embodiment, the enabling of a plurality of memory banks in sequence has been described as an example. However, the present invention can be applied to a case in which all semiconductor memory devices operate at one time in the test equipment used to test a plurality of semiconductor memory devices, thereby eliminating the problem of increasing the peak current.

1 is a block diagram for explaining a part of a configuration of a conventional semiconductor memory device.

FIG. 2 is a timing diagram for explaining an operation waveform for each signal in the configuration of FIG. 1. FIG.

3 is a block diagram for explaining a part of a configuration of a semiconductor memory device according to the first embodiment of the present invention;

FIG. 4 is a timing diagram for describing an operation waveform of each signal in the configuration of FIG. 3. FIG.

FIG. 5 is a block diagram for explaining a part of a configuration of a semiconductor memory device according to a second embodiment of the present invention; FIG.

FIG. 6 is a timing diagram for describing an operation waveform for each signal in the configuration of FIG. 5. FIG.

FIG. 7 is a block diagram for explaining a part of a configuration of a semiconductor memory device according to a third embodiment of the present invention; FIG.

* Explanation of symbols for the main parts of the drawings

310: bank enable signal generator 330: delay unit

350 memory area

Claims (11)

A plurality of memory banks enabled in response to the plurality of bank enable signals; And Delay means for sequentially activating the plurality of bank enable signals in response to an active signal in a test mode A semiconductor memory device having a. The method of claim 1, The delay means, And a plurality of delay units for outputting the plurality of bank enable signals in which different delay times are reflected in response to the active signals. The method of claim 1, The plurality of memory banks are grouped into a predetermined number and divided into first and second bank groups, and the first and second bank groups are sequentially enabled in response to the plurality of bank enable signals. Memory device. Enable signal generation means for generating first and second bank enable signals in response to an active signal in a test mode; First and second delay means for delaying and outputting each of the first and second bank enable signals by a first and a second delay time; And A plurality of memory banks enabled in response to the signals output from the first and second delay means A semiconductor memory device having a. The method of claim 4, wherein And the first and second delay times have different delay times. Enable signal generation means for generating a source enable signal in response to an active signal in a test mode; Delay means for generating a plurality of bank enable signals by reflecting different delay times to the source enable signals; And A plurality of memory banks enabled in response to the plurality of bank enable signals A semiconductor memory device having a. The method of claim 6, The delay means, And a plurality of delay units connected in series and configured to receive the source enable signal and generate the plurality of bank enable signals. The method of claim 7, wherein Each of the plurality of memory banks is enabled in response to an output signal of the plurality of delay units. Generating a plurality of bank enable signals sequentially activated in the test mode; Enabling a plurality of memory banks in response to the plurality of bank enable signals; And Inputting predetermined test data into the plurality of memory banks, compressing the predetermined test data, and outputting the compressed test data; Test method of a semiconductor memory device comprising a. 10. The method of claim 9, The generating of the plurality of bank enable signals may include: Generating a plurality of enable signals in an active operation; And And outputting the plurality of bank enable signals by reflecting different delay times to each of the plurality of enable signals. 10. The method of claim 9, The generating of the plurality of bank enable signals may include: Generating a source enable signal in an active operation; And And outputting the plurality of bank enable signals by reflecting different delay times to the source enable signals.

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